clash-lib-1.0.0: prims/verilog/Clash_Explicit_BlockRam.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.blockRam#"
    , "kind" : "Declaration"
    , "type" :
"blockRam#
  :: ( KnownDomain dom        ARG[0]
     , HasCallStack  --       ARG[1]
     , Undefined a ) --       ARG[2]
  => Clock dom       -- clk,  ARG[3]
  => Enable dom      -- en,   ARG[4]
  -> Vec n a         -- init, ARG[5]
  -> Signal dom Int  -- rd,   ARG[6]
  -> Signal dom Bool -- wren, ARG[7]
  -> Signal dom Int  -- wr,   ARG[8]
  -> Signal dom a    -- din,  ARG[9]
  -> Signal dom a"
    , "outputReg" : true
    , "template" :
"// blockRam begin
reg ~TYPO ~GENSYM[~RESULT_RAM][1] [0:~LENGTH[~TYP[5]]-1];

reg ~TYP[5] ~GENSYM[ram_init][3];
integer ~GENSYM[i][4];
initial begin
  ~SYM[3] = ~CONST[5];
  for (~SYM[4]=0; ~SYM[4] < ~LENGTH[~TYP[5]]; ~SYM[4] = ~SYM[4] + 1) begin
    ~SYM[1][~LENGTH[~TYP[5]]-1-~SYM[4]] = ~SYM[3][~SYM[4]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
  end
end
~IF ~ISACTIVEENABLE[4] ~THEN
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~GENSYM[~RESULT_blockRam][5]~IF ~VIVADO ~THEN
  if (~ARG[4]) begin
    if (~ARG[7]) begin
      ~SYM[1][~ARG[8]] <= ~ARG[9];
    end
    ~RESULT <= ~SYM[1][~ARG[6]];
  end~ELSE
  if (~ARG[7] & ~ARG[4]) begin
    ~SYM[1][~ARG[8]] <= ~ARG[9];
  end
  if (~ARG[4]) begin
    ~RESULT <= ~SYM[1][~ARG[6]];
  end~FI
end~ELSE
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~SYM[5]
  if (~ARG[7]) begin
    ~SYM[1][~ARG[8]] <= ~ARG[9];
  end
  ~RESULT <= ~SYM[1][~ARG[6]];
end~FI
// blockRam end"
    }
  }
, { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.blockRamU#"
    , "kind" : "Declaration"
    , "type" :
"blockRamU#
  :: ( KnownDomain dom        ARG[0]
     , HasCallStack  --       ARG[1]
     , Undefined a ) --       ARG[2]
  => Clock dom       -- clk,  ARG[3]
  -> Enable dom      -- en,   ARG[4]
  -> SNat n          -- len,  ARG[5]
  -> Signal dom Int  -- rd,   ARG[6]
  -> Signal dom Bool -- wren, ARG[7]
  -> Signal dom Int  -- wr,   ARG[8]
  -> Signal dom a    -- din,  ARG[9]
  -> Signal dom a"
    , "outputReg" : true
    , "template" :
"// blockRamU begin
reg ~TYPO ~GENSYM[~RESULT_RAM][0] [0:~LIT[5]-1];

~IF ~ISACTIVEENABLE[4] ~THEN
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~GENSYM[~RESULT_blockRam][5]~IF ~VIVADO ~THEN
  if (~ARG[4]) begin
    if (~ARG[7]) begin
      ~SYM[0][~ARG[8]] <= ~ARG[9];
    end
    ~RESULT <= ~SYM[0][~ARG[6]];
  end~ELSE
  if (~ARG[7] & ~ARG[4]) begin
    ~SYM[0][~ARG[8]] <= ~ARG[9];
  end
  if (~ARG[4]) begin
    ~RESULT <= ~SYM[0][~ARG[6]];
  end~FI
end~ELSE
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~SYM[5]
  if (~ARG[7]) begin
    ~SYM[0][~ARG[8]] <= ~ARG[9];
  end
  ~RESULT <= ~SYM[0][~ARG[6]];
end~FI
// blockRamU end"
    }
  }
, { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.blockRam1#"
    , "kind" : "Declaration"
    , "type" :
"blockRam1#
  :: ( KnownDomain dom        ARG[0]
     , HasCallStack  --       ARG[1]
     , Undefined a ) --       ARG[2]
  => Clock dom       -- clk,  ARG[3]
  -> Enable dom      -- en,   ARG[4]
  -> SNat n          -- len,  ARG[5]
  -> a               -- init, ARG[6]
  -> Signal dom Int  -- rd,   ARG[7]
  -> Signal dom Bool -- wren, ARG[8]
  -> Signal dom Int  -- wr,   ARG[9]
  -> Signal dom a    -- din,  ARG[10]
  -> Signal dom a"
    , "outputReg" : true
    , "template" :
"// blockRam1 begin
reg ~TYPO ~GENSYM[~RESULT_RAM][0] [0:~LIT[5]-1];
integer ~GENSYM[i][1];
initial begin
    for (~SYM[1]=0;~SYM[1]<~LIT[5];~SYM[1]=~SYM[1]+1) begin
        ~SYM[0][~SYM[1]] = ~CONST[6];
    end
end

~IF ~ISACTIVEENABLE[4] ~THEN
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~GENSYM[~RESULT_blockRam][5]~IF ~VIVADO ~THEN
  if (~ARG[4]) begin
    if (~ARG[8]) begin
      ~SYM[0][~ARG[9]] <= ~ARG[10];
    end
    ~RESULT <= ~SYM[0][~ARG[7]];
  end~ELSE
  if (~ARG[8] & ~ARG[4]) begin
    ~SYM[0][~ARG[9]] <= ~ARG[10];
  end
  if (~ARG[4]) begin
    ~RESULT <= ~SYM[0][~ARG[7]];
  end~FI
end~ELSE
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~SYM[5]
  if (~ARG[8]) begin
    ~SYM[0][~ARG[9]] <= ~ARG[10];
  end
  ~RESULT <= ~SYM[0][~ARG[7]];
end~FI
// blockRam1 end"
    }
  }
]