clash-lib-1.0.0: prims/systemverilog/GHC_Classes.json

[ { "BlackBox" :
    { "name"      : "GHC.Classes.divInt#"
    , "kind"      : "Declaration"
    , "type"      : "divInt# :: Int# -> Int# -> Int#"
    , "template"  :
"// divInt# begin
// divide (rounds towards zero)
~SIGD[~GENSYM[quot_res][0]][0];
assign ~SYM[0] = ~VAR[dividend][0] / ~VAR[divider][1];

// round toward minus infinity
assign ~RESULT = (~VAR[dividend][0][~SIZE[~TYPO]-1] == ~VAR[divider][1][~SIZE[~TYPO]-1]) ? ~SYM[0] : ~SYM[0] - ~SIZE[~TYPO]'sd1;
// divInt# end"
    }
  }
, { "BlackBox" :
    { "name"      : "GHC.Classes.modInt#"
    , "kind"      : "Declaration"
    , "type"      : "modInt# :: Int# -> Int# -> Int#"
    , "template"  :
"// modInt# begin
// remainder
~SIGD[~GENSYM[rem_res][0]][0];
assign ~SYM[0] = ~VAR[dividend][0] % ~VAR[divider][1];

// modulo
assign ~RESULT = (~VAR[dividend][0][~SIZE[~TYPO]-1] == ~VAR[divider][1][~SIZE[~TYPO]-1]) ?
                 ~SYM[0] :
                 ((~VAR[dividend][0] == ~SIZE[~TYPO]'sd0) ? ~SIZE[~TYPO]'sd0 : ~SYM[0] + ~VAR[divider][1]);
// modInt# end"
    }
  }
]