Clash_Explicit_RAM.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.RAM.asyncRam#"
    , "kind" : "Declaration"
    , "type" :
"asyncRam#
  :: ( HasCallStack              -- ARG[0]
     , KnownDomain wdom wconf    -- ARG[1]
     , KnownDomain rdom rconf )  -- ARG[2]
  => Clock wdom                  -- ^ wclk, ARG[3]
  -> Clock rdom                  -- ^ rclk, ARG[4]
  -> Enable wdom                 -- ^ wen,  ARG[5]
  -> SNat n                      -- ^ sz,   ARG[6]
  -> Signal rdom Int             -- ^ rd,   ARG[7]
  -> Signal wdom Bool            -- ^ en,   ARG[8]
  -> Signal wdom Int             -- ^ wr,   ARG[9]
  -> Signal wdom a               -- ^ din,  ARG[10]
  -> Signal rdom a"
    , "template" :
"// asyncRam begin
logic [~SIZE[~TYP[10]]-1:0] ~GENSYM[RAM][0] [0:~LIT[6]-1];
always @(~IF~ACTIVEEDGE[Rising][1]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~GENSYM[~COMPNAME_Ram][1]
  if (~IF ~ISACTIVEENABLE[5] ~THEN ~ARG[5] & ~ELSE ~FI ~ARG[8]) begin
    ~SYM[0][~ARG[9]] <= ~TOBV[~ARG[10]][~TYP[10]];
  end
end

assign ~RESULT = ~FROMBV[~SYM[0][\\~ARG[7]\\]][~TYPO];
// asyncRam end"
    }
  }
]