clash-lib-1.0.0: prims/commonverilog/Clash_Xilinx_ClockGen.json
[ { "BlackBox" :
{ "name" : "Clash.Xilinx.ClockGen.clockWizard"
, "workInfo" : "Always"
, "kind" : "Declaration"
, "type" :
"clockWizard
:: ( KnownDomain domIn confIn -- ARG[0]
, KnownDomain domOut confOut ) -- ARG[1]
=> SSymbol name -- ARG[2]
-> Clock pllIn -- ARG[3]
-> Reset pllIn -- ARG[4]
-> (Clock pllOut, Enable pllOut)"
, "template" :
"// clockWizard begin
~NAME[2] ~GENSYM[clockWizard_inst][2]
(.CLK_IN1 (~ARG[3])
,.RESET (~IF ~ISACTIVEHIGH[0] ~THEN ~ELSE ! ~FI ~ARG[4])
,.CLK_OUT1 (~RESULT[1])
,.LOCKED (~RESULT[0]));
// clockWizard end"
}
}
, { "BlackBox" :
{ "name" : "Clash.Xilinx.ClockGen.clockWizardDifferential"
, "workInfo" : "Always"
, "kind" : "Declaration"
, "type" :
"clockWizardDifferential
:: ( KnownDomain domIn confIn -- ARG[0]
, KnownDomain domOut confOut ) -- ARG[1]
:: SSymbol name -- ARG[2]
-> Clock pllIn -- ARG[3]
-> Clock pllIn -- ARG[4]
-> Reset pllIn -- ARG[5]
-> (Clock pllOut, Enable pllOut)"
, "template" :
"// clockWizardDifferential begin
~NAME[2] ~GENSYM[clockWizardDifferential_inst][2]
(.CLK_IN1_D_clk_n (~ARG[3])
,.CLK_IN1_D_clk_n (~ARG[4])
,.RESET (~IF ~ISACTIVEHIGH[0] ~THEN ~ELSE ! ~FI ~ARG[5])
,.CLK_OUT1 (~RESULT[1])
,.LOCKED (~RESULT[0]));
// clockWizardDifferential end"
}
}
]