clash-lib-0.99: prims/vhdl/Clash_Sized_Internal_BitVector.json
[ { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.size#"
, "type" : "size# :: KnownNat n => BitVector n -> Int"
, "templateE" : "to_signed(~LIT[0],~SIZE[~TYPO])"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.maxIndex#"
, "type" : "maxIndex# :: KnownNat n => BitVector n -> Int"
, "templateE" : "to_signed(~LIT[0] - 1,~SIZE[~TYPO])"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.high"
, "type" : "high :: Bit"
, "templateE" : "'1'"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.low"
, "type" : "low :: Bit"
, "templateE" : "'0'"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.pack#"
, "type" : "pack# :: Bit -> BitVector 1"
, "templateE" : "std_logic_vector'(0 => ~ARG[0])"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.unpack#"
, "type" : "unpack# :: BitVector 1 -> Bit"
, "templateE" : "~VAR[bv][0](0)"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.eq##"
, "type" : "eq## :: Bit -> Bit -> Bool"
, "templateE" : "~ARG[0] = ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.neq##"
, "type" : "neq## :: Bit -> Bit -> Bool"
, "templateE" : "~ARG[0] /= ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.lt##"
, "type" : "lt## :: Bit -> Bit -> Bool"
, "templateE" : "~ARG[0] < ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.ge##"
, "type" : "ge## :: Bit -> Bit -> Bool"
, "templateE" : "~ARG[0] >= ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.gt##"
, "type" : "gt## :: Bit -> Bit -> Bool"
, "templateE" : "~ARG[0] > ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.le##"
, "type" : "le## :: Bit -> Bit -> Bool"
, "templateE" : "~ARG[0] <= ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.fromInteger##"
, "type" : "fromInteger# :: Integer -> Bit"
, "templateE" : "~VAR[i][0](0)"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.and##"
, "type" : "and## :: Bit -> Bit -> Bit"
, "templateE" : "~ARG[0] and ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.or##"
, "type" : "or## :: Bit -> Bit -> Bit"
, "templateE" : "~ARG[0] or ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.xor##"
, "type" : "xor## :: Bit -> Bit -> Bit"
, "templateE" : "~ARG[0] xor ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.complement##"
, "type" : "complement## :: Bit -> Bit"
, "templateE" : "not ~ARG[0]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.++#"
, "type" : "(++#) :: KnownNat m => BitVector n -> BitVector m -> BitVector (n + m)"
, "templateE" : "std_logic_vector'(std_logic_vector'(~ARG[1]) & std_logic_vector'(~ARG[2]))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.reduceAnd#"
, "type" : "reduceAnd# :: KnownNat n => BitVector n -> Bit"
, "templateD" :
"-- reduceAnd begin
~GENSYM[reduceAnd][0] : block
function and_reduce (arg : std_logic_vector) return std_logic is
variable upper, lower : std_logic;
variable half : integer;
variable argi : std_logic_vector (arg'length - 1 downto 0);
variable result : std_logic;
begin
if (arg'length < 1) then
result := '1';
else
argi := arg;
if (argi'length = 1) then
result := argi(argi'left);
else
half := (argi'length + 1) / 2; -- lsb-biased tree
upper := and_reduce (argi (argi'left downto half));
lower := and_reduce (argi (half - 1 downto argi'right));
result := upper and lower;
end if;
end if;
return result;
end;
begin
~RESULT <= and_reduce(~ARG[1]);
end block;
-- reduceAnd end"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.reduceOr#"
, "type" : "reduceOr# :: BitVector n -> Bit"
, "templateD" :
"-- reduceOr begin
~GENSYM[reduceOr][0] : block
function or_reduce (arg : std_logic_vector) return std_logic is
variable upper, lower : std_logic;
variable half : integer;
variable argi : std_logic_vector (arg'length - 1 downto 0);
variable result : std_logic;
begin
if (arg'length < 1) then
result := '0';
else
argi := arg;
if (argi'length = 1) then
result := argi(argi'left);
else
half := (argi'length + 1) / 2; -- lsb-biased tree
upper := or_reduce (argi (argi'left downto half));
lower := or_reduce (argi (half - 1 downto argi'right));
result := upper or lower;
end if;
end if;
return result;
end;
begin
~RESULT <= or_reduce(~ARG[0]);
end block;
-- reduceOr end"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.reduceXor#"
, "type" : "reduceXor# :: BitVector n -> Bit"
, "templateD" :
"-- reduceXor begin
~GENSYM[reduceXor][0] : block
function xor_reduce (arg : std_logic_vector) return std_logic is
variable upper, lower : std_logic;
variable half : integer;
variable argi : std_logic_vector (arg'length - 1 downto 0);
variable result : std_logic;
begin
if (arg'length < 1) then
result := '0';
else
argi := arg;
if (argi'length = 1) then
result := argi(argi'left);
else
half := (argi'length + 1) / 2; -- lsb-biased tree
upper := xor_reduce (argi (argi'left downto half));
lower := xor_reduce (argi (half - 1 downto argi'right));
result := upper xor lower;
end if;
end if;
return result;
end;
begin
~RESULT <= xor_reduce(~ARG[0]);
end block;
-- reduceXor end"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.index#"
, "type" :
"index# :: KnownNat n -- ARG[0]
=> BitVector n -- ARG[1]
-> Int -- ARG[2]
-> Bit"
, "templateD" :
"-- indexBitVector begin~IF ~ISVAR[1] ~THEN
~GENSYM[indexBitVector][0] : block
signal ~GENSYM[vec_index][1] : integer range 0 to ~LIT[0]-1;
begin
~SYM[1] <= to_integer(~ARG[2])
-- pragma translate_off
mod ~LIT[0]
-- pragma translate_on
;
~RESULT <= ~ARG[1](~SYM[1]);
end block;~ELSE
~SYM[0] : block
signal ~SYM[1] : integer range 0 to ~LIT[0]-1;
begin
~SYM[1] <= to_integer(~ARG[2])
-- pragma translate_off
mod ~LIT[0]
-- pragma translate_on
;
~RESULT <= ~VAR[bv][1](~SYM[1]);
end block;~FI
-- indexBitVector end"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.replaceBit#"
, "type" :
"replaceBit# :: KnownNat n -- ARG[0]
=> BitVector n -- ARG[1]
-> Int -- ARG[2]
-> Bit -- ARG[3]
-> BitVector n"
, "templateD" :
"-- replaceBit begin
~GENSYM[replaceBit][0] : block
signal ~GENSYM[vec_index][1] : integer range 0 to ~LIT[0]-1;
begin
~SYM[1] <= to_integer(~ARG[2])
-- pragma translate_off
mod ~LIT[0]
-- pragma translate_on
;
process(~SYM[1],~VAR[b][3]~VARS[1])
variable ~GENSYM[ivec][2] : ~TYP[1];
begin
~SYM[2] := ~ARG[1];
~SYM[2](~SYM[1]) := ~ARG[3];
~RESULT <= ~SYM[2];
end process;
end block;
-- replaceBit end"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.setSlice#"
, "type" :
"setSlice# :: BitVector (m + 1 + i) -- ARG[0]
-> SNat m -- ARG[1]
-> SNat n -- ARG[2]
-> BitVector (m + 1 - n) -- ARG[3]
-> BitVector (m + 1 + i)"
, "templateD" :
"-- setSlice begin
~GENSYM[setSlice][0] : process(~VAR[bv][0]~VARS[3])
variable ~GENSYM[ivec][1] : ~TYP[0];
begin
~SYM[1] := ~ARG[0];
~SYM[1](~LIT[1] downto ~LIT[2]) := ~VAR[bv][3];
~RESULT <= ~SYM[1];
end process;
-- setSlice end"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.slice#"
, "type" :
"slice# :: BitVector (m + 1 + i) -- ARG[0]
-> SNat m -- ARG[1]
-> SNat n -- ARG[2]
-> BitVector (m + 1 - n)"
, "templateE" : "~VAR[bv][0](~LIT[1] downto ~LIT[2])"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.split#"
, "type" :
"split# :: KnownNat n -- ARG[0]
=> BitVector (m + n) -- ARG[1]
-> (BitVector m, BitVector n)"
, "templateE" : "(~VAR[bv][1](~VAR[bv][1]'high downto ~LIT[0]),~VAR[bv][1](~LIT[0]-1 downto 0))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.msb#"
, "type" :
"msb# :: KnownNat n -- ARG[0]
=> BitVector n -- ARG[1]
-> Bit"
, "templateE" : "~IF ~LIT[0] ~THEN ~VAR[bv][1](~VAR[bv][1]'high) ~ELSE \"0\" ~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.lsb#"
, "type" :
"lsb# :: BitVector n -- ARG[0]
-> Bit"
, "templateE" : "~IF ~SIZE[~TYP[0]] ~THEN ~VAR[bv][0](0) ~ELSE \"0\" ~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.eq#"
, "type" : "eq# :: BitVector n -> BitVector n -> Bool"
, "templateE" : "~IF~SIZE[~TYP[0]]~THEN~ARG[0] = ~ARG[1]~ELSEtrue~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.neq#"
, "type" : "neq# :: BitVector n -> BitVector n -> Bool"
, "templateE" : "~IF~SIZE[~TYP[0]]~THEN~ARG[0] /= ~ARG[1]~ELSEfalse~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.lt#"
, "type" : "lt# :: BitVector n -> BitVector n -> Bool"
, "templateE" : "~IF~SIZE[~TYP[0]]~THEN~ARG[0] < ~ARG[1]~ELSEfalse~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.ge#"
, "type" : "ge# :: BitVector n -> BitVector n -> Bool"
, "templateE" : "~IF~SIZE[~TYP[0]]~THEN~ARG[0] >= ~ARG[1]~ELSEtrue~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.gt#"
, "type" : "gt# :: BitVector n -> BitVector n -> Bool"
, "templateE" : "~IF~SIZE[~TYP[0]]~THEN~ARG[0] > ~ARG[1]~ELSEfalse~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.le#"
, "type" : "le# :: BitVector n -> BitVector n -> Bool"
, "templateE" : "~IF~SIZE[~TYP[0]]~THEN~ARG[0] <= ~ARG[1]~ELSEtrue~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.minBound#"
, "type" : "minBound# :: BitVector n"
, "templateE" : "~IF~SIZE[~TYPO]~THENstd_logic_vector'(~SIZE[~TYPO]-1 downto 0 => '0')~ELSEstd_logic_vector'(0 downto 1 => '0')~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.maxBound#"
, "type" : "maxBound# :: KnownNat n => BitVector n"
, "templateE" : "~IF~SIZE[~TYPO]~THENstd_logic_vector'(~SIZE[~TYPO]-1 downto 0 => '1')~ELSEstd_logic_vector'(0 downto 1 => '1')~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.+#"
, "type" : "(+#) :: KnownNat n => BitVector n -> BitVector n -> BitVector n"
, "templateE" : "std_logic_vector(unsigned(~ARG[1]) + unsigned(~ARG[2]))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.-#"
, "type" : "(-#) :: KnownNat n => BitVector n -> BitVector n -> BitVector n"
, "templateE" : "std_logic_vector(unsigned(~ARG[1]) - unsigned(~ARG[2]))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.*#"
, "type" : "(*#) :: KnownNat n => BitVector n -> BitVector n -> BitVector n"
, "templateE" : "std_logic_vector(resize(unsigned(~ARG[1]) * unsigned(~ARG[2]), ~LIT[0]))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.negate#"
, "type" : "negate# :: KnownNat n => BitVector n -> BitVector n"
, "templateE" : "std_logic_vector(-(signed(~ARG[1])))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.fromInteger#"
, "type" : "fromInteger# :: KnownNat n => Integer -> BitVector n"
, "templateE" : "std_logic_vector(resize(unsigned(std_logic_vector(~ARG[1])),~LIT[0]))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.plus#"
, "type" : "plus# :: BitVector m -> BitVector n -> BitVector (Max m n + 1)"
, "templateE" : "std_logic_vector(resize(unsigned(~ARG[0]),~SIZE[~TYPO]) + resize(unsigned(~ARG[1]),~SIZE[~TYPO]))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.minus#"
, "type" : "minus# :: (KnownNat m, KnownNat n) => BitVector m -> BitVector n -> BitVector (Max m n + 1)"
, "templateE" : "std_logic_vector(resize(unsigned(~ARG[2]),~SIZE[~TYPO]) - resize(unsigned(~ARG[3]),~SIZE[~TYPO]))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.times#"
, "type" : "times# :: BitVector m -> BitVector n -> BitVector (m + n)"
, "templateE" : "std_logic_vector(unsigned(~ARG[0]) * unsigned(~ARG[1]))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.quot#"
, "type" : "quot# :: BitVector n -> BitVector n -> BitVector n"
, "templateE" : "std_logic_vector(unsigned(~ARG[0]) / unsigned(~ARG[1]))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.rem#"
, "type" : "rem# :: BitVector n -> BitVector n -> BitVector n"
, "templateE" : "std_logic_vector(unsigned(~ARG[0]) rem unsigned(~ARG[1]))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.toInteger#"
, "type" : "toInteger# :: BitVector n -> Integer"
, "templateE" : "~IF~SIZE[~TYP[0]]~THENsigned(std_logic_vector(resize(unsigned(~ARG[0]),~SIZE[~TYPO])))~ELSEto_signed(0,64)~FI"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.and#"
, "type" : "and# :: BitVector n -> BitVector n -> BitVector n"
, "templateE" : "~ARG[0] and ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.or#"
, "type" : "or# :: BitVector n -> BitVector n -> BitVector n"
, "templateE" : "~ARG[0] or ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.xor#"
, "type" : "xor# :: BitVector n -> BitVector n -> BitVector n"
, "templateE" : "~ARG[0] xor ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.complement#"
, "type" : "complement# :: KnownNat n => BitVector n -> BitVector n"
, "templateE" : "not ~ARG[1]"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.shiftL#"
, "type" : "shiftL# :: KnownNat n => BitVector n -> Int -> BitVector n"
, "templateE" : "std_logic_vector(shift_left(unsigned(~ARG[1]),to_integer(~ARG[2])))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.shiftR#"
, "type" : "shiftR# :: KnownNat n => BitVector n -> Int -> BitVector n"
, "templateE" : "std_logic_vector(shift_right(unsigned(~ARG[1]),to_integer(~ARG[2])))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.rotateL#"
, "type" : "rotateL# :: KnownNat n => BitVector n -> Int -> BitVector n"
, "templateE" : "std_logic_vector(rotate_left(unsigned(~ARG[1]),to_integer(~ARG[2])))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.rotateR#"
, "type" : "rotateR# :: KnownNat n => BitVector n -> Int -> BitVector n"
, "templateE" : "std_logic_vector(rotate_right(unsigned(~ARG[1]),to_integer(~ARG[2])))"
}
}
, { "BlackBox" :
{ "name" : "Clash.Sized.Internal.BitVector.resize#"
, "type" : "resize# :: KnownNat m => BitVector n -> BitVector m"
, "templateE" : "std_logic_vector(resize(unsigned(~ARG[1]),~LIT[0]))"
}
}
]