clash-lib-0.99: prims/vhdl/Clash_Signal_Internal.json
[ { "BlackBox" :
{ "name" : "Clash.Signal.Internal.delay#"
, "type" :
"register#
:: HasCallStack -- ARG[0]
=> Clock domain gated -- ARG[1]
-> Signal clk a -- ARG[2]
-> Signal clk a"
, "templateD" :
"-- register begin~IF ~ISGATED[1] ~THEN
~GENSYM[~COMPNAME_delay][0] : block
signal ~GENSYM[clk][1] : std_logic;
signal ~GENSYM[ce][2] : boolean;
begin
(~SYM[1],~SYM[2]) <= ~ARG[1];
~GENSYM[~COMPNAME_dly][3] : process(~SYM[1])
begin
if rising_edge(~SYM[1]) then
if ~SYM[2] then
~RESULT <= ~ARG[2]
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
end if;
end if;
end process;
end block;~ELSE
~SYM[0] : process(~ARG[1])
begin
if rising_edge(~ARG[1]) then
~RESULT <= ~ARG[2]
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
end if;
end process;~FI
-- register end"
}
}
, { "BlackBox" :
{ "name" : "Clash.Signal.Internal.register#"
, "type" :
"register#
:: HasCallStack -- ARG[0]
=> Clock domain gated -- ARG[1]
-> Reset domain synchronous -- ARG[2]
-> a -- ARG[3]
-> Signal clk a -- ARG[4]
-> Signal clk a"
, "templateD" :
"-- register begin~IF ~ISGATED[1] ~THEN
~GENSYM[~COMPNAME_register][0] : block
signal ~GENSYM[clk][1] : std_logic;
signal ~GENSYM[ce][2] : boolean;
begin
(~SYM[1],~SYM[2]) <= ~ARG[1];~IF ~ISSYNC[2] ~THEN
~GENSYM[~COMPNAME_reg][3] : process(~SYM[1])
begin
if rising_edge(~SYM[1]) then
if ~ARG[2] = '1' then
~RESULT <= ~ARG[3]
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
elsif ~SYM[2] then
~RESULT <= ~ARG[4]
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
end if;
end if;
end process;~ELSE
~SYM[3] : process(~SYM[1],~ARG[2]~VARS[3])
begin
if ~ARG[2] = '1' then
~RESULT <= ~ARG[3];
elsif rising_edge(~SYM[1]) then
if ~SYM[2] then
~RESULT <= ~ARG[4]
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
end if;
end if;
end process;~FI
end block;~ELSE ~IF ~ISSYNC[2] ~THEN
~SYM[0] : process(~ARG[1])
begin
if rising_edge(~ARG[1]) then
if ~ARG[2] = '1' then
~RESULT <= ~ARG[3]
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
else
~RESULT <= ~ARG[4]
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
end if;
end if;
end process;~ELSE
~SYM[0] : process(~ARG[1],~ARG[2]~VARS[3])
begin
if ~ARG[2] = '1' then
~RESULT <= ~ARG[3]
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
elsif rising_edge(~ARG[1]) then
~RESULT <= ~ARG[4]
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
end if;
end process;~FI~FI
-- register end"
}
}
, { "BlackBox" :
{ "name" : "Clash.Signal.Internal.clockGate"
, "type" :
"clockGate
:: Clock domain gated -- ARG[0]
-> Signal domain Bool -- ARG[1]
-> Clcok domain 'Gated"
, "templateD" :
"-- clockGate begin~IF ~ISGATED[0] ~THEN
~RESULT <= (~ARG[0].~TYPM[0]_sel0,~ARG[0].~TYPM[0]_sel1 and ~ARG[1]);~ELSE
~RESULT <= (~ARG[0],~ARG[1]);~FI
-- clockGate end"
}
}
, { "BlackBox" :
{ "name" : "Clash.Signal.Internal.clockGen"
, "type" :
"clockGen
:: (domain ~ Dom nm period -- ARG[0]
,KnownSymbol nm -- ARG[1]
,KnownNat period) -- ARG[2]
=> Clock domain Source"
, "templateD" :
"-- pragma translate_off
~GENSYM[clkGen][0] : process is
constant ~GENSYM[half_period][1] : time := ~LIT[2]0 ps / 2;
begin
~RESULT <= '0';
wait for 3000 ps;
loop
~RESULT <= not ~RESULT;
wait for ~SYM[1];
~RESULT <= not ~RESULT;
wait for ~SYM[1];
end loop;
wait;
end process;
-- pragma translate_on"
}
}
, { "BlackBox" :
{ "name" : "Clash.Signal.Internal.tbClockGen"
, "type" :
"tbClockGen
:: (domain ~ Dom nm period -- ARG[0]
,KnownSymbol nm -- ARG[1]
,KnownNat period) -- ARG[2]
=> Signal domain Bool -- ARG[3]
-> Clock domain Source"
, "templateD" :
"-- pragma translate_off
~GENSYM[clkGen][0] : process is
constant ~GENSYM[half_period][1] : time := ~LIT[2]0 ps / 2;
begin
~RESULT <= '0';
wait for 3000 ps;
while ~ARG[3] loop
~RESULT <= not ~RESULT;
wait for ~SYM[1];
~RESULT <= not ~RESULT;
wait for ~SYM[1];
end loop;
wait;
end process;
-- pragma translate_on"
}
}
, { "BlackBox" :
{ "name" : "Clash.Signal.Internal.asyncResetGen"
, "type" :
"asyncResetGen :: Reset domain 'Asynchronous"
, "templateD" :
"-- pragma translate_off
~RESULT <= '1',
'0' after 2000 ps;
-- pragma translate_on"
}
}
, { "BlackBox" :
{ "name" : "Clash.Signal.Internal.syncResetGen"
, "type" :
"syncResetGen :: ( domain ~ 'Dom n clkPeriod
, KnownNat clkPeriod )
=> Reset domain 'Synchronous"
, "templateD" :
"-- pragma translate_off
~RESULT <= '1',
'0' after (2999 ps + ~LIT[1]0 ps);
-- pragma translate_on"
}
}
, { "BlackBox" :
{ "name" : "Clash.Signal.Internal.unsafeFromAsyncReset"
, "type" :
"unsafeFromAsyncReset :: Reset domain Asynchronous -> Signal domain Bool"
, "templateD" : "~RESULT <= true when ~ARG[0] = '1' else false;"
}
}
, { "BlackBox" :
{ "name" : "Clash.Signal.Internal.unsafeToAsyncReset"
, "type" :
"unsafeToAsyncReset :: Signal domain Bool -> Reset domain Asynchronous"
, "templateD" : "~RESULT <= '1' when ~ARG[0] else '0';"
}
}
, { "BlackBox" :
{ "name" : "Clash.Signal.Internal.fromSyncReset"
, "type" :
"fromSyncReset :: Reset domain Synchronous -> Signal domain Bool"
, "templateD" : "~RESULT <= true when ~ARG[0] = '1' else false;"
}
}
, { "BlackBox" :
{ "name" : "Clash.Signal.Internal.unsafeToSyncReset"
, "type" :
"unsafeToSyncReset :: Signal domain Bool -> Reset domain Synchronous"
, "templateD" : "~RESULT <= '1' when ~ARG[0] else '0';"
}
}
, { "Primitive" :
{ "name" : "Clash.Signal.Internal.signal#"
, "primType" : "Function"
}
}
, { "Primitive" :
{ "name" : "Clash.Signal.Internal.mapSignal#"
, "primType" : "Function"
}
}
, { "Primitive" :
{ "name" : "Clash.Signal.Internal.appSignal#"
, "primType" : "Function"
}
}
, { "Primitive" :
{ "name" : "Clash.Signal.Internal.foldr#"
, "primType" : "Function"
}
}
, { "Primitive" :
{ "name" : "Clash.Signal.Internal.traverse#"
, "primType" : "Function"
}
}
, { "Primitive" :
{ "name" : "Clash.Signal.Internal.joinSignal#"
, "primType" : "Function"
}
}
]