clash-lib-0.99: prims/vhdl/Clash_Intel_ClockGen.json

[ { "BlackBox" :
    { "name"      : "Clash.Intel.ClockGen.altpll"
    , "type"      :
"altpll
  :: SSymbol name               -- ARG[0]
  -> Clock  pllIn 'Source       -- ARG[1]
  -> Reset  pllIn 'Asynchronous -- ARG[2]
  -> (Clock pllOut 'Source, Signal pllOut Bool)"
    , "templateD" :
"-- altpll begin
~GENSYM[altpll][0] : block
  signal ~GENSYM[pllOut][1]  : std_logic;
  signal ~GENSYM[locked][2]  : std_logic;
  signal ~GENSYM[pllLock][3] : boolean;

  component ~NAME[0]
    port (inclk0 : in std_logic;
          areset : in std_logic;
          c0     : out std_logic;
          locked : out std_logic);
  end component;
begin
  ~GENSYM[altpll_inst][4] : component ~NAME[0] port map (~ARG[1],~ARG[2],~SYM[1],~SYM[2]);
  ~SYM[3] <= true when ~SYM[2] = '1' else false;
  ~RESULT <= (~SYM[1],~SYM[3]);
end block;
-- altpll end"
    }
  }
, { "BlackBox" :
    { "name"      : "Clash.Intel.ClockGen.alteraPll"
    , "type"      :
"alteraPll
  :: SSymbol name               -- ARG[0]
  -> Clock  pllIn 'Source       -- ARG[1]
  -> Reset  pllIn 'Asynchronous -- ARG[2]
  -> (Clock pllOut 'Source, Signal pllOut Bool)"
    , "templateD" :
"-- alteraPll begin
~GENSYM[alteraPll][0] : block
  signal ~GENSYM[pllOut][1]  : std_logic;
  signal ~GENSYM[locked][2]  : std_logic;
  signal ~GENSYM[pllLock][3] : boolean;

  component ~NAME[0]
    port (refclk   : in std_logic;
          rst      : in std_logic;
          outclk_0 : out std_logic;
          locked   : out std_logic);
  end component;
begin
  ~GENSYM[alteraPll_inst][4] : component ~NAME[0] port map (~ARG[1],~ARG[2],~SYM[1],~SYM[2]);
  ~SYM[3] <= true when ~SYM[2] = '1' else false;
  ~RESULT <= (~SYM[1],~SYM[3]);
end block;
-- alteraPll end"
    }
  }
]