clash-lib-0.99: prims/vhdl/Clash_Explicit_ROM.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.ROM.rom#"
    , "type" :
"rom# :: KnownNat n      -- ARG[0]
      => Clock dom gated -- clk,  ARG[1]
      -> Vec n a         -- init, ARG[2]
      -> Signal dom Int  -- rd,   ARG[3]
      -> Signal dom a"
    , "templateD" :
"-- rom begin
~GENSYM[~COMPNAME_rom][0] : block
  signal ~GENSYM[ROM][1] : ~TYP[2];
  signal ~GENSYM[rd][2] : integer range 0 to ~LIT[0]-1;~IF ~ISGATED[1] ~THEN
  signal ~GENSYM[clk][3] : std_logic;
  signal ~GENSYM[ce][4]  : boolean;~ELSE ~FI
begin
  ~SYM[1] <= ~ARG[2];

  ~SYM[2] <= to_integer(~ARG[3])
  -- pragma translate_off
                mod ~LIT[0]
  -- pragma translate_on
                ;
  ~IF ~ISGATED[1] ~THEN
  (~SYM[3],~SYM[4]) <= ~ARG[1];
  ~GENSYM[romSync][5] : process (~SYM[3])
  begin
    if (rising_edge(~SYM[3])) then
      if ~SYM[4] then~IF ~VIVADO ~THEN
        ~RESULT <= ~FROMBV[~SYM[1](~SYM[2])][~TYPO]
        -- pragma translate_off
        after 1 ps
        -- pragma translate_on
        ;~ELSE
        ~RESULT <= ~SYM[1](~SYM[2])
        -- pragma translate_off
        after 1 ps
        -- pragma translate_on
        ;~FI
      end if;
    end if;
  end process;~ELSE
  ~SYM[5] : process (~ARG[1])
  begin
    if (rising_edge(~ARG[1])) then~IF ~VIVADO ~THEN
      ~RESULT <= ~FROMBV[~SYM[1](~SYM[2])][~TYPO]
      -- pragma translate_off
      after 1 ps
      -- pragma translate_on
      ;~ELSE
      ~RESULT <= ~SYM[1](~SYM[2])
      -- pragma translate_off
      after 1 ps
      -- pragma translate_on
      ;~FI
    end if;
  end process;~FI
end block;
-- rom end"
    }
  }
]