clash-lib-0.99: prims/verilog/GHC_Base.json

[ { "Primitive" :
    { "name"      : "GHC.Base.$"
    , "primType"  : "Function"
    }
  }
, { "BlackBox" :
    { "name"      : "GHC.Base.quotInt"
    , "type"      : "quotInt :: Int -> Int -> Int"
    , "templateE" : "~ARG[0] / ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "GHC.Base.remInt"
    , "type"      : "remInt :: Int -> Int -> Int"
    , "templateE" : "~ARG[0] % ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "GHC.Base.divInt"
    , "type"      : "divInt :: Int -> Int -> Int"
    , "templateD" :
"// divInt begin
// divide (rounds towards zero)
wire ~SIGD[~GENSYM[quot_res][0]][0];
assign ~SYM[0] = ~VAR[dividend][0] / ~VAR[divider][1];

// round toward minus infinity
assign ~RESULT = (~VAR[dividend][0][~SIZE[~TYPO]-1] == ~VAR[divider][1][~SIZE[~TYPO]-1]) ? ~SYM[0] : ~SYM[0] - ~SIZE[~TYPO]'sd1;
// divInt end"
    }
  }
, { "BlackBox" :
    { "name"      : "GHC.Base.modInt"
    , "type"      : "modInt :: Int -> Int -> Int"
    , "templateD" :
"// modInt begin
// remainder
wire ~SIGD[~GENSYM[rem_res][0]][0];
assign ~SYM[0] = ~VAR[dividend][0] % ~VAR[divider][1];

// modulo
assign ~RESULT = (~VAR[dividend][0][~SIZE[~TYPO]-1] == ~VAR[divider][1][~SIZE[~TYPO]-1]) ?
                 ~SYM[0] :
                 ((~VAR[dividend][0] == ~SIZE[~TYPO]'sd0) ? ~SIZE[~TYPO]'sd0 : ~SYM[0] + ~VAR[divider][1]);
// modInt end"
    }
  }
]