clash-lib-0.99: prims/verilog/Clash_Prelude_ROM.json

[ { "BlackBox" :
    { "name" : "Clash.Prelude.ROM.asyncRom#"
    , "type" :
"asyncRom# :: KnownNat n -- ^ ARG[0]
           => Vec n a    -- ^ ARG[1]
           -> Int        -- ^ ARG[2]
           -> a"
    , "templateD" :
"// asyncRom begin
wire ~TYPO ~GENSYM[ROM][0] [0:~LIT[0]-1];

wire ~TYP[1] ~GENSYM[romflat][1];
assign ~SYM[1] = ~ARG[1];
genvar ~GENSYM[i][2];
~GENERATE
for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : ~GENSYM[mk_array][3]
  assign ~SYM[0][(~LIT[0]-1)-~SYM[2]] = ~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
end
~ENDGENERATE

assign ~RESULT = ~SYM[0][~ARG[2]];
// asyncRom end"
    }
  }
]