clash-lib-0.99: prims/verilog/Clash_Intel_ClockGen.json

[ { "BlackBox" :
    { "name"      : "Clash.Intel.ClockGen.altpll"
    , "type"      :
"altpll
  :: SSymbol name               -- ARG[0]
  -> Clock  pllIn 'Source       -- ARG[1]
  -> Reset  pllIn 'Asynchronous -- ARG[2]
  -> (Clock pllOut 'Source, Signal pllOut Bool)"
    , "templateD" :
"// altpll begin
~NAME[0] ~GENSYM[altpll_inst][2]
(.inclk0 (~ARG[1])
,.areset (~ARG[2])
,.c0     (~RESULT[1])
,.locked (~RESULT[0]));
// altpll end"
    }
  }
, { "BlackBox" :
    { "name"      : "Clash.Intel.ClockGen.alteraPll"
    , "type"      :
"alteraPll
  :: SSymbol name               -- ARG[0]
  -> Clock  pllIn 'Source       -- ARG[1]
  -> Reset  pllIn 'Asynchronous -- ARG[2]
  -> (Clock pllOut 'Source, Signal pllOut Bool)"
    , "templateD" :
"// alteraPll begin
~NAME[0] ~GENSYM[alteraPll_inst][2]
(.refclk   (~ARG[1])
,.rst      (~ARG[2])
,.outclk_0 (~RESULT[1])
,.locked   (~RESULT[0]));
// alteraPll end"
    }
  }
]