clash-lib-0.99: prims/verilog/Clash_Explicit_Testbench.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.Testbench.assert"
    , "type" :
"assert
  :: (Eq a,ShowX a)           -- (ARG[0],ARG[1])
  => Clock domain gated       -- ARG[2]
  -> Reset domain synchronous -- ARG[3]
  -> String                   -- ARG[4]
  -> Signal domain a          -- Checked value (ARG[5])
  -> Signal domain a          -- Expected value (ARG[6])
  -> Signal domain b          -- Return valued (ARG[7])
  -> Signal domain b"
    , "templateD" :
"// assert begin
// pragma translate_off
always @(posedge ~IF ~ISGATED[2] ~THEN ~ARG[2][1] ~ELSE ~ARG[2] ~FI~IF ~ISSYNC[3] ~THEN ~ELSE or negedge ~ARG[3]~FI) begin
  if (~ARG[5] !== ~ARG[6]) begin
    $display(\"@%0tns: %s, expected: %b, actual: %b\", $time, ~LIT[4], ~ARG[6], ~ARG[5]);
    $finish;
  end
end
// pragma translate_on
assign ~RESULT = ~ARG[7];
// assert end"
    }
  }
]