clash-lib-0.99: prims/verilog/Clash_Explicit_ROM.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.ROM.rom#"
    , "type" :
"rom# :: KnownNat n      -- ARG[0]
      => Clock dom gated -- clk,  ARG[1]
      -> Vec n a         -- init, ARG[2]
      -> Signal dom Int  -- rd,   ARG[3]
      -> Signal dom a"
    , "outputReg" : true
    , "templateD" :
"// rom begin
reg ~TYPO ~GENSYM[ROM][0] [0:~LIT[0]-1];

reg ~TYP[2] ~GENSYM[rom_init][2];
integer ~GENSYM[i][3];
initial begin
  ~SYM[2] = ~ARG[2];
  for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3] = ~SYM[3] + 1) begin
    ~SYM[0][~LIT[0]-1-~SYM[3]] = ~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
  end
end
~IF ~ISGATED[1] ~THEN
always @(posedge ~ARG[1][1]) begin : ~GENSYM[~COMPNAME_rom][4]
  if (~ARG[1][0]) begin
    ~RESULT <= ~SYM[0][~ARG[3]];
  end
end~ELSE
always @(posedge ~ARG[1]) begin : ~SYM[4]
  ~RESULT <= ~SYM[0][~ARG[3]];
end~FI
// rom end"
    }
  }
]