clash-lib-0.99: prims/verilog/Clash_Explicit_BlockRam.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.blockRam#"
    , "type" :
"blockRam#
  :: HasCallStack    -- ARG[0]
  => Clock dom gated -- clk,  ARG[1]
  -> Vec n a         -- init, ARG[2]
  -> Signal dom Int  -- rd,   ARG[3]
  -> Signal dom Bool -- wren, ARG[4]
  -> Signal dom Int  -- wr,   ARG[5]
  -> Signal dom a    -- din,  ARG[6]
  -> Signal dom a"
    , "outputReg" : true
    , "templateD" :
"// blockRam begin
reg ~TYPO ~GENSYM[RAM][0] [0:~LENGTH[~TYP[2]]-1];

reg ~TYP[2] ~GENSYM[ram_init][2];
integer ~GENSYM[i][3];
initial begin
  ~SYM[2] = ~ARG[2];
  for (~SYM[3]=0; ~SYM[3] < ~LENGTH[~TYP[2]]; ~SYM[3] = ~SYM[3] + 1) begin
    ~SYM[0][~LENGTH[~TYP[2]]-1-~SYM[3]] = ~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
  end
end
~IF ~ISGATED[1] ~THEN
always @(posedge ~ARG[1][1]) begin : ~GENSYM[~COMPNAME_blockRam][4]~IF ~VIVADO ~THEN
  if (~ARG[1][0]) begin
    if (~ARG[4]) begin
      ~SYM[0][~ARG[5]] <= ~ARG[6];
    end
    ~RESULT <= ~SYM[0][~ARG[3]];
  end~ELSE
  if (~ARG[4] & ~ARG[1][0]) begin
    ~SYM[0][~ARG[5]] <= ~ARG[6];
  end
  if (~ARG[1][0]) begin
    ~RESULT <= ~SYM[0][~ARG[3]];
  end~FI
end~ELSE
always @(posedge ~ARG[1]) begin : ~SYM[4]
  if (~ARG[4]) begin
    ~SYM[0][~ARG[5]] <= ~ARG[6];
  end
  ~RESULT <= ~SYM[0][~ARG[3]];
end~FI
// blockRam end"
    }
  }
]