clash-lib-0.99: prims/systemverilog/Clash_Xilinx_ClockGen.json

[ { "BlackBox" :
    { "name"      : "Clash.Xilinx.ClockGen.clockWizard"
    , "type"      :
"clockWizard
  :: SSymbol name               -- ARG[0]
  -> Clock  pllIn 'Source       -- ARG[1]
  -> Reset  pllIn 'Asynchronous -- ARG[2]
  -> (Clock pllOut 'Source, Signal pllOut Bool)"
    , "templateD" :
"// clockWizard begin
~NAME[0] ~GENSYM[clockWizard_inst][2]
(.CLK_IN1  (~ARG[1])
,.RESET    (~ARG[2])
,.CLK_OUT1 (~RESULT[1])
,.LOCKED   (~RESULT[0]));
// clockWizard end"
    }
  }
, { "BlackBox" :
    { "name"      : "Clash.Xilinx.ClockGen.clockWizardDifferential"
    , "type"      :
"clockWizardDifferential
  :: SSymbol name               -- ARG[0]
  -> Clock  pllIn 'Source       -- ARG[1]
  -> Clock  pllIn 'Source       -- ARG[2]
  -> Reset  pllIn 'Asynchronous -- ARG[3]
  -> (Clock pllOut 'Source, Signal pllOut Bool)"
    , "templateD" :
"// clockWizardDifferential begin
~NAME[0] ~GENSYM[clockWizardDifferential_inst][2]
(.CLK_IN1_D_clk_n (~ARG[1])
,.CLK_IN1_D_clk_n (~ARG[2])
,.RESET           (~ARG[3])
,.CLK_OUT1        (~RESULT[1])
,.LOCKED          (~RESULT[0]));
// clockWizardDifferential end"
    }
  }
]