Clash_Intel_DDR.json

[ { "BlackBox" :
    { "name" : "Clash.Intel.DDR.altddioIn"
    , "type" :
"altddioIn
  :: ( HasCallStack               -- ARG[0]
     , fast ~ Dom n pFast         -- ARG[1]
     , slow ~ Dom n (2*pFast)     -- ARG[2]
     , KnownNat m )               -- ARG[3]
  => SSymbol deviceFamily         -- ARG[4]
  -> Clock slow gated             -- ARG[5]
  -> Reset slow synchronous       -- ARG[6]
  -> Signal fast (BitVector m)    -- ARG[7]
  -> Signal slow (BitVector m,BitVector m)"
    , "templateD" :
"// altddioIn begin
~SIGD[~GENSYM[dataout_l][1]][7];
~SIGD[~GENSYM[dataout_h][2]][7];

altddio_in ~GENSYM[~COMPNAME_ALTDDIO_IN][7] (~IF ~ISSYNC[6] ~THEN
  .sclr (~ARG[6]),
  .aclr (1'b0),~ELSE
  .aclr (~ARG[6]),
  .sclr (1'b0),~FI
  .datain (~ARG[7]),~IF ~ISGATED[5] ~THEN
  .inclock (~ARG[5][1]),
  .inclocken (~ARG[5][0]),~ELSE
  .inclock (~ARG[5]),
  .inclocken (1'b1),~FI
  .dataout_h (~SYM[2]),
  .dataout_l (~SYM[1]),
  .aset (1'b0),
  .sset (1'b0));
defparam
  ~SYM[7].intended_device_family = ~LIT[4],
  ~SYM[7].invert_input_clocks = \"OFF\",
  ~SYM[7].lpm_hint = \"UNUSED\",
  ~SYM[7].lpm_type = \"altddio_in\",
  ~SYM[7].power_up_high = \"OFF\",
  ~SYM[7].width = ~SIZE[~TYP[7]];

assign ~RESULT = {~SYM[1],~SYM[2]};
// altddioIn end"
    }
  }
, { "BlackBox" :
    { "name" : "Clash.Intel.DDR.altddioOut#"
    , "type" :
"altddioOut#
  :: ( HasCallStack             -- ARG[0]
     , fast ~ Dom n pFast       -- ARG[1]
     , slow ~ Dom n (2*pFast)   -- ARG[2]
     , KnownNat m )             -- ARG[3]
  => SSymbol deviceFamily       -- ARG[4]
  -> Clock slow gated           -- ARG[5]
  -> Reset slow synchronous     -- ARG[6]
  -> Signal slow (BitVector m)  -- ARG[7]
  -> Signal slow (BitVector m)  -- ARG[8]
  -> Signal fast (BitVector m)"
    , "templateD" :
"// altddioOut begin
altddio_out ~GENSYM[~COMPNAME_ALTDDIO_OUT][7] (~IF ~ISSYNC[6] ~THEN
  .sclr (~ARG[6]),
  .aclr (1'b0),~ELSE
  .aclr (~ARG[6]),
  .sclr (1'b0),~FI
  .datain_h (~ARG[7]),
  .datain_l (~ARG[8]),~IF ~ISGATED[5] ~THEN
  .outclock (~ARG[5][1]),
  .outclocken (~ARG[5][0]),~ELSE
  .outclock (~ARG[5]),
  .outclocken (1'b1),~FI
  .dataout (~RESULT),
  .aset (1'b0),
  .sset (1'b0),
  .oe (1'b1),
  .oe_out ());
defparam
  ~SYM[7].extend_oe_disable = \"OFF\",
  ~SYM[7].intended_device_family = ~LIT[4],
  ~SYM[7].invert_output = \"OFF\",
  ~SYM[7].lpm_hint = \"UNUSED\",
  ~SYM[7].lpm_type = \"altddio_out\",
  ~SYM[7].oe_reg = \"UNREGISTERED\",
  ~SYM[7].power_up_high = \"OFF\",
  ~SYM[7].width = ~SIZE[~TYPO];
// altddioOut end"
    }
  }
]