clash-lib-0.99: prims/systemverilog/Clash_Explicit_ROM_File.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.ROM.File.romFile#"
    , "type" :
"romFile# :: KnownNat m      -- ARG[0]
          => Clock clk gated -- clk,  ARG[1]
          -> SNat n          -- sz,   ARG[2]
          -> FilePath        -- file, ARG[3]
          -> Signal dom Int  -- rd,   ARG[4]
          -> Signal dom (BitVector m)"
    , "templateD" :
"// romFile begin
~SIGDO[~GENSYM[ROM][0]] [0:~LIT[2]-1];

initial begin
  $readmemb(~FILE[~LIT[3]],~SYM[0]);
end

~SIGDO[~GENSYM[~RESULT_q][1]];~IF ~ISGATED[1] ~THEN
always @(posedge ~ARG[1][1]) begin : ~GENSYM[~COMPNAME_romFile][2]
  if (~ARG[1][0]) begin
    ~SYM[1] <= ~SYM[0][~ARG[4]];
  end
end~ELSE
always @(posedge ~ARG[1]) begin : ~SYM[2]
  ~SYM[1] <= ~SYM[0][~ARG[4]];
end~FI

assign ~RESULT = ~SYM[1];
// romFile end"
    }
  }
]