clash-lib-0.99: prims/systemverilog/Clash_Explicit_BlockRam_File.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.File.blockRamFile#"
    , "type" :
"blockRamFile#
  :: (KnownNat m, HasCallStack)-- (ARG[0],ARG[1])
  => Clock dom gated           -- clk,  ARG[2]
  -> SNat n                    -- sz,   ARG[3]
  -> FilePath                  -- file, ARG[4]
  -> Signal dom Int            -- rd,   ARG[5]
  -> Signal dom Bool           -- wren, ARG[6]
  -> Signal dom Int            -- wr,   ARG[7]
  -> Signal dom (BitVector m)  -- din,  ARG[8]
  -> Signal dom (BitVector m)"
    , "templateD" :
"// blockRamFile begin
~SIGDO[~GENSYM[RAM][0]] [0:~LIT[3]-1];
~SIGD[~GENSYM[~RESULT_q][1]][8];

initial begin
  $readmemb(~FILE[~LIT[4]],~SYM[0]);
end
~IF ~ISGATED[2] ~THEN
always @(posedge ~ARG[2][1]) begin : ~GENSYM[~COMPNAME_blockRamFile][2]~IF ~VIVADO ~THEN
  if (~ARG[2][0]) begin
    if (~ARG[6]) begin
      ~SYM[0][~ARG[7]] <= ~ARG[8];
    end
    ~SYM[1] <= ~SYM[0][~ARG[5]];
  end~ELSE
  if (~ARG[6] & ~ARG[2][0]) begin
    ~SYM[0][~ARG[7]] <= ~ARG[8];
  end
  if (~ARG[2][0] begin
    ~SYM[1] <= ~SYM[0][~ARG[5]];
  end~FI
end~ELSE
always @(posedge ~ARG[2]) begin : ~SYM[2]
  if (~ARG[6]) begin
    ~SYM[0][~ARG[7]] <= ~ARG[8];
  end
  ~SYM[1] <= ~SYM[0][~ARG[5]];
end~FI

assign ~RESULT = ~SYM[1];
// blockRamFile end"
    }
  }
]