clash-lib-0.99: prims/systemverilog/Clash_Explicit_BlockRam.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.blockRam#"
    , "type" :
"blockRam#
  :: HasCallStack    -- ARG[0]
  => Clock dom gated -- clk,  ARG[1]
  -> Vec n a         -- init, ARG[2]
  -> Signal dom Int  -- rd,   ARG[3]
  -> Signal dom Bool -- wren, ARG[4]
  -> Signal dom Int  -- wr,   ARG[5]
  -> Signal dom a    -- din,  ARG[6]
  -> Signal dom a"
    , "templateD" :
"// blockRam begin
~SIGD[~GENSYM[RAM][0]][2];
logic [~SIZE[~TYP[6]]-1:0] ~GENSYM[~RESULT_q][1];
initial begin
  ~SYM[0] = ~LIT[2];
end~IF ~ISGATED[1] ~THEN
always @(posedge ~ARG[1][1]) begin : ~GENSYM[~COMPNAME_blockRam][2]~IF ~VIVADO ~THEN
  if (~ARG[1][0]) begin
    if (~ARG[4]) begin
      ~SYM[0][~ARG[5]] <= ~TOBV[~ARG[6]][~TYP[6]];
    end
    ~SYM[1] <= ~SYM[0][~ARG[3]];
  end~ELSE
  if (~ARG[4] & ~ARG[1][0]) begin
    ~SYM[0][~ARG[5]] <= ~TOBV[~ARG[6]][~TYP[6]];
  end
  if (~ARG[1][0]) begin
    ~SYM[1] <= ~SYM[0][~ARG[3]];
  end~FI
end~ELSE
always @(posedge ~ARG[1]) begin : ~SYM[2]
  if (~ARG[4]) begin
    ~SYM[0][~ARG[5]] <= ~TOBV[~ARG[6]][~TYP[6]];
  end
  ~SYM[1] <= ~SYM[0][~ARG[3]];
end~FI
assign ~RESULT = ~FROMBV[~SYM[1]][~TYP[6]];
// blockRam end"
    }
  }
]