clash-ghc-0.3.1: primitives/clash.sized.vector.json

[ { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vhead"
    , "templateD" :
"~SYM[0]_vhead : block
  signal ~SYM[1] : ~TYP[0];
begin
  ~SYM[1] <= ~ARG[0];
  ~RESULT <= ~SYM[1](~SYM[1]'high);
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vtail"
    , "templateD" :
"~SYM[0]_vtail : block
  signal ~SYM[1] : ~TYP[0];
begin
  ~SYM[1] <= ~ARG[0];
  ~RESULT <= ~SYM[1]((~SYM[1]'high)-1 downto 0);
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vlast"
    , "templateD" :
"~SYM[0]_vlast : block
  signal ~SYM[1] : ~TYP[0];
begin
  ~SYM[1] <= ~ARG[0];
  ~RESULT <= ~SYM[1](0);
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vinit"
    , "templateD" :
"~SYM[0]_vinit : block
  signal ~SYM[1] : ~TYP[0];
begin
  ~SYM[1] <= ~ARG[0];
  ~RESULT <= ~SYM[1](~SYM[1]'high downto 1);
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.shiftIntoL"
    , "templateD" :
"~SYM[0]_shiftIntoL : block
  signal ~SYM[1] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];
  ~RESULT <= ~TYPM[0]'(~ARG[0]) & ~SYM[1](~SYM[1]'high downto 1);
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.snoc"
    , "templateE" : "~TYPM[1]'(~ARG[1]) & ~TYPM[0]'(~ARG[0])"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.shiftIntoR"
    , "templateD" :
"~SYM[0]_shiftIntoR : block
  signal ~SYM[1] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];
  ~RESULT <= ~SYM[1]((~SYM[1]'high)-1 downto 0) & ~TYPM[0]'(~ARG[0]);
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vappend"
    , "templateE" : "~TYPM[0]'(~ARG[0]) & ~TYPM[1]'(~ARG[1])"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vsplit"
    , "templateD" :
"~SYM[0]_vsplit : block
  signal ~SYM[1] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];
  ~RESULT <= (~SYM[1](~SYM[1]'high downto (~SYM[1]'high - ~LIT[0] + 1)),~SYM[1]((~SYM[1]'high - ~LIT[0]) downto 0));
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vconcat"
    , "templateD" :
"~SYM[0]_vconcat : block
  signal ~SYM[1] : ~TYP[0];
begin
  ~SYM[1] <= ~ARG[0];
  ~SYM[2]_vconcat : for ~SYM[3] in ~ARG[0]'high downto 0 generate
  begin
    ~RESULT(((~SYM[3] * ~SYM[1](0)'length) + ~SYM[1](0)'high) downto (~SYM[3] * ~SYM[1](0)'length)) <= ~SYM[1](~SYM[3]);
  end generate;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vunconcat"
    , "templateD" :
"~SYM[0]_vunconcat : block
  signal ~SYM[1] : ~TYP[2];
begin
  ~SYM[1] <= ~ARG[2];
  ~SYM[2]_vunconcat : for ~SYM[3] in ~RESULT'high downto 0 generate
  begin
    ~RESULT(~SYM[3]) <= ~SYM[1](((~SYM[3] * ~RESULT(0)'length) + ~RESULT(0)'high) downto (~SYM[3] * ~RESULT(0)'length));
  end generate;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vmerge"
    , "templateD" :
"~SYM[0]_vmerge : block
  signal ~SYM[1] : ~TYP[0];
  signal ~SYM[2] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[0];
  ~SYM[2] <= ~ARG[1];

  ~SYM[3]_vmerge : for ~SYM[4] in ~SYM[1]'high downto 0 generate
  begin
    ~RESULT(2*~SYM[4]+1) <= ~SYM[1](~SYM[4]);
    ~RESULT(2*~SYM[4])   <= ~SYM[2](~SYM[4]);
  end generate;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vreverse"
    , "templateD" :
"~SYM[0]_vreverse : block
  signal ~SYM[1] : ~TYP[0];
begin
  ~SYM[1] <= ~ARG[0];

  process(~SYM[1])
  begin
    for ~SYM[2] in ~SYM[1]'range loop
      ~RESULT(~SYM[1]'high - ~SYM[2]) <= ~SYM[1](~SYM[2]);
    end loop;
  end process;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vmap"
    , "templateD" :
"~SYM[0]_vmap : block
  signal ~SYM[1] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];

  ~SYM[2]_vmap : for ~SYM[3] in ~RESULT'high downto 0 generate
  begin
    ~INST 0
      ~OUTPUT <= ~RESULT(~SYM[3])~ ~TYPEL[~TYPO]~
      ~INPUT  <= ~SYM[1](~SYM[3])~ ~TYPEL[~TYP[1]]~
    ~INST
  end generate;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vzipWith"
    , "templateD" :
"~SYM[0]_vzipWith : block
  signal ~SYM[1] : ~TYP[1];
  signal ~SYM[2] : ~TYP[2];
begin
  ~SYM[1] <= ~ARG[1];
  ~SYM[2] <= ~ARG[2];

  ~SYM[3]_generate : for ~SYM[4] in ~RESULT'high downto 0 generate
  begin
    ~INST 0
      ~OUTPUT <= ~RESULT(~SYM[4])~ ~TYPEL[~TYPO]~
      ~INPUT  <= ~SYM[1](~SYM[4])~ ~TYPEL[~TYP[1]]~
      ~INPUT  <= ~SYM[2](~SYM[4])~ ~TYPEL[~TYP[2]]~
    ~INST
  end generate;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vfoldr"
    , "templateD" :
"~SYM[0]_vfoldr : block
  type ~SYM[7] is array (integer range <>) of ~TYP[1];
  signal ~SYM[6] : ~TYP[2];
  signal ~SYM[1] : ~SYM[7](~SYM[6]'high downto 0);
begin
  ~SYM[1](0) <= ~ARG[1];
  ~SYM[6] <= ~ARG[2];

  ~SYM[2]_generate : for ~SYM[3] in 0 to ~SYM[6]'high generate
  begin
    ~SYM[4]_generate : if ~SYM[3] /= (~SYM[6]'high) generate
      ~INST 0
        ~OUTPUT <= ~SYM[1](~SYM[3]+1)~ ~TYP[1]~
        ~INPUT  <= ~SYM[6](~SYM[3])~ ~TYPEL[~TYP[2]]~
        ~INPUT  <= ~SYM[1](~SYM[3])~ ~TYP[1]~
      ~INST
    end generate;

    ~SYM[5]_generate : if ~SYM[3] = (~SYM[6]'high) generate
      ~INST 0
        ~OUTPUT <= ~RESULT~ ~TYPO~
        ~INPUT  <= ~SYM[6](~SYM[3])~ ~TYPEL[~TYP[2]]~
        ~INPUT  <= ~SYM[1](~SYM[3])~ ~TYP[1]~
      ~INST
    end generate;
  end generate;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vfoldl"
    , "templateD" :
"~SYM[0]_vfoldl : block
  type ~SYM[7] is array (integer range <>) of ~TYP[1];
  signal ~SYM[6] : ~TYP[2];
  signal ~SYM[1] : ~SYM[7](~SYM[6]'high downto 0);
begin
  ~SYM[1](~SYM[1]'high) <= ~ARG[1];
  ~SYM[6] <= ~ARG[2];

  ~SYM[2]_generate : for ~SYM[3] in ~SYM[6]'high downto 0 generate
  begin
    ~SYM[4]_generate : if ~SYM[3] /= 0 generate
      ~INST 0
        ~OUTPUT <= ~SYM[1](~SYM[3]-1)~ ~TYP[1]~
        ~INPUT  <= ~SYM[1](~SYM[3])~ ~TYP[1]~
        ~INPUT  <= ~SYM[6](~SYM[3])~ ~TYPEL[~TYP[2]]~
      ~INST
    end generate;

    ~SYM[5]_generate : if ~SYM[3] = 0 generate
      ~INST 0
        ~OUTPUT <= ~RESULT~ ~TYPO~
        ~INPUT  <= ~SYM[1](~SYM[3])~ ~TYP[1]~
        ~INPUT  <= ~SYM[6](~SYM[3])~ ~TYPEL[~TYP[2]]~
      ~INST
    end generate;
  end generate;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vfoldr1"
    , "templateD" :
"~SYM[0]_vfoldr1 : block
  signal ~SYM[1] : ~TYP[1];
  signal ~SYM[2] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];
  ~SYM[2](0) <= SYM[1](0);

  ~SYM[3]_generate : for ~SYM[4] in 1 to ~SYM[2]'high generate
  begin
    ~INST 0
      ~OUTPUT <= ~SYM[2](~SYM[4])~ ~TYPEL[~TYP[1]]~
      ~INPUT  <= ~SYM[1](~SYM[4])~ ~TYPEL[~TYP[1]]~
      ~INPUT  <= ~SYM[2](~SYM[4]-1)~ ~TYPEL[~TYP[1]]~
    ~INST
  end generate;

  ~RESULT <= ~SYM[2](~SYM[2]'high);
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vindex_integer"
    , "templateD" :
"~SYM[0]_vindex_integer : block
  signal ~SYM[1] : ~TYP[1];
  signal ~SYM[2] : ~TYP[2];
begin
  ~SYM[1] <= ~ARG[1];
  ~SYM[2] <= ~ARG[2];
  -- pragma translate_off
  process (~SYM[1],~SYM[2])
  begin
    if ~SYM[2] < ~SYM[1]'low or ~SYM[2] > ~SYM[1]'high then
      assert false report (\"Index: \" & integer'image(~SYM[2]) & \", is out of bounds: \" & integer'image(~SYM[1]'low) & \" downto \" & integer'image(~SYM[1]'high)) severity warning;
      ~RESULT <= ~ERRORO;
    else
    -- pragma translate_on
      ~RESULT <= ~SYM[1](~SYM[2]);
    -- pragma translate_off
    end if;
  end process;
  -- pragma translate_on
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.maxIndex"
    , "templateD" :
"~SYM[0]_maxIndex : block
  signal ~SYM[1] : ~TYP[1];
begin
  ~RESULT <= ~SYM[1]'high;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vreplace_integer"
    , "templateD" :
"~SYM[0]_vreplace_integer : block
  signal ~SYM[1] : ~TYP[1];
  signal ~SYM[2] : ~TYP[2];
  signal ~SYM[3] : ~TYP[3];
begin
  ~SYM[1] <= ~ARG[1];
  ~SYM[2] <= ~ARG[2];
  ~SYM[3] <= ~ARG[3];
  process(~SYM[1],~SYM[2],~SYM[3])
    variable ~SYM[4] : ~TYP[1];
  begin
    ~SYM[4] := ~SYM[1];
    -- pragma translate_off
    if ~SYM[2] < ~SYM[4]'low or ~SYM[2] > ~SYM[4]'high then
      assert false report (\"Index: \" & integer'image(~SYM[2]) & \", is out of bounds: \" & integer'image(~SYM[1]'low) & \" downto \" & integer'image(~SYM[1]'high)) severity warning;
      ~SYM[4] := ~ERROR[1];
    else
      -- pragma translate_on
      ~SYM[4](~SYM[2]) := ~SYM[3];
      -- pragma translate_off
    end if;
    -- pragma translate_on
    ~RESULT <= ~SYM[4];
  end process;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vtake"
    , "templateD" :
"~SYM[0]_vtake : block
  signal ~SYM[1] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];
  ~RESULT <= ~SYM[1](~SYM[1]'high downto (~SYM[1]'length - ~LIT[0]));
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vdrop"
    , "templateD" :
"~SYM[0]_vdrop : block
  signal ~SYM[1] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];
  ~RESULT <= ~SYM[1]((~SYM[1]'high - ~LIT[0]) downto 0);
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vexact"
    , "templateD" :
"~SYM[0]_vexact : block
  signal ~SYM[1] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];
  ~RESULT <= ~SYM[1](~LIT[0]);
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vselect"
    , "comment"   :
    "vselect :: ((f + (s * n) + 1) <= i) -- ARG[0]
        => SNat f                        -- ARG[1]
        -> SNat s                        -- ARG[2]
        -> SNat (n + 1)                  -- ARG[3]
        -> Vec i a                       -- ARG[4]
        -> Vec (n + 1) a"
    , "templateD" :
"~SYM[0]_vselect : block
  signal ~SYM[1] : ~TYP[4];
begin
  ~SYM[1] <= ~ARG[4];
  ~SYM[2]_vselect : for ~SYM[3] in 0 to ~RESULT'high generate
  begin
    ~RESULT(~RESULT'high - ~SYM[3]) <= ~SYM[1](~SYM[1]'high - (~LIT[1]+(~LIT[2]*~SYM[3])));
  end generate;
end block;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vcopy"
    , "templateE" : "~TYPMO'((~LIT[0] - 1) downto 0 => ~ARG[1])"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.viterate"
    , "templateD" :
"~SYM[0]_viterate : for ~SYM[1] in ~RESULT'high downto 0 generate
begin
  ~SYM[2]_generate : if ~SYM[1] = (~RESULT'high) generate
  begin
    ~RESULT(~SYM[1]) <= ~ARG[2];
  end generate;

  ~SYM[3]_generate : if ~SYM[1] /= (~RESULT'high) generate
  begin
    ~INST 0
      ~OUTPUT <= ~RESULT(~SYM[1])~ ~TYPEL[~TYPO]~
      ~INPUT  <= ~RESULT(~SYM[1]+1)~ ~TYPEL[~TYPO]~
    ~INST
  end generate;
end generate;"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.lazyV"
    , "templateE" : "~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.vhead'"
    , "templateD" :
"~SYM[0]_vhead : block
  signal ~SYM[1] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];
  ~RESULT <= ~SYM[1](~SYM[1]'high);
end block;"
    }
  }
]