x86-64bit 0.4.3 → 0.4.4

raw patch · 4 files changed

+20/−7 lines, 4 filesPVP ok

version bump matches the API change (PVP)

API changes (from Hackage documentation)

Files

• CHANGELOG.md +4/−0
• CodeGen/X86.hs +3/−1
• CodeGen/X86/Asm.hs +12/−5
• x86-64bit.cabal +1/−1

@@ -1,3 +1,7 @@+# Version 0.4.4
+
+-   export some useful data types 
+
 # Version 0.4.3
 
 -   fixes to compile on GHC 7.10 and on Windows

@@ -9,6 +9,7 @@     , HasSize (..)     , IsSize     -- * Registers+    , Reg , FromReg (..)     -- ** 64 bit registers     , rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15     -- ** 32 bit registers@@ -22,6 +23,7 @@     -- ** SSE registers     , xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7     -- * Addresses+    , Addr (..), BaseReg, IndexReg, Scale, Displacement, Address     , addr     , addr8     , addr16@@ -31,7 +33,7 @@     , ipRel8     -- * Operands     , Access (..)-    , Operand+    , Operand (..)     , resizeOperand     , ipRelValue     -- * Conditions

@@ -62,6 +62,7 @@  ------------------------------------------------------- sizes +-- | The size of a register (in bits) data Size = S8 | S16 | S32 | S64 | S128     deriving (Eq, Ord) @@ -135,7 +136,7 @@  ------------------------------------------------------- scale --- replace with Size?+-- | The scaling of an index. (replace with Size?) newtype Scale = Scale Word8     deriving (Eq) @@ -158,6 +159,7 @@  ------------------------------------------------------- operand +-- | An operand can be an immediate, a register, a memory address or RIP-relative (memory address relative to the instruction pointer) data Operand :: Access -> Size -> * where     ImmOp     :: Immediate Int64 -> Operand R s     RegOp     :: Reg s -> Operand rw s@@ -198,19 +200,24 @@     = R     -- ^ readable operand     | RW    -- ^ readable and writeable operand +-- | A register. data Reg :: Size -> * where-    NormalReg :: Word8 -> Reg s-    HighReg   :: Word8 -> Reg S8-    XMM       :: Word8 -> Reg S128+    NormalReg :: Word8 -> Reg s      -- \"normal\" registers are for example @AL@, @BX@, @ECX@ or @RSI@+    HighReg   :: Word8 -> Reg S8     -- \"high\" registers are @AH@, @BH@, @CH@ etc+    XMM       :: Word8 -> Reg S128   -- XMM registers  deriving instance Eq (Reg s) deriving instance Ord (Reg s) +-- | A (relative) address is made up base a base register, a displacement, and a (scaled) index.+-- For example in @[eax+4*ecx+20]@ the base register is @eax@, the displacement is @20@ and the+-- index is @4*ecx@. data Addr s = Addr     { baseReg        :: BaseReg s     , displacement   :: Displacement     , indexReg       :: IndexReg s     }+    deriving (Eq)  type BaseReg s    = Maybe (Reg s) type IndexReg s   = Maybe (Scale, Reg s)@@ -222,7 +229,7 @@ pattern NoIndex = Nothing pattern IndexReg a b = Just (a, b) --- | intruction pointer relative address+-- | intruction pointer (RIP) relative address ipRel :: Label -> Operand rw s ipRel l = IPMemOp $ LabelRelValue S32 l 

@@ -1,5 +1,5 @@ name:                x86-64bit
-version:             0.4.3
+version:             0.4.4
 homepage:            https://github.com/divipp/x86-64
 synopsis:            Runtime code generation for x86 64 bit machine code
 description:         The primary goal of x86-64bit is to provide a lightweight assembler for machine generated 64 bit x86 assembly instructions. See README.md for further details.