verismith 0.6.0.0 → 0.6.0.1
raw patch · 5 files changed
+80/−35 lines, 5 filesPVP: major bump suggested
API removals or changes: PVP suggests a major version bump
API changes (from Hackage documentation)
+ Verismith.Config: [_propDefaultYosys] :: ConfProperty -> !Maybe Text
+ Verismith.Config: propDefaultYosys :: Lens' ConfProperty (Maybe Text)
+ Verismith.Result: instance Shelly.Lifted.MonadShControl m => Shelly.Lifted.MonadShControl (Verismith.Result.ResultT a m)
- Verismith.Config: ConfProperty :: {-# UNPACK #-} !Int -> !Maybe Seed -> {-# UNPACK #-} !Int -> {-# UNPACK #-} !Int -> {-# UNPACK #-} !Int -> !Text -> {-# UNPACK #-} !Int -> !Bool -> {-# UNPACK #-} !Int -> {-# UNPACK #-} !Int -> ConfProperty
+ Verismith.Config: ConfProperty :: {-# UNPACK #-} !Int -> !Maybe Seed -> {-# UNPACK #-} !Int -> {-# UNPACK #-} !Int -> {-# UNPACK #-} !Int -> !Text -> {-# UNPACK #-} !Int -> !Bool -> {-# UNPACK #-} !Int -> {-# UNPACK #-} !Int -> !Maybe Text -> ConfProperty
- Verismith.Verilog.AST: ConstBinOpF :: !r_aPQP -> !BinaryOperator -> !r_aPQP -> ConstExprF r_aPQP
+ Verismith.Verilog.AST: ConstBinOpF :: !r_aQ5h -> !BinaryOperator -> !r_aQ5h -> ConstExprF r_aQ5h
- Verismith.Verilog.AST: ConstConcatF :: !NonEmpty r_aPQP -> ConstExprF r_aPQP
+ Verismith.Verilog.AST: ConstConcatF :: !NonEmpty r_aQ5h -> ConstExprF r_aQ5h
- Verismith.Verilog.AST: ConstCondF :: !r_aPQP -> !r_aPQP -> !r_aPQP -> ConstExprF r_aPQP
+ Verismith.Verilog.AST: ConstCondF :: !r_aQ5h -> !r_aQ5h -> !r_aQ5h -> ConstExprF r_aQ5h
- Verismith.Verilog.AST: ConstNumF :: {-# UNPACK #-} !BitVecF Integer -> ConstExprF r_aPQP
+ Verismith.Verilog.AST: ConstNumF :: {-# UNPACK #-} !BitVecF Integer -> ConstExprF r_aQ5h
- Verismith.Verilog.AST: ConstStrF :: {-# UNPACK #-} !Text -> ConstExprF r_aPQP
+ Verismith.Verilog.AST: ConstStrF :: {-# UNPACK #-} !Text -> ConstExprF r_aQ5h
- Verismith.Verilog.AST: ConstUnOpF :: !UnaryOperator -> !r_aPQP -> ConstExprF r_aPQP
+ Verismith.Verilog.AST: ConstUnOpF :: !UnaryOperator -> !r_aQ5h -> ConstExprF r_aQ5h
- Verismith.Verilog.AST: ParamIdF :: {-# UNPACK #-} !Identifier -> ConstExprF r_aPQP
+ Verismith.Verilog.AST: ParamIdF :: {-# UNPACK #-} !Identifier -> ConstExprF r_aQ5h
- Verismith.Verilog.AST: [_constBinOpF] :: ConstExprF r_aPQP -> !BinaryOperator
+ Verismith.Verilog.AST: [_constBinOpF] :: ConstExprF r_aQ5h -> !BinaryOperator
- Verismith.Verilog.AST: [_constConcatF] :: ConstExprF r_aPQP -> !NonEmpty r_aPQP
+ Verismith.Verilog.AST: [_constConcatF] :: ConstExprF r_aQ5h -> !NonEmpty r_aQ5h
- Verismith.Verilog.AST: [_constCondF] :: ConstExprF r_aPQP -> !r_aPQP
+ Verismith.Verilog.AST: [_constCondF] :: ConstExprF r_aQ5h -> !r_aQ5h
- Verismith.Verilog.AST: [_constFalseF] :: ConstExprF r_aPQP -> !r_aPQP
+ Verismith.Verilog.AST: [_constFalseF] :: ConstExprF r_aQ5h -> !r_aQ5h
- Verismith.Verilog.AST: [_constLhsF] :: ConstExprF r_aPQP -> !r_aPQP
+ Verismith.Verilog.AST: [_constLhsF] :: ConstExprF r_aQ5h -> !r_aQ5h
- Verismith.Verilog.AST: [_constNumF] :: ConstExprF r_aPQP -> {-# UNPACK #-} !BitVecF Integer
+ Verismith.Verilog.AST: [_constNumF] :: ConstExprF r_aQ5h -> {-# UNPACK #-} !BitVecF Integer
- Verismith.Verilog.AST: [_constParamIdF] :: ConstExprF r_aPQP -> {-# UNPACK #-} !Identifier
+ Verismith.Verilog.AST: [_constParamIdF] :: ConstExprF r_aQ5h -> {-# UNPACK #-} !Identifier
- Verismith.Verilog.AST: [_constPrimF] :: ConstExprF r_aPQP -> !r_aPQP
+ Verismith.Verilog.AST: [_constPrimF] :: ConstExprF r_aQ5h -> !r_aQ5h
- Verismith.Verilog.AST: [_constRhsF] :: ConstExprF r_aPQP -> !r_aPQP
+ Verismith.Verilog.AST: [_constRhsF] :: ConstExprF r_aQ5h -> !r_aQ5h
- Verismith.Verilog.AST: [_constStrF] :: ConstExprF r_aPQP -> {-# UNPACK #-} !Text
+ Verismith.Verilog.AST: [_constStrF] :: ConstExprF r_aQ5h -> {-# UNPACK #-} !Text
- Verismith.Verilog.AST: [_constTrueF] :: ConstExprF r_aPQP -> !r_aPQP
+ Verismith.Verilog.AST: [_constTrueF] :: ConstExprF r_aQ5h -> !r_aQ5h
- Verismith.Verilog.AST: [_constUnOpF] :: ConstExprF r_aPQP -> !UnaryOperator
+ Verismith.Verilog.AST: [_constUnOpF] :: ConstExprF r_aQ5h -> !UnaryOperator
- Verismith.Verilog.AST: data ConstExprF r_aPQP
+ Verismith.Verilog.AST: data ConstExprF r_aQ5h
Files
- src/Verismith/Config.hs +56/−27
- src/Verismith/Fuzz.hs +8/−5
- src/Verismith/Reduce.hs +1/−0
- src/Verismith/Result.hs +13/−1
- verismith.cabal +2/−2
src/Verismith/Config.hs view
@@ -72,6 +72,7 @@ , propCombine , propDeterminism , propNonDeterminism+ , propDefaultYosys , parseConfigFile , parseConfig , encodeConfig@@ -140,107 +141,133 @@ -- | Probability of different expressions nodes. data ProbExpr = ProbExpr { _probExprNum :: {-# UNPACK #-} !Int- -- ^ Probability of generation a number like+ -- ^ @expr.number@: probability of generation a number like -- @4'ha@. This should never be set to 0, as it is used -- as a fallback in case there are no viable -- identifiers, such as none being in scope. , _probExprId :: {-# UNPACK #-} !Int- -- ^ Probability of generating an identifier that is in+ -- ^ @expr.variable@: probability of generating an identifier that is in -- scope and of the right type. , _probExprRangeSelect :: {-# UNPACK #-} !Int- -- ^ Probability of generating a range selection from a port.+ -- ^ @expr.rangeselect@: probability of generating a range+ -- selection from a port (@reg1[2:0]@). , _probExprUnOp :: {-# UNPACK #-} !Int- -- ^ Probability of generating a unary operator.+ -- ^ @expr.unary@: probability of generating a unary operator. , _probExprBinOp :: {-# UNPACK #-} !Int- -- ^ Probability of generation a binary operator.+ -- ^ @expr.binary@: probability of generation a binary operator. , _probExprCond :: {-# UNPACK #-} !Int- -- ^ probability of generating a conditional ternary+ -- ^ @expr.ternary@: probability of generating a conditional ternary -- operator. , _probExprConcat :: {-# UNPACK #-} !Int- -- ^ Probability of generating a concatenation.+ -- ^ @expr.concatenation@: probability of generating a concatenation. , _probExprStr :: {-# UNPACK #-} !Int- -- ^ Probability of generating a string. This is not+ -- ^ @expr.string@: probability of generating a string. This is not -- fully supported therefore currently cannot be set. , _probExprSigned :: {-# UNPACK #-} !Int- -- ^ Probability of generating a signed function+ -- ^ @expr.signed@: probability of generating a signed function -- @$signed(...)@. , _probExprUnsigned :: {-# UNPACK #-} !Int- -- ^ Probability of generating an unsigned function+ -- ^ @expr.unsigned@: probability of generating an unsigned function -- @$unsigned(...)@. } deriving (Eq, Show) -- | Probability of generating different nodes inside a module declaration. data ProbModItem = ProbModItem { _probModItemAssign :: {-# UNPACK #-} !Int- -- ^ Probability of generating an @assign@.+ -- ^ @moditem.assign@: probability of generating an @assign@. , _probModItemSeqAlways :: {-# UNPACK #-} !Int- -- ^ Probability of generating a sequential @always@ block.+ -- ^ @moditem.sequential@: probability of generating a sequential @always@ block. , _probModItemCombAlways :: {-# UNPACK #-} !Int- -- ^ Probability of generating an combinational @always@ block.+ -- ^ @moditem.combinational@: probability of generating an combinational @always@+ -- block. This is currently not implemented. , _probModItemInst :: {-# UNPACK #-} !Int- -- ^ Probability of generating a module+ -- ^ @moditem.instantiation@: probability of generating a module -- instantiation. } deriving (Eq, Show) +-- | Probability of generating different statements. data ProbStatement = ProbStatement { _probStmntBlock :: {-# UNPACK #-} !Int+ -- ^ @statement.blocking@: probability of generating blocking assignments. , _probStmntNonBlock :: {-# UNPACK #-} !Int+ -- ^ @statement.nonblocking@: probability of generating nonblocking assignments. , _probStmntCond :: {-# UNPACK #-} !Int+ -- ^ @statement.conditional@: probability of generating conditional+ -- statements (@if@ statements). , _probStmntFor :: {-# UNPACK #-} !Int+ -- ^ @statement.forloop@: probability of generating for loops. } deriving (Eq, Show) +-- | @[probability]@: combined probabilities. data Probability = Probability { _probModItem :: {-# UNPACK #-} !ProbModItem+ -- ^ Probabilities for module items. , _probStmnt :: {-# UNPACK #-} !ProbStatement+ -- ^ Probabilities for statements. , _probExpr :: {-# UNPACK #-} !ProbExpr+ -- ^ Probaiblities for expressions. } deriving (Eq, Show) +-- | @[property]@: properties for the generated Verilog file. data ConfProperty = ConfProperty { _propSize :: {-# UNPACK #-} !Int- -- ^ The size of the generated Verilog.+ -- ^ @size@: the size of the generated Verilog. , _propSeed :: !(Maybe Seed)- -- ^ A possible seed that could be used to+ -- ^ @seed@: a possible seed that could be used to -- generate the same Verilog. , _propStmntDepth :: {-# UNPACK #-} !Int- -- ^ The maximum statement depth that should be+ -- ^ @statement.depth@: the maximum statement depth that should be -- reached. , _propModDepth :: {-# UNPACK #-} !Int- -- ^ The maximium module depth that should be+ -- ^ @module.depth@: the maximium module depth that should be -- reached. , _propMaxModules :: {-# UNPACK #-} !Int- -- ^ The maximum number of modules that are+ -- ^ @module.max@: the maximum number of modules that are -- allowed to be created at each level. , _propSampleMethod :: !Text- -- ^ The sampling method that should be used to+ -- ^ @sample.method@: the sampling method that should be used to -- generate specific distributions of random -- programs. , _propSampleSize :: {-# UNPACK #-} !Int- -- ^ The number of samples to take for the+ -- ^ @sample.size@: the number of samples to take for the -- sampling method. , _propCombine :: !Bool- -- ^ If the output should be combined into one+ -- ^ @output.combine@: if the output should be combined into one -- bit or not. , _propNonDeterminism :: {-# UNPACK #-} !Int- -- ^ The frequency at which nondeterminism- -- should be generated.+ -- ^ @nondeterminism@: the frequency at which nondeterminism+ -- should be generated (currently a work in progress). , _propDeterminism :: {-# UNPACK #-} !Int- -- ^ The frequency at which determinism should- -- be generated.+ -- ^ @determinism@: the frequency at which determinism should+ -- be generated (currently modules are always deterministic).+ , _propDefaultYosys :: !(Maybe Text)+ -- ^ @default.yosys@: Default location for Yosys, which will be used for+ -- equivalence checking. } deriving (Eq, Show) data Info = Info { _infoCommit :: !Text+ -- ^ @commit@: the hash of the commit that was compiled. , _infoVersion :: !Text+ -- ^ @version@: the version of Verismith that was compiled. } deriving (Eq, Show) +-- | Description of the simulator data SimDescription = SimDescription { simName :: {-# UNPACK #-} !Text } deriving (Eq, Show) +-- | @[[synthesiser]]@: description of the synthesis tool. There can be multiple of these sections in a config+-- file. data SynthDescription = SynthDescription { synthName :: {-# UNPACK #-} !Text+ -- ^ @name@: type of the synthesis tool. Can either be @yosys@, @quartus@,+ -- @quartuslight@, @vivado@, @xst@. , synthBin :: Maybe Text+ -- ^ @bin@: location of the synthesis tool binary. , synthDesc :: Maybe Text+ -- ^ @description@: description that should be used for the synthesis tool. , synthOut :: Maybe Text+ -- ^ @output@: name of the output Verilog file. } deriving (Eq, Show) @@ -299,7 +326,7 @@ defaultConfig = Config (Info (pack $(gitHash)) (pack $ showVersion version)) (Probability defModItem defStmnt defExpr)- (ConfProperty 20 Nothing 3 2 5 "random" 10 False 0 1)+ (ConfProperty 20 Nothing 3 2 5 "random" 10 False 0 1 Nothing) [] [fromYosys defaultYosys, fromVivado defaultVivado] where@@ -424,6 +451,8 @@ .= _propNonDeterminism <*> defaultValue (defProp propDeterminism) (Toml.int "determinism") .= _propDeterminism+ <*> Toml.dioptional (Toml.text (twoKey "default" "yosys"))+ .= _propDefaultYosys where defProp i = defaultConfig ^. configProperty . i simulator :: TomlCodec SimDescription
src/Verismith/Fuzz.hs view
@@ -50,8 +50,8 @@ import qualified Hedgehog.Internal.Seed as Hog import qualified Hedgehog.Internal.Tree as Hog import Prelude hiding (FilePath)-import Shelly hiding (get)-import Shelly.Lifted (MonadSh, liftSh)+import Shelly hiding (get, sub)+import Shelly.Lifted (MonadSh, liftSh, sub) import System.FilePath.Posix (takeBaseName) import Verismith.Config import Verismith.CounterEg (CounterEg (..))@@ -273,16 +273,17 @@ datadir <- fmap _fuzzDataDir askOpts checker <- fmap _fuzzOptsChecker askOpts synth <- passedSynthesis+ conf <- fmap _fuzzOptsConfig askOpts let synthComb = if doCrossCheck then nubBy tupEq . filter (uncurry (/=)) $ combinations synth synth else nubBy tupEq . filter (uncurry (/=)) $ (,) defaultIdentitySynth <$> synth- resTimes <- liftSh $ mapM (uncurry (equiv checker datadir)) synthComb+ resTimes <- liftSh $ mapM (uncurry (equiv (conf ^. configProperty . propDefaultYosys) checker datadir)) synthComb fuzzSynthResults .= toSynthResult synthComb resTimes liftSh $ inspect resTimes where tupEq (a, b) (a', b') = (a == a' && b == b') || (a == b' && b == a')- equiv checker datadir a b =+ equiv yosysloc checker datadir a b = toolRun ("equivalence check for " <> toText a <> " and " <> toText b) . runResultT $ do make dir@@ -297,7 +298,9 @@ </> synthOutput b ) $ synthOutput b writefile "rtl.v" $ genSource src- runEquiv checker datadir a b src+ sub $ do+ maybe (return ()) (liftSh . prependToPath . fromText) yosysloc+ runEquiv checker datadir a b src where dir = fromText $ "equiv_" <> toText a <> "_" <> toText b simulation :: (MonadIO m, MonadSh m) => SourceInfo -> Fuzz m ()
src/Verismith/Reduce.hs view
@@ -575,6 +575,7 @@ >>= redAll "Statements" (const defaultBot) halveStatements -- >>= redAll "Expressions" (const defaultBot) halveExpr >>= red "Remove constants in concat" defaultBot removeConstInConcat+ >>= red "Cleaning" defaultBot (pure . cleanSourceInfoAll) where red s bot a = reduce_ fp s a bot eval red' s bot a t = reduce_ fp s (a t) (bot t) eval
src/Verismith/Result.hs view
@@ -29,13 +29,15 @@ ) where +import Control.Monad (liftM) import Control.Monad.Base import Control.Monad.IO.Class import Control.Monad.Trans.Class import Control.Monad.Trans.Control import Data.Bifunctor (Bifunctor (..)) import Shelly (RunFailed (..), Sh, catch_sh)-import Shelly.Lifted (MonadSh, liftSh)+import Shelly.Lifted (MonadSh, MonadShControl, ShM,+ liftSh, liftShWith, restoreSh) -- | Result type which is equivalent to 'Either' or 'Error'. This is -- reimplemented so that there is full control over the 'Monad' definition and@@ -133,6 +135,16 @@ restoreM = defaultRestoreM {-# INLINABLE liftBaseWith #-} {-# INLINABLE restoreM #-}++instance (MonadShControl m)+ => MonadShControl (ResultT a m) where+ newtype ShM (ResultT a m) b = ResultTShM (ShM m (Result a b))+ liftShWith f =+ ResultT $ liftM return $ liftShWith $ \runInSh -> f $ \k ->+ liftM ResultTShM $ runInSh $ runResultT k+ restoreSh (ResultTShM m) = ResultT . restoreSh $ m+ {-# INLINE liftShWith #-}+ {-# INLINE restoreSh #-} infix 0 <?>
verismith.cabal view
@@ -1,5 +1,5 @@ name: verismith-version: 0.6.0.0+version: 0.6.0.1 synopsis: Random verilog generation and simulator testing. description: Verismith provides random verilog generation modules@@ -27,7 +27,7 @@ source-repository this type: git location: https://github.com/ymherklotz/verismith- tag: v0.6.0.0+ tag: v0.6.0.1 custom-setup setup-depends: