diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,6 +1,13 @@
-# 5.0.2
+# 5.0.3: Maintenance release
 
-This is a maintenance release:
+  * Fixed constraints for Semigroup-Monoid-Proposal
+  * Fixed flags for older GHCs
+
+Contributors:
+
+  * [Pavel Krajcevski](https://github.com/Mokosha)
+
+# 5.0.2: Maintenance release
 
   * Moved to Git and GitHub.
   * Relaxed profunctors dependency (finally).
diff --git a/Control/Wire/Session.hs b/Control/Wire/Session.hs
--- a/Control/Wire/Session.hs
+++ b/Control/Wire/Session.hs
@@ -30,7 +30,7 @@
 import Control.Monad.IO.Class
 import Data.Data
 import Data.Foldable (Foldable)
-import Data.Monoid
+import Data.Semigroup
 import Data.Time.Clock
 import Data.Traversable (Traversable)
 
@@ -66,17 +66,18 @@
     deriving (Data, Eq, Foldable, Functor,
               Ord, Read, Show, Traversable, Typeable)
 
-instance (Monoid s, Real t) => HasTime t (Timed t s) where
+instance (Semigroup s, Monoid s, Real t) => HasTime t (Timed t s) where
     dtime (Timed dt _) = dt
 
-instance (Monoid s, Num t) => Monoid (Timed t s) where
-    mempty = Timed 0 mempty
-
-    mappend (Timed dt1 ds1) (Timed dt2 ds2) =
+instance (Semigroup s, Num t) => Semigroup (Timed t s) where
+    Timed dt1 ds1 <> Timed dt2 ds2 =
         let dt = dt1 + dt2
             ds = ds1 <> ds2
         in dt `seq` ds `seq` Timed dt ds
 
+instance (Semigroup s, Monoid s, Num t) => Monoid (Timed t s) where
+    mempty = Timed 0 mempty
+    mappend = (<>)
 
 -- | State delta generator for a real time clock.
 
diff --git a/netwire.cabal b/netwire.cabal
--- a/netwire.cabal
+++ b/netwire.cabal
@@ -1,5 +1,5 @@
 name:     netwire
-version:  5.0.2
+version:  5.0.3
 category: FRP
 synopsis: Functional reactive programming library
 
@@ -41,7 +41,10 @@
         transformers >= 0.3  && < 1,
         time         >= 1.4  && < 2
     default-language: Haskell2010
-    ghc-options: -W -fdefer-typed-holes
+    if impl(ghc >= 7.10.1)
+        ghc-options: -W -fdefer-typed-holes
+    else
+        ghc-options: -W
     exposed-modules:
         Control.Wire
         Control.Wire.Core