netlist 0.2 → 0.3.1
raw patch · 4 files changed
+55/−52 lines, 4 filesnew-uploader
Files
- Language/Netlist/AST.hs +41/−33
- Language/Netlist/Examples.hs +6/−7
- Language/Netlist/Util.hs +4/−8
- netlist.cabal +4/−4
Language/Netlist/AST.hs view
@@ -74,8 +74,12 @@ -- The first range is the most significant dimension. -- So, @MemDecl x (0, 31) (7, 0)@ corresponds to the following in Verilog: -- @reg [7:0] x [0:31]@- | MemDecl Ident (Maybe Range) (Maybe Range)+ | MemDecl Ident (Maybe Range) (Maybe Range) (Maybe [Expr]) + -- | These are permanent assignments to memory locations,+ -- of the form mem[addr] = val+ | MemAssign Ident Expr Expr+ -- | A module/entity instantiation. The arguments are the name of the module, -- the name of the instance, the parameter assignments, the input port -- connections, and the output port connections.@@ -88,20 +92,8 @@ -- declare an external module entity -- TODO: ExternDecl ExternLang - -- | A general process construct, compatible with both VHDL and Verilog- -- processes. It supports positive and negative edge triggers and a body (a- -- statement) for each trigger. Here are loose semantics of a process- -- @[(trigger0, stmt0), (trigger1, stmt1)...]@:- --- -- @- -- if trigger0- -- statement0- -- else if- -- trigger1- -- ...- -- @-- | ProcessDecl [(Event, Stmt)]+ -- | A sequential process with clock and (optional) asynchronous reset.+ | ProcessDecl Event (Maybe (Event, Stmt)) Stmt -- | A statement that executes once at the beginning of simulation. -- Equivalent to Verilog \"initial\" statement.@@ -132,9 +124,6 @@ data Edge = PosEdge | NegEdge- | AsyncHigh- | AsyncLow- -- TODO: AnyEdge? deriving (Eq, Ord, Show, Data, Typeable) -- | Expr is a combination of VHDL and Verilog expressions.@@ -232,6 +221,7 @@ | LessThan | LessEqual | GreaterThan | GreaterEqual -- relational | And | Nand | Or | Nor | Xor | Xnor -- bitwise | ShiftLeft | ShiftRight | RotateLeft | RotateRight -- shift/rotate+ | ShiftLeftArith | ShiftRightArith -- arithmetical shift deriving (Eq, Ord, Show, Data, Typeable) -- -----------------------------------------------------------------------------@@ -264,21 +254,28 @@ NetAssign x1 x2 -> do putWord8 1 put x1 put x2- MemDecl x1 x2 x3 -> do putWord8 2- put x1- put x2- put x3- InstDecl x1 x2 x3 x4 x5 -> do putWord8 3+ MemDecl x1 x2 x3 x4 -> do putWord8 2+ put x1+ put x2+ put x3+ put x4+ MemAssign x1 x2 x3 -> do putWord8 3+ put x1+ put x2+ put x3+ InstDecl x1 x2 x3 x4 x5 -> do putWord8 4 put x1 put x2 put x3 put x4 put x5- ProcessDecl x1 -> do putWord8 4- put x1- InitProcessDecl x1 -> do putWord8 5+ ProcessDecl x1 x2 x3 -> do putWord8 5+ put x1+ put x2+ put x3+ InitProcessDecl x1 -> do putWord8 6 put x1- CommentDecl x1 -> do putWord8 6+ CommentDecl x1 -> do putWord8 7 put x1 get = do i <- getWord8@@ -293,18 +290,25 @@ 2 -> do x1 <- get x2 <- get x3 <- get- return (MemDecl x1 x2 x3)+ x4 <- get+ return (MemDecl x1 x2 x3 x4) 3 -> do x1 <- get x2 <- get x3 <- get+ return (MemAssign x1 x2 x3)+ 4 -> do x1 <- get+ x2 <- get+ x3 <- get x4 <- get x5 <- get return (InstDecl x1 x2 x3 x4 x5)- 4 -> do x1 <- get- return (ProcessDecl x1) 5 -> do x1 <- get- return (InitProcessDecl x1)+ x2 <- get+ x3 <- get+ return (ProcessDecl x1 x2 x3) 6 -> do x1 <- get+ return (InitProcessDecl x1)+ 7 -> do x1 <- get return (CommentDecl x1) _ -> error "Corrupted binary data for Decl" @@ -332,8 +336,8 @@ instance Binary Edge where put x = case x of- PosEdge -> putWord8 0- NegEdge -> putWord8 1+ PosEdge -> putWord8 0+ NegEdge -> putWord8 1 get = do i <- getWord8 case i of@@ -564,6 +568,8 @@ ShiftRight -> putWord8 23 RotateLeft -> putWord8 24 RotateRight -> putWord8 25+ ShiftLeftArith -> putWord8 26+ ShiftRightArith -> putWord8 27 get = do i <- getWord8 case i of@@ -593,5 +599,7 @@ 23 -> return ShiftRight 24 -> return RotateLeft 25 -> return RotateRight+ 26 -> return ShiftLeftArith+ 27 -> return ShiftRightArith _ -> error "Corrupted binary data for BinaryOp" -- GENERATED STOP
Language/Netlist/Examples.hs view
@@ -30,13 +30,12 @@ ds :: [Decl] ds = [ NetDecl "a" (makeRange Down 16) (Just (ExprVar "x")) , NetDecl "b" (makeRange Down 16) (Just (sizedInteger 16 10))- , MemDecl "c" Nothing (makeRange Down 16)- , ProcessDecl- [ (Event (ExprVar "reset") PosEdge, Assign (ExprVar "c") (sizedInteger 16 0))- , (Event (ExprVar "clk") PosEdge, If (ExprVar "enable")- (Assign (ExprVar "c") (ExprVar "x"))- Nothing)- ]+ , MemDecl "c" Nothing (makeRange Down 16) Nothing+ , ProcessDecl (Event (ExprVar "clk") PosEdge)+ (Just (Event (ExprVar "reset") PosEdge, (Assign (ExprVar "c") (sizedInteger 16 0))))+ (If (ExprVar "enable")+ (Assign (ExprVar "c") (ExprVar "x"))+ Nothing) ] var_exprs :: [Expr]
Language/Netlist/Util.hs view
@@ -89,15 +89,11 @@ generateReg :: Expr -> Expr -> Maybe (Expr, Expr) -> Maybe (Expr, Expr) -> Maybe Expr -> Expr -> Decl generateReg x clk mb_reset mb_restart mb_enable expr- = ProcessDecl as+ = ProcessDecl (Event clk PosEdge) mb_reset' stmt2 where- as = case mb_reset of- Just (reset, initial)- -> [ (Event reset PosEdge, Assign x initial), a0]- Nothing- -> [a0]-- a0 = (Event clk PosEdge, stmt2)+ mb_reset' = case mb_reset of+ Just (reset, initial) -> Just (Event reset PosEdge, Assign x initial)+ Nothing -> Nothing stmt2 = case mb_restart of Just (restart, initial)
netlist.cabal view
@@ -1,5 +1,5 @@ name: netlist-version: 0.2+version: 0.3.1 synopsis: Netlist AST description: A very simplified and generic netlist designed to be compatible with Hardware Description Languages (HDLs) like Verilog and VHDL.@@ -8,9 +8,9 @@ license: BSD3 license-file: LICENSE copyright: Copyright (c) 2010 Signali Corp.- Copyright (c) 2010 Philip Weaver-author: Philip Weaver-maintainer: philip.weaver@gmail.com+ Copyright (c) 2010 Philip Weaver.+author: Philip Weaver <philip.weaver@gmail.com>+maintainer: andygill@ku.edu package-url: git://github.com/pheaver/netlist-verilog.git build-type: Simple cabal-version: >=1.6