diff --git a/Language/Netlist/GenVHDL.hs b/Language/Netlist/GenVHDL.hs
--- a/Language/Netlist/GenVHDL.hs
+++ b/Language/Netlist/GenVHDL.hs
@@ -16,7 +16,7 @@
 import Language.Netlist.AST
 
 import Text.PrettyPrint
-import Data.Maybe(catMaybes)
+import Data.Maybe(catMaybes, mapMaybe)
 
 
 -- | Generate a 'Language.Netlist.AST.Module' as a VHDL file . The ['String'] argument
@@ -56,8 +56,7 @@
                  text "end" <+> text "architecture" <+> text "str" <> semi
 
 decls :: [Decl] -> Doc
-decls [] = empty
-decls ds = (vcat $ punctuate semi $ catMaybes $ map decl ds) <> semi
+decls = vcat . map (<> semi) . mapMaybe decl
 
 decl :: Decl -> Maybe Doc
 decl (NetDecl i r Nothing) = Just $
@@ -82,10 +81,7 @@
 decl _d = Nothing
 
 insts ::  [Decl] -> Doc
-insts [] = empty
-insts is = case catMaybes $ zipWith inst gensyms is of
-             [] -> empty
-             is' -> (vcat $ punctuate semi is') <> semi
+insts = vcat . map (<> semi) . catMaybes . zipWith inst gensyms
   where gensyms = ["proc" ++ show i | i <- [(0::Integer)..]]
 
 inst :: String -> Decl -> Maybe Doc
diff --git a/netlist-to-vhdl.cabal b/netlist-to-vhdl.cabal
--- a/netlist-to-vhdl.cabal
+++ b/netlist-to-vhdl.cabal
@@ -1,5 +1,5 @@
 name:           netlist-to-vhdl
-version:        0.3.1
+version:        0.3.2
 synopsis:       Convert a Netlist AST to VHDL
 description:    Convert a Netlist AST to VHDL
 category:       Language
@@ -8,7 +8,7 @@
 copyright:      Copyright (c) 2010 University of Kansas
 author:         Garrin Kimmell
 maintainer:     garrin.kimmell@gmail.com
-package-url:    git://github.com/pheaver/netlist-verilog.git
+package-url:    git://github.com/ku-fpg/netlist.git
 build-type:     Simple
 cabal-version:  >=1.6
 
@@ -27,3 +27,12 @@
      build-depends:   base == 4.*
   else
      build-depends:   base == 3.*
+
+source-repository head
+  type:     git
+  location: git://github.com/ku-fpg/netlist.git
+
+source-repository this
+  type:     git
+  location: git://github.com/ku-fpg/netlist.git
+  tag:      netlist-to-vhdl-0.3.2