netlist-to-vhdl 0.2 → 0.3.1

raw patch · 2 files changed

+40/−37 lines, 2 filesdep ~netlistnew-uploaderPVP ok

version bump matches the API change (PVP)

Dependency ranges changed: netlist

API changes (from Hackage documentation)

Files

• Language/Netlist/GenVHDL.hs +38/−35
• netlist-to-vhdl.cabal +2/−2

@@ -17,7 +17,6 @@  import Text.PrettyPrint import Data.Maybe(catMaybes)-import Data.List(nub)   -- | Generate a 'Language.Netlist.AST.Module' as a VHDL file . The ['String'] argument@@ -67,20 +66,21 @@ decl (NetDecl i r (Just init)) = Just $   text "signal" <+> text i <+> colon <+> slv_type r <+> text ":=" <+> expr init -decl (MemDecl i Nothing dsize) = Just $+decl (MemDecl i Nothing dsize Nothing) = Just $     text "signal" <+> text i <+> colon <+> slv_type dsize -decl (MemDecl i (Just asize) dsize) = Just $+decl (MemDecl i (Just asize) dsize def) = Just $   text "type" <+> mtype  <+> text "is" <+>        text "array" <+> range asize <+> text "of" <+> slv_type dsize <> semi $$-  text "signal" <+> text i <> text "_ram" <+> colon <+> mtype- where mtype = text i <> text "_memory_type"+  text "signal" <+> text i <+> colon <+> mtype <> def_txt+ where mtype = text i <> text "_type"+       def_txt = case def of+                  Nothing -> empty+                  Just [xs] -> empty <+> text ":=" <+> parens (text "0 =>" <+> expr xs)+                  Just xs -> empty <+> text ":=" <+> parens (vcat $ punctuate comma (map expr xs))  decl _d = Nothing --- insts ::  [Decl] -> Doc insts [] = empty insts is = case catMaybes $ zipWith inst gensyms is of@@ -90,14 +90,39 @@  inst :: String -> Decl -> Maybe Doc inst _ (NetAssign i e) = Just $ text i <+> text "<=" <+> expr e+inst _ (MemAssign i idx e) = Just $ text i <> parens (expr idx) <+> text "<=" <+> expr e -inst gensym proc@(ProcessDecl evs) = Just $+inst gensym (ProcessDecl (Event clk edge) Nothing s) = Just $     text gensym <+> colon <+> text "process" <> senlist <+> text "is" $$     text "begin" $$-    nest 2 (pstmts evs) $$+    nest 2 (text "if" <+> nest 2 event <+> text "then" $$+            nest 2 (stmt s) $$+            text "end if" <> semi) $$     text "end process" <+> text gensym-  where senlist = parens $ cat $ punctuate comma $ map expr $   mkSensitivityList proc+  where+    senlist = parens $ expr clk+    event   = case edge of+                PosEdge -> text "rising_edge" <> parens (expr clk)+                NegEdge -> text "falling_edge" <> parens (expr clk) +inst gensym (ProcessDecl (Event clk clk_edge)+             (Just (Event reset reset_edge, reset_stmt)) s) = Just $+    text gensym <+> colon <+> text "process" <> senlist <+> text "is" $$+    text "begin" $$+    nest 2 (text "if" <+> nest 2 reset_event <+> text "then" $$+            nest 2 (stmt reset_stmt) $$+            text "elsif" <+> nest 2 clk_event <+> text "then" $$+            nest 2 (stmt s) $$+            text "end if" <> semi) $$+    text "end process" <+> text gensym+  where+    senlist     = parens $ cat $ punctuate comma $ map expr [ clk, reset ]+    clk_event   = case clk_edge of+                    PosEdge -> text "rising_edge" <> parens (expr clk)+                    NegEdge -> text "falling_edge" <> parens (expr clk)+    reset_event = case reset_edge of+                    PosEdge -> expr reset <+> text "= '1'"+                    NegEdge -> expr reset <+> text "= '0'"   inst _ (InstDecl nm inst gens ins outs) = Just $@@ -130,18 +155,6 @@  inst _ _d = Nothing -pstmts :: [(Event, Stmt)] -> Doc-pstmts ss = (vcat $ zipWith mkIf is ss)  $$ text "end if" <> semi-  where is = (text "if"):(repeat (text "elsif"))-        mkIf i (p,s) = i <+> nest 2 (event p) <+> text "then" $$-                       nest 2 (stmt s)--event :: Event -> Doc-event (Event i PosEdge)   = text "rising_edge" <> parens (expr i)-event (Event i NegEdge)   = text "falling_edge" <> parens (expr i)-event (Event i AsyncHigh) = expr i <+> text "= '1'"-event (Event i AsyncLow)  = expr i <+> text "= '0'"- stmt :: Stmt -> Doc stmt (Assign l r) = expr l <+> text "<=" <+> expr r <> semi stmt (Seq ss) = vcat (map stmt ss)@@ -215,18 +228,6 @@ expr x = text (show x)  --- | mkSensitivityList takes a process and extracts the appropriate sensitify list-----mkSensitivityList :: Decl -> [Expr]-mkSensitivityList (ProcessDecl evs) = nub event_names-  where event_names =-	 	--   AJG: This is now *only* based on the 'Event' vars, nothing else.-		map (\ (e,_) -> case e of-				 Event (ExprVar name) _ -> ExprVar name-				 _ -> error $ "strange form for mkSensitivityList " ++ show e-		    ) evs- lookupUnary :: UnaryOp -> Doc -> Doc lookupUnary op e = text (unOp op) <> parens e @@ -274,6 +275,8 @@ binOp ShiftRight = "srl" binOp RotateLeft = "rol" binOp RotateRight = "ror"+binOp ShiftLeftArith = "sla"+binOp ShiftRightArith = "sra"  slv_type :: Maybe Range -> Doc slv_type Nothing = text "std_logic"

@@ -1,5 +1,5 @@ name:           netlist-to-vhdl-version:        0.2+version:        0.3.1 synopsis:       Convert a Netlist AST to VHDL description:    Convert a Netlist AST to VHDL category:       Language@@ -21,7 +21,7 @@    exposed-modules:      Language.Netlist.GenVHDL -  build-depends:        netlist == 0.2, pretty >= 1.0+  build-depends:        netlist >= 0.3.1 && < 0.4, pretty >= 1.0    if flag(base4)      build-depends:   base == 4.*