lion 0.3.0.0 → 0.4.0.0

raw patch · 9 files changed

+77/−59 lines, 9 filesdep ~basedep ~clash-preludedep ~ice40-primPVP ok

version bump matches the API change (PVP)

Dependency ranges changed: base, clash-prelude, ice40-prim, lens

API changes (from Hackage documentation)

Files

• CHANGELOG.md +4/−0
• LICENSE +1/−1
• README.md +4/−0
• lion.cabal +6/−6
• src/Lion/Alu.hs +35/−17
• src/Lion/Core.hs +15/−19
• src/Lion/Instruction.hs +1/−1
• src/Lion/Pipe.hs +10/−14
• src/Lion/Rvfi.hs +1/−1

@@ -1,5 +1,9 @@ # Revision history for lion +## 0.4.0.0+* Update clash-prelude dependency bounds #4+* Type-level -> data-level configuration #6+ ## 0.3.0.0  * Update base dependency version bounds

@@ -1,6 +1,6 @@ BSD 3-Clause License -Copyright (c) 2021, David Cox+Copyright (c) 2024, David Cox All rights reserved.  Redistribution and use in source and binary forms, with or without

@@ -37,6 +37,10 @@  Check out the [Lion Development project](https://github.com/standardsemiconductor/lion/projects/1) to see which features are in progress. +## References and Additional Resources+* [RISC-V Specifications](https://riscv.org/technical/specifications/)+* [Computer Architecture: A Quantitative Approach 6th Ed.](https://www.elsevier.com/books/computer-architecture/hennessy/978-0-12-811905-1)+ [hackage]:            <https://hackage.haskell.org/package/lion> [hackage-badge]:      <https://img.shields.io/hackage/v/lion.svg?color=success> [hackage-deps-badge]: <https://img.shields.io/hackage-deps/v/lion.svg>

@@ -1,6 +1,6 @@ cabal-version:      2.4 name:               lion-version:            0.3.0.0+version:            0.4.0.0 synopsis:           RISC-V Core description:        Lion is a formally verified, 5-stage pipeline [RISC-V](https://riscv.org) core. Lion targets the [VELDT FPGA development board](https://standardsemiconductor.com) and is written in Haskell using [Clash](https://clash-lang.org). bug-reports:        https://github.com/standardsemiconductor/lion/issues@@ -8,7 +8,7 @@ license-file:       LICENSE author:             dopamane <standard.semiconductor@gmail.com> maintainer:         dopamane <standard.semiconductor@gmail.com>-copyright:          (c) 2021 David Cox+copyright:          (c) 2021-2024 David Cox category:           Hardware extra-source-files:     CHANGELOG.md@@ -27,12 +27,12 @@   hs-source-dirs: src   default-language: Haskell2010   build-depends: -    base           >= 4.13  && < 4.16,+    base           >= 4.13  && < 4.17,     generic-monoid >= 0.1   && < 0.2,     mtl            >= 2.2   && < 2.3,-    lens           >= 4.19  && < 5.1,-    ice40-prim     >= 0.3   && < 0.4,-    clash-prelude  >= 1.2.5 && < 1.5,+    lens           >= 4.19  && < 5.2,+    ice40-prim     >= 0.3   && < 0.3.1.4,+    clash-prelude  >= 1.2.5 && < 1.7,     ghc-typelits-natnormalise,     ghc-typelits-extra,     ghc-typelits-knownnat

@@ -1,7 +1,7 @@ {-|  Module      : Lion.Alu Description : Lion arithmetic logic unit-Copyright   : (c) David Cox, 2021+Copyright   : (c) David Cox, 2021-2024 License     : BSD-3-Clause Maintainer  : standardsemiconductor@gmail.com @@ -12,25 +12,38 @@  import Clash.Prelude import Data.Function ( on )-import Data.Proxy-import Ice40.Mac -import Lion.Instruction+import Ice40.Mac (+  Input(..),+  Parameter(..),+  defaultInput,+  defaultParameter,+  mac+  )+import Lion.Instruction (Op(..))  -- | ALU configuration data AluConfig = Hard -- ^ use hard adder and subtractor from iCE40 SB_MAC16                | Soft -- ^ use generic adder and subtractor: (+) and (-)   deriving stock (Generic, Show, Eq) -class Alu (config :: AluConfig) where-  alu :: HiddenClockResetEnable dom -      => Proxy (config :: AluConfig)-      -> Signal dom Op-      -> Signal dom (BitVector 32)-      -> Signal dom (BitVector 32)-      -> Signal dom (BitVector 32)+alu+  :: HiddenClockResetEnable dom+  => AluConfig+  -> Signal dom Op+  -> Signal dom (BitVector 32)+  -> Signal dom (BitVector 32)+  -> Signal dom (BitVector 32)+alu = \case+  Hard -> hardAlu+  Soft -> softAlu -instance Alu 'Soft where-  alu _ op in1 = register 0 . liftA3 aluFunc op in1 +softAlu+ :: HiddenClockResetEnable dom+ => Signal dom Op+ -> Signal dom (BitVector 32)+ -> Signal dom (BitVector 32)+ -> Signal dom (BitVector 32)+softAlu op in1 = register 0 . liftA3 aluFunc op in1     where       aluFunc = \case          Add  -> (+)@@ -47,9 +60,14 @@           shamt = unpack . resize . slice d4 d0           sign = unpack :: BitVector 32 -> Signed 32           (...) = (.).(.)-      -instance Alu 'Hard where-  alu _ op in1 in2 = mux isAddSub adderSubtractor $ register 0 $ baseAlu op in1 in2++hardAlu+  :: HiddenClockResetEnable dom+  => Signal dom Op+  -> Signal dom (BitVector 32)+  -> Signal dom (BitVector 32)+  -> Signal dom (BitVector 32)+hardAlu op in1 in2 = mux isAddSub adderSubtractor $ register 0 $ baseAlu op in1 in2     where       isAdd = (Add == ) <$> op       isSub = (Sub == ) <$> op@@ -80,7 +98,7 @@ -- | addSub32PipelinedUnsigned hardAddSub   :: HiddenClock dom-  => Signal dom Bit -- 0 = Add, 1 = Sub+  => Signal dom Bit -- ^ 0 = Add, 1 = Sub   -> Signal dom (BitVector 32)   -> Signal dom (BitVector 32)   -> Signal dom (BitVector 32)

@@ -1,7 +1,7 @@ {-| Module      : Lion.Core Description : Lion RISC-V Core-Copyright   : (c) David Cox, 2021+Copyright   : (c) David Cox, 2024 License     : BSD-3-Clause Maintainer  : standardsemiconductor@gmail.com @@ -18,11 +18,9 @@   , FromCore(..)   , P.ToMem(..)   , P.MemoryAccess(..)-  , Alu   ) where  import Clash.Prelude-import Data.Proxy import Data.Maybe import Data.Monoid import Lion.Alu@@ -31,21 +29,21 @@ import qualified Lion.Instruction as I (Op(Add))  -- | Core configuration------ ALU configuration default: `Soft`-newtype CoreConfig (startPC :: Nat) (a :: AluConfig) = CoreConfig-  { pipeConfig :: P.PipeConfig (startPC :: Nat) -- ^ pipeline configuration+data CoreConfig = CoreConfig+  { aluConfig  :: AluConfig    -- ^ ALU configuration, default: `Soft`+  , pipeConfig :: P.PipeConfig -- ^ pipeline configuration   }   deriving stock (Generic, Show, Eq)  -- | Default core configuration ----- ALU configuration = `Soft`+-- `aluConfig` = `Soft` ----- `pipeConfig` = `defaultPipeConfig`-defaultCoreConfig :: CoreConfig 0 'Soft+-- `pipeConfig` = `P.defaultPipeConfig`+defaultCoreConfig :: CoreConfig defaultCoreConfig = CoreConfig-  { pipeConfig = P.defaultPipeConfig+  { aluConfig  = Soft+  , pipeConfig = P.defaultPipeConfig   }  -- | Core outputs@@ -56,13 +54,10 @@  -- | RISC-V Core: RV32I core-  :: forall a startPC dom-   . HiddenClockResetEnable dom-  => Alu a-  => (KnownNat startPC, startPC <= 0xFFFFFFFF)-  => CoreConfig (startPC :: Nat) (a :: AluConfig) -- ^ core configuration-  -> Signal dom (BitVector 32)   -- ^ core input, from memory/peripherals-  -> FromCore dom                -- ^ core output+  :: HiddenClockResetEnable dom+  => CoreConfig                 -- ^ core configuration+  -> Signal dom (BitVector 32)  -- ^ core input, from memory/peripherals+  -> FromCore dom               -- ^ core output core config toCore = FromCore   { toMem  = getFirst . P._toMem <$> fromPipe   , toRvfi = fromMaybe mkRvfi . getFirst . P._toRvfi <$> fromPipe@@ -72,7 +67,8 @@     aluOp = fromMaybe I.Add . getFirst . P._toAluOp     <$> fromPipe     aluInput1 = fromMaybe 0 . getFirst . P._toAluInput1 <$> fromPipe     aluInput2 = fromMaybe 0 . getFirst . P._toAluInput2 <$> fromPipe-    aluOutput = alu (Proxy :: Proxy a) aluOp aluInput1 aluInput2+    aluOutput = alu (aluConfig config) aluOp aluInput1 aluInput2+     -- reg bank connection     rs1Addr = fromMaybe 0 . getFirst . P._toRs1Addr <$> fromPipe     rs2Addr = fromMaybe 0 . getFirst . P._toRs2Addr <$> fromPipe

@@ -1,7 +1,7 @@ {-| Module      : Lion.Instruction Description : RISC-V ISA-Copyright   : (c) David Cox, 2021+Copyright   : (c) David Cox, 2024 License     : BSD-3-Clause Maintainer  : standardsemiconductor@gmail.com -}

@@ -1,7 +1,7 @@ {-| Module      : Lion.Pipe Description : RISC-V 5-stage pipeline-Copyright   : (c) David Cox, 2021+Copyright   : (c) David Cox, 2024 License     : BSD-3-Clause Maintainer  : standardsemiconductor@gmail.com -}@@ -17,14 +17,15 @@ import Lion.Rvfi  -- | Pipeline configuration-data PipeConfig (startPC :: Nat) = PipeConfig-  deriving stock (Generic, Show, Eq)+newtype PipeConfig = PipeConfig+  { startPC :: BitVector 32 -- ^ start program counter+  } deriving stock (Generic, Show, Eq)  -- | Default pipeline configuration --  -- `startPC` = 0-defaultPipeConfig :: PipeConfig 0-defaultPipeConfig = PipeConfig+defaultPipeConfig :: PipeConfig+defaultPipeConfig = PipeConfig 0  -- | Pipeline inputs data ToPipe = ToPipe@@ -151,13 +152,9 @@   deriving anyclass NFDataX makeLenses ''Pipe -mkPipe -  :: forall startPC-   . (KnownNat startPC, startPC <= 0xFFFFFFFF)-  => PipeConfig (startPC :: Nat) -  -> Pipe-mkPipe _ = Pipe-  { _fetchPC = natToNum @startPC+mkPipe :: PipeConfig -> Pipe+mkPipe pipeConfig = Pipe+  { _fetchPC = startPC pipeConfig    -- decode stage    , _dePC    = 0@@ -185,8 +182,7 @@ -- | 5-Stage RISC-V pipeline pipe    :: HiddenClockResetEnable dom-  => (KnownNat startPC, startPC <= 0xFFFFFFFF)-  => PipeConfig (startPC :: Nat)+  => PipeConfig   -> Signal dom ToPipe   -> Signal dom FromPipe pipe config = mealy pipeMealy (mkPipe config)

@@ -1,7 +1,7 @@ {-| Module      : Lion.Rvfi Description : Lion RISC-V Formal Verification Interface-Copyright   : (c) David Cox, 2021+Copyright   : (c) David Cox, 2024 License     : BSD-3-Clause Maintainer  : standardsemiconductor@gmail.com