language-vhdl 0.1.1.0 → 0.1.2.0
raw patch · 3 files changed
+163/−46 lines, 3 filesPVP: major bump suggested
API removals or changes: PVP suggests a major version bump
API changes (from Hackage documentation)
- Language.VHDL.Pretty: instance Pretty AbstractLiteral
- Language.VHDL.Pretty: instance Pretty AccessTypeDefinition
- Language.VHDL.Pretty: instance Pretty ActualDesignator
- Language.VHDL.Pretty: instance Pretty ActualPart
- Language.VHDL.Pretty: instance Pretty AddingOperator
- Language.VHDL.Pretty: instance Pretty Aggregate
- Language.VHDL.Pretty: instance Pretty AliasDeclaration
- Language.VHDL.Pretty: instance Pretty AliasDesignator
- Language.VHDL.Pretty: instance Pretty Allocator
- Language.VHDL.Pretty: instance Pretty ArchitectureBody
- Language.VHDL.Pretty: instance Pretty ArrayTypeDefinition
- Language.VHDL.Pretty: instance Pretty Assertion
- Language.VHDL.Pretty: instance Pretty AssertionStatement
- Language.VHDL.Pretty: instance Pretty AssociationElement
- Language.VHDL.Pretty: instance Pretty AssociationList
- Language.VHDL.Pretty: instance Pretty AttributeDeclaration
- Language.VHDL.Pretty: instance Pretty AttributeName
- Language.VHDL.Pretty: instance Pretty AttributeSpecification
- Language.VHDL.Pretty: instance Pretty Base
- Language.VHDL.Pretty: instance Pretty BaseSpecifier
- Language.VHDL.Pretty: instance Pretty BaseUnitDeclaration
- Language.VHDL.Pretty: instance Pretty BasedInteger
- Language.VHDL.Pretty: instance Pretty BasedLiteral
- Language.VHDL.Pretty: instance Pretty BasicCharacter
- Language.VHDL.Pretty: instance Pretty BasicGraphicCharacter
- Language.VHDL.Pretty: instance Pretty BasicIdentifier
- Language.VHDL.Pretty: instance Pretty BindingIndication
- Language.VHDL.Pretty: instance Pretty BitStringLiteral
- Language.VHDL.Pretty: instance Pretty BitValue
- Language.VHDL.Pretty: instance Pretty BlockConfiguration
- Language.VHDL.Pretty: instance Pretty BlockDeclarativeItem
- Language.VHDL.Pretty: instance Pretty BlockHeader
- Language.VHDL.Pretty: instance Pretty BlockSpecification
- Language.VHDL.Pretty: instance Pretty BlockStatement
- Language.VHDL.Pretty: instance Pretty CaseStatement
- Language.VHDL.Pretty: instance Pretty CaseStatementAlternative
- Language.VHDL.Pretty: instance Pretty CharacterLiteral
- Language.VHDL.Pretty: instance Pretty Choice
- Language.VHDL.Pretty: instance Pretty Choices
- Language.VHDL.Pretty: instance Pretty ComponentConfiguration
- Language.VHDL.Pretty: instance Pretty ComponentDeclaration
- Language.VHDL.Pretty: instance Pretty ComponentInstantiationStatement
- Language.VHDL.Pretty: instance Pretty ComponentSpecification
- Language.VHDL.Pretty: instance Pretty CompositeTypeDefinition
- Language.VHDL.Pretty: instance Pretty ConcurrentAssertionStatement
- Language.VHDL.Pretty: instance Pretty ConcurrentProcedureCallStatement
- Language.VHDL.Pretty: instance Pretty ConcurrentSignalAssignmentStatement
- Language.VHDL.Pretty: instance Pretty ConcurrentStatement
- Language.VHDL.Pretty: instance Pretty ConditionClause
- Language.VHDL.Pretty: instance Pretty ConditionalSignalAssignment
- Language.VHDL.Pretty: instance Pretty ConditionalWaveforms
- Language.VHDL.Pretty: instance Pretty ConfigurationDeclaration
- Language.VHDL.Pretty: instance Pretty ConfigurationDeclarativeItem
- Language.VHDL.Pretty: instance Pretty ConfigurationItem
- Language.VHDL.Pretty: instance Pretty ConfigurationSpecification
- Language.VHDL.Pretty: instance Pretty ConstantDeclaration
- Language.VHDL.Pretty: instance Pretty ConstrainedArrayDefinition
- Language.VHDL.Pretty: instance Pretty Constraint
- Language.VHDL.Pretty: instance Pretty ContextClause
- Language.VHDL.Pretty: instance Pretty ContextItem
- Language.VHDL.Pretty: instance Pretty DecimalLiteral
- Language.VHDL.Pretty: instance Pretty Declaration
- Language.VHDL.Pretty: instance Pretty DelayMechanism
- Language.VHDL.Pretty: instance Pretty DesignFile
- Language.VHDL.Pretty: instance Pretty DesignUnit
- Language.VHDL.Pretty: instance Pretty Designator
- Language.VHDL.Pretty: instance Pretty Direction
- Language.VHDL.Pretty: instance Pretty DisconnectionSpecification
- Language.VHDL.Pretty: instance Pretty DiscreteRange
- Language.VHDL.Pretty: instance Pretty ElementAssociation
- Language.VHDL.Pretty: instance Pretty ElementDeclaration
- Language.VHDL.Pretty: instance Pretty EntityAspect
- Language.VHDL.Pretty: instance Pretty EntityClass
- Language.VHDL.Pretty: instance Pretty EntityClassEntry
- Language.VHDL.Pretty: instance Pretty EntityDeclaration
- Language.VHDL.Pretty: instance Pretty EntityDeclarativeItem
- Language.VHDL.Pretty: instance Pretty EntityDesignator
- Language.VHDL.Pretty: instance Pretty EntityHeader
- Language.VHDL.Pretty: instance Pretty EntityNameList
- Language.VHDL.Pretty: instance Pretty EntitySpecification
- Language.VHDL.Pretty: instance Pretty EntityStatement
- Language.VHDL.Pretty: instance Pretty EntityTag
- Language.VHDL.Pretty: instance Pretty EnumerationLiteral
- Language.VHDL.Pretty: instance Pretty EnumerationTypeDefinition
- Language.VHDL.Pretty: instance Pretty ExitStatement
- Language.VHDL.Pretty: instance Pretty Exponent
- Language.VHDL.Pretty: instance Pretty Expression
- Language.VHDL.Pretty: instance Pretty ExtendedDigit
- Language.VHDL.Pretty: instance Pretty ExtendedIdentifier
- Language.VHDL.Pretty: instance Pretty Factor
- Language.VHDL.Pretty: instance Pretty FileDeclaration
- Language.VHDL.Pretty: instance Pretty FileOpenInformation
- Language.VHDL.Pretty: instance Pretty FileTypeDefinition
- Language.VHDL.Pretty: instance Pretty FormalDesignator
- Language.VHDL.Pretty: instance Pretty FormalPart
- Language.VHDL.Pretty: instance Pretty FullTypeDeclaration
- Language.VHDL.Pretty: instance Pretty FunctionCall
- Language.VHDL.Pretty: instance Pretty GenerateStatement
- Language.VHDL.Pretty: instance Pretty GenerationScheme
- Language.VHDL.Pretty: instance Pretty GenericClause
- Language.VHDL.Pretty: instance Pretty GenericMapAspect
- Language.VHDL.Pretty: instance Pretty GraphicCharacter
- Language.VHDL.Pretty: instance Pretty GroupConstituent
- Language.VHDL.Pretty: instance Pretty GroupDeclaration
- Language.VHDL.Pretty: instance Pretty GroupTemplateDeclaration
- Language.VHDL.Pretty: instance Pretty GuardedSignalSpecification
- Language.VHDL.Pretty: instance Pretty Identifier
- Language.VHDL.Pretty: instance Pretty IfStatement
- Language.VHDL.Pretty: instance Pretty IncompleteTypeDeclaration
- Language.VHDL.Pretty: instance Pretty IndexConstraint
- Language.VHDL.Pretty: instance Pretty IndexSpecification
- Language.VHDL.Pretty: instance Pretty IndexSubtypeDefinition
- Language.VHDL.Pretty: instance Pretty IndexedName
- Language.VHDL.Pretty: instance Pretty InstantiatedUnit
- Language.VHDL.Pretty: instance Pretty InstantiationList
- Language.VHDL.Pretty: instance Pretty Integer
- Language.VHDL.Pretty: instance Pretty InterfaceDeclaration
- Language.VHDL.Pretty: instance Pretty InterfaceList
- Language.VHDL.Pretty: instance Pretty IterationScheme
- Language.VHDL.Pretty: instance Pretty Letter
- Language.VHDL.Pretty: instance Pretty LetterOrDigit
- Language.VHDL.Pretty: instance Pretty LibraryClause
- Language.VHDL.Pretty: instance Pretty LibraryUnit
- Language.VHDL.Pretty: instance Pretty Literal
- Language.VHDL.Pretty: instance Pretty LogicalName
- Language.VHDL.Pretty: instance Pretty LogicalNameList
- Language.VHDL.Pretty: instance Pretty LogicalOperator
- Language.VHDL.Pretty: instance Pretty LoopStatement
- Language.VHDL.Pretty: instance Pretty MiscellaneousOperator
- Language.VHDL.Pretty: instance Pretty Mode
- Language.VHDL.Pretty: instance Pretty MultiplyingOperator
- Language.VHDL.Pretty: instance Pretty Name
- Language.VHDL.Pretty: instance Pretty NextStatement
- Language.VHDL.Pretty: instance Pretty NullStatement
- Language.VHDL.Pretty: instance Pretty NumericLiteral
- Language.VHDL.Pretty: instance Pretty ObjectDeclaration
- Language.VHDL.Pretty: instance Pretty Options
- Language.VHDL.Pretty: instance Pretty PackageBody
- Language.VHDL.Pretty: instance Pretty PackageBodyDeclarativeItem
- Language.VHDL.Pretty: instance Pretty PackageDeclaration
- Language.VHDL.Pretty: instance Pretty PackageDeclarativeItem
- Language.VHDL.Pretty: instance Pretty ParameterSpecification
- Language.VHDL.Pretty: instance Pretty PhysicalLiteral
- Language.VHDL.Pretty: instance Pretty PhysicalTypeDefinition
- Language.VHDL.Pretty: instance Pretty PortClause
- Language.VHDL.Pretty: instance Pretty PortMapAspect
- Language.VHDL.Pretty: instance Pretty Prefix
- Language.VHDL.Pretty: instance Pretty Primary
- Language.VHDL.Pretty: instance Pretty PrimaryUnit
- Language.VHDL.Pretty: instance Pretty ProcedureCall
- Language.VHDL.Pretty: instance Pretty ProcedureCallStatement
- Language.VHDL.Pretty: instance Pretty ProcessDeclarativeItem
- Language.VHDL.Pretty: instance Pretty ProcessStatement
- Language.VHDL.Pretty: instance Pretty QualifiedExpression
- Language.VHDL.Pretty: instance Pretty Range
- Language.VHDL.Pretty: instance Pretty RangeConstraint
- Language.VHDL.Pretty: instance Pretty RecordTypeDefinition
- Language.VHDL.Pretty: instance Pretty Relation
- Language.VHDL.Pretty: instance Pretty RelationalOperator
- Language.VHDL.Pretty: instance Pretty ReportStatement
- Language.VHDL.Pretty: instance Pretty ReturnStatement
- Language.VHDL.Pretty: instance Pretty ScalarTypeDefinition
- Language.VHDL.Pretty: instance Pretty SecondaryUnit
- Language.VHDL.Pretty: instance Pretty SecondaryUnitDeclaration
- Language.VHDL.Pretty: instance Pretty SelectedName
- Language.VHDL.Pretty: instance Pretty SelectedSignalAssignment
- Language.VHDL.Pretty: instance Pretty SelectedWaveforms
- Language.VHDL.Pretty: instance Pretty SensitivityClause
- Language.VHDL.Pretty: instance Pretty SensitivityList
- Language.VHDL.Pretty: instance Pretty SequentialStatement
- Language.VHDL.Pretty: instance Pretty ShiftExpression
- Language.VHDL.Pretty: instance Pretty ShiftOperator
- Language.VHDL.Pretty: instance Pretty Sign
- Language.VHDL.Pretty: instance Pretty SignalAssignmentStatement
- Language.VHDL.Pretty: instance Pretty SignalDeclaration
- Language.VHDL.Pretty: instance Pretty SignalKind
- Language.VHDL.Pretty: instance Pretty SignalList
- Language.VHDL.Pretty: instance Pretty Signature
- Language.VHDL.Pretty: instance Pretty SimpleExpression
- Language.VHDL.Pretty: instance Pretty SliceName
- Language.VHDL.Pretty: instance Pretty StringLiteral
- Language.VHDL.Pretty: instance Pretty SubprogramBody
- Language.VHDL.Pretty: instance Pretty SubprogramDeclarativeItem
- Language.VHDL.Pretty: instance Pretty SubprogramKind
- Language.VHDL.Pretty: instance Pretty SubprogramSpecification
- Language.VHDL.Pretty: instance Pretty SubtypeDeclaration
- Language.VHDL.Pretty: instance Pretty SubtypeIndication
- Language.VHDL.Pretty: instance Pretty Suffix
- Language.VHDL.Pretty: instance Pretty Target
- Language.VHDL.Pretty: instance Pretty Term
- Language.VHDL.Pretty: instance Pretty TimeoutClause
- Language.VHDL.Pretty: instance Pretty TypeConversion
- Language.VHDL.Pretty: instance Pretty TypeDeclaration
- Language.VHDL.Pretty: instance Pretty TypeDefinition
- Language.VHDL.Pretty: instance Pretty TypeMark
- Language.VHDL.Pretty: instance Pretty UnconstrainedArrayDefinition
- Language.VHDL.Pretty: instance Pretty UseClause
- Language.VHDL.Pretty: instance Pretty VariableAssignmentStatement
- Language.VHDL.Pretty: instance Pretty VariableDeclaration
- Language.VHDL.Pretty: instance Pretty WaitStatement
- Language.VHDL.Pretty: instance Pretty Waveform
- Language.VHDL.Pretty: instance Pretty WaveformElement
- Language.VHDL.Pretty: instance Pretty a => Pretty [a]
- Language.VHDL.Syntax: ContextClause :: ContextClause
- Language.VHDL.Syntax: ContextItem :: ContextItem
- Language.VHDL.Syntax: DesignFile :: DesignFile
- Language.VHDL.Syntax: LogicalName :: LogicalName
- Language.VHDL.Syntax: PrimaryUnit :: PrimaryUnit
- Language.VHDL.Syntax: SecondaryUnit :: SecondaryUnit
- Language.VHDL.Syntax: agg_element_association :: Aggregate -> [ElementAssociation]
- Language.VHDL.Syntax: alias_designator :: AliasDeclaration -> AliasDesignator
- Language.VHDL.Syntax: alias_name :: AliasDeclaration -> Name
- Language.VHDL.Syntax: alias_signature :: AliasDeclaration -> Maybe Signature
- Language.VHDL.Syntax: alias_subtype_indication :: AliasDeclaration -> Maybe SubtypeIndication
- Language.VHDL.Syntax: aname_attribute_designator :: AttributeName -> AttributeDesignator
- Language.VHDL.Syntax: aname_expression :: AttributeName -> Maybe Expression
- Language.VHDL.Syntax: aname_prefix :: AttributeName -> Prefix
- Language.VHDL.Syntax: aname_signature :: AttributeName -> Maybe Signature
- Language.VHDL.Syntax: archi_declarative_part :: ArchitectureBody -> ArchitectureDeclarativePart
- Language.VHDL.Syntax: archi_entity_name :: ArchitectureBody -> Name
- Language.VHDL.Syntax: archi_identifier :: ArchitectureBody -> Identifier
- Language.VHDL.Syntax: archi_statement_part :: ArchitectureBody -> ArchitectureStatementPart
- Language.VHDL.Syntax: arrc_index_constraint :: ConstrainedArrayDefinition -> IndexConstraint
- Language.VHDL.Syntax: arrc_subtype_indication :: ConstrainedArrayDefinition -> SubtypeIndication
- Language.VHDL.Syntax: arru_element_subtype_indication :: UnconstrainedArrayDefinition -> (SubtypeIndication)
- Language.VHDL.Syntax: arru_index_subtype_definition :: UnconstrainedArrayDefinition -> [IndexSubtypeDefinition]
- Language.VHDL.Syntax: as_attribute_designator :: AttributeSpecification -> AttributeDesignator
- Language.VHDL.Syntax: as_entity_specification :: AttributeSpecification -> EntitySpecification
- Language.VHDL.Syntax: as_expression :: AttributeSpecification -> Expression
- Language.VHDL.Syntax: assoc_actual_part :: AssociationElement -> ActualPart
- Language.VHDL.Syntax: assoc_formal_part :: AssociationElement -> Maybe FormalPart
- Language.VHDL.Syntax: attr_identifier :: AttributeDeclaration -> Identifier
- Language.VHDL.Syntax: attr_type_marke :: AttributeDeclaration -> TypeMark
- Language.VHDL.Syntax: bi_entity_aspect :: BindingIndication -> Maybe EntityAspect
- Language.VHDL.Syntax: bi_generic_map_aspect :: BindingIndication -> Maybe GenericMapAspect
- Language.VHDL.Syntax: bi_port_map_aspect :: BindingIndication -> Maybe PortMapAspect
- Language.VHDL.Syntax: block_configuration_item :: BlockConfiguration -> [ConfigurationItem]
- Language.VHDL.Syntax: block_specification :: BlockConfiguration -> BlockSpecification
- Language.VHDL.Syntax: block_use_clause :: BlockConfiguration -> [UseClause]
- Language.VHDL.Syntax: blockh_generic_clause :: BlockHeader -> Maybe (GenericClause, Maybe GenericMapAspect)
- Language.VHDL.Syntax: blockh_port_clause :: BlockHeader -> Maybe (PortClause, Maybe PortMapAspect)
- Language.VHDL.Syntax: blocks_declarative_part :: BlockStatement -> BlockDeclarativePart
- Language.VHDL.Syntax: blocks_guard_expression :: BlockStatement -> Maybe Expression
- Language.VHDL.Syntax: blocks_header :: BlockStatement -> BlockHeader
- Language.VHDL.Syntax: blocks_label :: BlockStatement -> Label
- Language.VHDL.Syntax: blocks_statment_part :: BlockStatement -> BlockStatementPart
- Language.VHDL.Syntax: cas_assertion :: ConcurrentAssertionStatement -> Assertion
- Language.VHDL.Syntax: cas_label :: ConcurrentAssertionStatement -> Maybe Label
- Language.VHDL.Syntax: cas_postponed :: ConcurrentAssertionStatement -> Bool
- Language.VHDL.Syntax: case_alternatives :: CaseStatement -> [CaseStatementAlternative]
- Language.VHDL.Syntax: case_expression :: CaseStatement -> Expression
- Language.VHDL.Syntax: case_label :: CaseStatement -> Maybe Label
- Language.VHDL.Syntax: cis_generic_map_aspect :: ComponentInstantiationStatement -> Maybe GenericMapAspect
- Language.VHDL.Syntax: cis_instantiated_unit :: ComponentInstantiationStatement -> InstantiatedUnit
- Language.VHDL.Syntax: cis_instantiation_label :: ComponentInstantiationStatement -> Label
- Language.VHDL.Syntax: cis_port_map_aspect :: ComponentInstantiationStatement -> Maybe PortMapAspect
- Language.VHDL.Syntax: comp_binding_indication :: ComponentConfiguration -> Maybe BindingIndication
- Language.VHDL.Syntax: comp_block_configuration :: ComponentConfiguration -> Maybe BlockConfiguration
- Language.VHDL.Syntax: comp_identifier :: ComponentDeclaration -> Identifier
- Language.VHDL.Syntax: comp_local_generic_clause :: ComponentDeclaration -> Maybe GenericClause
- Language.VHDL.Syntax: comp_local_port_clause :: ComponentDeclaration -> Maybe PortClause
- Language.VHDL.Syntax: comp_simple_name :: ComponentDeclaration -> Maybe SimpleName
- Language.VHDL.Syntax: comp_specification :: ComponentConfiguration -> ComponentSpecification
- Language.VHDL.Syntax: config_block_configuration :: ConfigurationDeclaration -> BlockConfiguration
- Language.VHDL.Syntax: config_declarative_part :: ConfigurationDeclaration -> ConfigurationDeclarativePart
- Language.VHDL.Syntax: config_entity_name :: ConfigurationDeclaration -> Name
- Language.VHDL.Syntax: config_identifier :: ConfigurationDeclaration -> Identifier
- Language.VHDL.Syntax: const_expression :: ConstantDeclaration -> Maybe Expression
- Language.VHDL.Syntax: const_identifier_list :: ConstantDeclaration -> IdentifierList
- Language.VHDL.Syntax: const_subtype_indication :: ConstantDeclaration -> SubtypeIndication
- Language.VHDL.Syntax: cpcs_label :: ConcurrentProcedureCallStatement -> Maybe Label
- Language.VHDL.Syntax: cpcs_postponed :: ConcurrentProcedureCallStatement -> Bool
- Language.VHDL.Syntax: cpcs_procedure_call :: ConcurrentProcedureCallStatement -> ProcedureCall
- Language.VHDL.Syntax: cs_binding_indication :: ConfigurationSpecification -> BindingIndication
- Language.VHDL.Syntax: cs_component_name :: ComponentSpecification -> Name
- Language.VHDL.Syntax: cs_component_specification :: ConfigurationSpecification -> ComponentSpecification
- Language.VHDL.Syntax: cs_instantiation_list :: ComponentSpecification -> InstantiationList
- Language.VHDL.Syntax: csa_conditional_waveforms :: ConditionalSignalAssignment -> ConditionalWaveforms
- Language.VHDL.Syntax: csa_options :: ConditionalSignalAssignment -> Options
- Language.VHDL.Syntax: csa_target :: ConditionalSignalAssignment -> Target
- Language.VHDL.Syntax: csas_cond_label :: ConcurrentSignalAssignmentStatement -> Maybe Label
- Language.VHDL.Syntax: csas_cond_postponed :: ConcurrentSignalAssignmentStatement -> Bool
- Language.VHDL.Syntax: csas_cond_signal_assignment :: ConcurrentSignalAssignmentStatement -> ConditionalSignalAssignment
- Language.VHDL.Syntax: csas_select_label :: ConcurrentSignalAssignmentStatement -> Maybe Label
- Language.VHDL.Syntax: csas_select_postponed :: ConcurrentSignalAssignmentStatement -> Bool
- Language.VHDL.Syntax: csas_select_signal_assignment :: ConcurrentSignalAssignmentStatement -> SelectedSignalAssignment
- Language.VHDL.Syntax: cw_optional :: ConditionalWaveforms -> [(Waveform, Condition)]
- Language.VHDL.Syntax: cw_wave :: ConditionalWaveforms -> (Waveform, Maybe Condition)
- Language.VHDL.Syntax: data ContextClause
- Language.VHDL.Syntax: data DesignFile
- Language.VHDL.Syntax: data LogicalName
- Language.VHDL.Syntax: ds_guarded_signal_specification :: DisconnectionSpecification -> GuardedSignalSpecification
- Language.VHDL.Syntax: ds_time_expression :: DisconnectionSpecification -> Expression
- Language.VHDL.Syntax: eassoc_choices' :: ElementAssociation -> Maybe Choices
- Language.VHDL.Syntax: eassoc_expression :: ElementAssociation -> Expression
- Language.VHDL.Syntax: ed_entity_tag :: EntityDesignator -> EntityTag
- Language.VHDL.Syntax: ed_signature :: EntityDesignator -> Maybe Signature
- Language.VHDL.Syntax: elemd_identifier_list :: ElementDeclaration -> IdentifierList
- Language.VHDL.Syntax: elemd_subtype_definition :: ElementDeclaration -> ElementSubtypeDefinition
- Language.VHDL.Syntax: entc_entity_class :: EntityClassEntry -> EntityClass
- Language.VHDL.Syntax: entc_multiple :: EntityClassEntry -> Bool
- Language.VHDL.Syntax: entity_declarative_part :: EntityDeclaration -> EntityDeclarativePart
- Language.VHDL.Syntax: entity_header :: EntityDeclaration -> EntityHeader
- Language.VHDL.Syntax: entity_identifier :: EntityDeclaration -> Identifier
- Language.VHDL.Syntax: entity_statement_part :: EntityDeclaration -> Maybe EntityStatementPart
- Language.VHDL.Syntax: es_entity_class :: EntitySpecification -> EntityClass
- Language.VHDL.Syntax: es_entity_name_list :: EntitySpecification -> EntityNameList
- Language.VHDL.Syntax: exit_label :: ExitStatement -> Maybe Label
- Language.VHDL.Syntax: exit_loop :: ExitStatement -> Maybe Label
- Language.VHDL.Syntax: exit_when :: ExitStatement -> Maybe Condition
- Language.VHDL.Syntax: expression :: TypeConversion -> Expression
- Language.VHDL.Syntax: fc_actual_parameter_part :: FunctionCall -> Maybe ActualParameterPart
- Language.VHDL.Syntax: fc_function_name :: FunctionCall -> Name
- Language.VHDL.Syntax: fd_identifier_list :: FileDeclaration -> IdentifierList
- Language.VHDL.Syntax: fd_open_information :: FileDeclaration -> Maybe FileOpenInformation
- Language.VHDL.Syntax: fd_subtype_indication :: FileDeclaration -> SubtypeIndication
- Language.VHDL.Syntax: foi_logical_name :: FileOpenInformation -> FileLogicalName
- Language.VHDL.Syntax: foi_open_kind_expression :: FileOpenInformation -> Maybe Expression
- Language.VHDL.Syntax: formal_generic_clause :: EntityHeader -> Maybe GenericClause
- Language.VHDL.Syntax: formal_port_clause :: EntityHeader -> Maybe PortClause
- Language.VHDL.Syntax: ftd_identifier :: FullTypeDeclaration -> Identifier
- Language.VHDL.Syntax: ftd_type_definition :: FullTypeDeclaration -> TypeDefinition
- Language.VHDL.Syntax: gens_block_declarative_item :: GenerateStatement -> Maybe (BlockDeclarativeItem)
- Language.VHDL.Syntax: gens_concurrent_statement :: GenerateStatement -> [ConcurrentStatement]
- Language.VHDL.Syntax: gens_generation_scheme :: GenerateStatement -> GenerationScheme
- Language.VHDL.Syntax: gens_label :: GenerateStatement -> Label
- Language.VHDL.Syntax: group_constituent_list :: GroupDeclaration -> GroupConstituentList
- Language.VHDL.Syntax: group_identifier :: GroupDeclaration -> Identifier
- Language.VHDL.Syntax: group_template_name :: GroupDeclaration -> Name
- Language.VHDL.Syntax: gs_guarded_signal_list :: GuardedSignalSpecification -> SignalList
- Language.VHDL.Syntax: gs_type_mark :: GuardedSignalSpecification -> TypeMark
- Language.VHDL.Syntax: gtd_entity_class_entry_list :: GroupTemplateDeclaration -> EntityClassEntryList
- Language.VHDL.Syntax: gtd_identifier :: GroupTemplateDeclaration -> Identifier
- Language.VHDL.Syntax: iconst_static_expression :: InterfaceDeclaration -> Maybe Expression
- Language.VHDL.Syntax: iconst_subtype_indication :: InterfaceDeclaration -> SubtypeIndication
- Language.VHDL.Syntax: idecl_identifier_list :: InterfaceDeclaration -> IdentifierList
- Language.VHDL.Syntax: if_also :: IfStatement -> [(Condition, SequenceOfStatements)]
- Language.VHDL.Syntax: if_else :: IfStatement -> Maybe SequenceOfStatements
- Language.VHDL.Syntax: if_label :: IfStatement -> Maybe Label
- Language.VHDL.Syntax: if_then :: IfStatement -> (Condition, SequenceOfStatements)
- Language.VHDL.Syntax: ifile_subtype_indication :: InterfaceDeclaration -> SubtypeIndication
- Language.VHDL.Syntax: iname_expression :: IndexedName -> [Expression]
- Language.VHDL.Syntax: iname_prefix :: IndexedName -> Prefix
- Language.VHDL.Syntax: instance Eq AbstractLiteral
- Language.VHDL.Syntax: instance Eq AccessTypeDefinition
- Language.VHDL.Syntax: instance Eq ActualDesignator
- Language.VHDL.Syntax: instance Eq ActualPart
- Language.VHDL.Syntax: instance Eq AddingOperator
- Language.VHDL.Syntax: instance Eq Aggregate
- Language.VHDL.Syntax: instance Eq AliasDeclaration
- Language.VHDL.Syntax: instance Eq AliasDesignator
- Language.VHDL.Syntax: instance Eq Allocator
- Language.VHDL.Syntax: instance Eq ArchitectureBody
- Language.VHDL.Syntax: instance Eq ArrayTypeDefinition
- Language.VHDL.Syntax: instance Eq Assertion
- Language.VHDL.Syntax: instance Eq AssertionStatement
- Language.VHDL.Syntax: instance Eq AssociationElement
- Language.VHDL.Syntax: instance Eq AssociationList
- Language.VHDL.Syntax: instance Eq AttributeDeclaration
- Language.VHDL.Syntax: instance Eq AttributeName
- Language.VHDL.Syntax: instance Eq AttributeSpecification
- Language.VHDL.Syntax: instance Eq Base
- Language.VHDL.Syntax: instance Eq BaseSpecifier
- Language.VHDL.Syntax: instance Eq BaseUnitDeclaration
- Language.VHDL.Syntax: instance Eq BasedInteger
- Language.VHDL.Syntax: instance Eq BasedLiteral
- Language.VHDL.Syntax: instance Eq BasicCharacter
- Language.VHDL.Syntax: instance Eq BasicGraphicCharacter
- Language.VHDL.Syntax: instance Eq BasicIdentifier
- Language.VHDL.Syntax: instance Eq BindingIndication
- Language.VHDL.Syntax: instance Eq BitStringLiteral
- Language.VHDL.Syntax: instance Eq BitValue
- Language.VHDL.Syntax: instance Eq BlockConfiguration
- Language.VHDL.Syntax: instance Eq BlockDeclarativeItem
- Language.VHDL.Syntax: instance Eq BlockHeader
- Language.VHDL.Syntax: instance Eq BlockSpecification
- Language.VHDL.Syntax: instance Eq BlockStatement
- Language.VHDL.Syntax: instance Eq CaseStatement
- Language.VHDL.Syntax: instance Eq CaseStatementAlternative
- Language.VHDL.Syntax: instance Eq CharacterLiteral
- Language.VHDL.Syntax: instance Eq Choice
- Language.VHDL.Syntax: instance Eq Choices
- Language.VHDL.Syntax: instance Eq ComponentConfiguration
- Language.VHDL.Syntax: instance Eq ComponentDeclaration
- Language.VHDL.Syntax: instance Eq ComponentInstantiationStatement
- Language.VHDL.Syntax: instance Eq ComponentSpecification
- Language.VHDL.Syntax: instance Eq CompositeTypeDefinition
- Language.VHDL.Syntax: instance Eq ConcurrentAssertionStatement
- Language.VHDL.Syntax: instance Eq ConcurrentProcedureCallStatement
- Language.VHDL.Syntax: instance Eq ConcurrentSignalAssignmentStatement
- Language.VHDL.Syntax: instance Eq ConcurrentStatement
- Language.VHDL.Syntax: instance Eq ConditionClause
- Language.VHDL.Syntax: instance Eq ConditionalSignalAssignment
- Language.VHDL.Syntax: instance Eq ConditionalWaveforms
- Language.VHDL.Syntax: instance Eq ConfigurationDeclaration
- Language.VHDL.Syntax: instance Eq ConfigurationDeclarativeItem
- Language.VHDL.Syntax: instance Eq ConfigurationItem
- Language.VHDL.Syntax: instance Eq ConfigurationSpecification
- Language.VHDL.Syntax: instance Eq ConstantDeclaration
- Language.VHDL.Syntax: instance Eq ConstrainedArrayDefinition
- Language.VHDL.Syntax: instance Eq Constraint
- Language.VHDL.Syntax: instance Eq ContextClause
- Language.VHDL.Syntax: instance Eq ContextItem
- Language.VHDL.Syntax: instance Eq DecimalLiteral
- Language.VHDL.Syntax: instance Eq Declaration
- Language.VHDL.Syntax: instance Eq DelayMechanism
- Language.VHDL.Syntax: instance Eq DesignFile
- Language.VHDL.Syntax: instance Eq DesignUnit
- Language.VHDL.Syntax: instance Eq Designator
- Language.VHDL.Syntax: instance Eq Direction
- Language.VHDL.Syntax: instance Eq DisconnectionSpecification
- Language.VHDL.Syntax: instance Eq DiscreteRange
- Language.VHDL.Syntax: instance Eq ElementAssociation
- Language.VHDL.Syntax: instance Eq ElementDeclaration
- Language.VHDL.Syntax: instance Eq EntityAspect
- Language.VHDL.Syntax: instance Eq EntityClass
- Language.VHDL.Syntax: instance Eq EntityClassEntry
- Language.VHDL.Syntax: instance Eq EntityDeclaration
- Language.VHDL.Syntax: instance Eq EntityDeclarativeItem
- Language.VHDL.Syntax: instance Eq EntityDesignator
- Language.VHDL.Syntax: instance Eq EntityHeader
- Language.VHDL.Syntax: instance Eq EntityNameList
- Language.VHDL.Syntax: instance Eq EntitySpecification
- Language.VHDL.Syntax: instance Eq EntityStatement
- Language.VHDL.Syntax: instance Eq EntityTag
- Language.VHDL.Syntax: instance Eq EnumerationLiteral
- Language.VHDL.Syntax: instance Eq EnumerationTypeDefinition
- Language.VHDL.Syntax: instance Eq ExitStatement
- Language.VHDL.Syntax: instance Eq Exponent
- Language.VHDL.Syntax: instance Eq Expression
- Language.VHDL.Syntax: instance Eq ExtendedDigit
- Language.VHDL.Syntax: instance Eq ExtendedIdentifier
- Language.VHDL.Syntax: instance Eq Factor
- Language.VHDL.Syntax: instance Eq FileDeclaration
- Language.VHDL.Syntax: instance Eq FileOpenInformation
- Language.VHDL.Syntax: instance Eq FileTypeDefinition
- Language.VHDL.Syntax: instance Eq FormalDesignator
- Language.VHDL.Syntax: instance Eq FormalPart
- Language.VHDL.Syntax: instance Eq FullTypeDeclaration
- Language.VHDL.Syntax: instance Eq FunctionCall
- Language.VHDL.Syntax: instance Eq GenerateStatement
- Language.VHDL.Syntax: instance Eq GenerationScheme
- Language.VHDL.Syntax: instance Eq GenericClause
- Language.VHDL.Syntax: instance Eq GenericMapAspect
- Language.VHDL.Syntax: instance Eq GraphicCharacter
- Language.VHDL.Syntax: instance Eq GroupConstituent
- Language.VHDL.Syntax: instance Eq GroupDeclaration
- Language.VHDL.Syntax: instance Eq GroupTemplateDeclaration
- Language.VHDL.Syntax: instance Eq GuardedSignalSpecification
- Language.VHDL.Syntax: instance Eq Identifier
- Language.VHDL.Syntax: instance Eq IfStatement
- Language.VHDL.Syntax: instance Eq IncompleteTypeDeclaration
- Language.VHDL.Syntax: instance Eq IndexConstraint
- Language.VHDL.Syntax: instance Eq IndexSpecification
- Language.VHDL.Syntax: instance Eq IndexSubtypeDefinition
- Language.VHDL.Syntax: instance Eq IndexedName
- Language.VHDL.Syntax: instance Eq InstantiatedUnit
- Language.VHDL.Syntax: instance Eq InstantiationList
- Language.VHDL.Syntax: instance Eq InterfaceDeclaration
- Language.VHDL.Syntax: instance Eq InterfaceList
- Language.VHDL.Syntax: instance Eq IterationScheme
- Language.VHDL.Syntax: instance Eq Letter
- Language.VHDL.Syntax: instance Eq LetterOrDigit
- Language.VHDL.Syntax: instance Eq LibraryClause
- Language.VHDL.Syntax: instance Eq LibraryUnit
- Language.VHDL.Syntax: instance Eq Literal
- Language.VHDL.Syntax: instance Eq LogicalName
- Language.VHDL.Syntax: instance Eq LogicalNameList
- Language.VHDL.Syntax: instance Eq LogicalOperator
- Language.VHDL.Syntax: instance Eq LoopStatement
- Language.VHDL.Syntax: instance Eq MiscellaneousOperator
- Language.VHDL.Syntax: instance Eq Mode
- Language.VHDL.Syntax: instance Eq MultiplyingOperator
- Language.VHDL.Syntax: instance Eq Name
- Language.VHDL.Syntax: instance Eq NextStatement
- Language.VHDL.Syntax: instance Eq NullStatement
- Language.VHDL.Syntax: instance Eq NumericLiteral
- Language.VHDL.Syntax: instance Eq ObjectDeclaration
- Language.VHDL.Syntax: instance Eq Options
- Language.VHDL.Syntax: instance Eq PackageBody
- Language.VHDL.Syntax: instance Eq PackageBodyDeclarativeItem
- Language.VHDL.Syntax: instance Eq PackageDeclaration
- Language.VHDL.Syntax: instance Eq PackageDeclarativeItem
- Language.VHDL.Syntax: instance Eq ParameterSpecification
- Language.VHDL.Syntax: instance Eq PhysicalLiteral
- Language.VHDL.Syntax: instance Eq PhysicalTypeDefinition
- Language.VHDL.Syntax: instance Eq PortClause
- Language.VHDL.Syntax: instance Eq PortMapAspect
- Language.VHDL.Syntax: instance Eq Prefix
- Language.VHDL.Syntax: instance Eq Primary
- Language.VHDL.Syntax: instance Eq PrimaryUnit
- Language.VHDL.Syntax: instance Eq ProcedureCall
- Language.VHDL.Syntax: instance Eq ProcedureCallStatement
- Language.VHDL.Syntax: instance Eq ProcessDeclarativeItem
- Language.VHDL.Syntax: instance Eq ProcessStatement
- Language.VHDL.Syntax: instance Eq QualifiedExpression
- Language.VHDL.Syntax: instance Eq Range
- Language.VHDL.Syntax: instance Eq RangeConstraint
- Language.VHDL.Syntax: instance Eq RecordTypeDefinition
- Language.VHDL.Syntax: instance Eq Relation
- Language.VHDL.Syntax: instance Eq RelationalOperator
- Language.VHDL.Syntax: instance Eq ReportStatement
- Language.VHDL.Syntax: instance Eq ReturnStatement
- Language.VHDL.Syntax: instance Eq ScalarTypeDefinition
- Language.VHDL.Syntax: instance Eq SecondaryUnit
- Language.VHDL.Syntax: instance Eq SecondaryUnitDeclaration
- Language.VHDL.Syntax: instance Eq SelectedName
- Language.VHDL.Syntax: instance Eq SelectedSignalAssignment
- Language.VHDL.Syntax: instance Eq SelectedWaveforms
- Language.VHDL.Syntax: instance Eq SensitivityClause
- Language.VHDL.Syntax: instance Eq SensitivityList
- Language.VHDL.Syntax: instance Eq SequentialStatement
- Language.VHDL.Syntax: instance Eq ShiftExpression
- Language.VHDL.Syntax: instance Eq ShiftOperator
- Language.VHDL.Syntax: instance Eq Sign
- Language.VHDL.Syntax: instance Eq SignalAssignmentStatement
- Language.VHDL.Syntax: instance Eq SignalDeclaration
- Language.VHDL.Syntax: instance Eq SignalKind
- Language.VHDL.Syntax: instance Eq SignalList
- Language.VHDL.Syntax: instance Eq Signature
- Language.VHDL.Syntax: instance Eq SimpleExpression
- Language.VHDL.Syntax: instance Eq SliceName
- Language.VHDL.Syntax: instance Eq StringLiteral
- Language.VHDL.Syntax: instance Eq SubprogramBody
- Language.VHDL.Syntax: instance Eq SubprogramDeclarativeItem
- Language.VHDL.Syntax: instance Eq SubprogramKind
- Language.VHDL.Syntax: instance Eq SubprogramSpecification
- Language.VHDL.Syntax: instance Eq SubtypeDeclaration
- Language.VHDL.Syntax: instance Eq SubtypeIndication
- Language.VHDL.Syntax: instance Eq Suffix
- Language.VHDL.Syntax: instance Eq Target
- Language.VHDL.Syntax: instance Eq Term
- Language.VHDL.Syntax: instance Eq TimeoutClause
- Language.VHDL.Syntax: instance Eq TypeConversion
- Language.VHDL.Syntax: instance Eq TypeDeclaration
- Language.VHDL.Syntax: instance Eq TypeDefinition
- Language.VHDL.Syntax: instance Eq TypeMark
- Language.VHDL.Syntax: instance Eq UnconstrainedArrayDefinition
- Language.VHDL.Syntax: instance Eq UseClause
- Language.VHDL.Syntax: instance Eq VariableAssignmentStatement
- Language.VHDL.Syntax: instance Eq VariableDeclaration
- Language.VHDL.Syntax: instance Eq WaitStatement
- Language.VHDL.Syntax: instance Eq Waveform
- Language.VHDL.Syntax: instance Eq WaveformElement
- Language.VHDL.Syntax: instance Show AbstractLiteral
- Language.VHDL.Syntax: instance Show AccessTypeDefinition
- Language.VHDL.Syntax: instance Show ActualDesignator
- Language.VHDL.Syntax: instance Show ActualPart
- Language.VHDL.Syntax: instance Show AddingOperator
- Language.VHDL.Syntax: instance Show Aggregate
- Language.VHDL.Syntax: instance Show AliasDeclaration
- Language.VHDL.Syntax: instance Show AliasDesignator
- Language.VHDL.Syntax: instance Show Allocator
- Language.VHDL.Syntax: instance Show ArchitectureBody
- Language.VHDL.Syntax: instance Show ArrayTypeDefinition
- Language.VHDL.Syntax: instance Show Assertion
- Language.VHDL.Syntax: instance Show AssertionStatement
- Language.VHDL.Syntax: instance Show AssociationElement
- Language.VHDL.Syntax: instance Show AssociationList
- Language.VHDL.Syntax: instance Show AttributeDeclaration
- Language.VHDL.Syntax: instance Show AttributeName
- Language.VHDL.Syntax: instance Show AttributeSpecification
- Language.VHDL.Syntax: instance Show Base
- Language.VHDL.Syntax: instance Show BaseSpecifier
- Language.VHDL.Syntax: instance Show BaseUnitDeclaration
- Language.VHDL.Syntax: instance Show BasedInteger
- Language.VHDL.Syntax: instance Show BasedLiteral
- Language.VHDL.Syntax: instance Show BasicCharacter
- Language.VHDL.Syntax: instance Show BasicGraphicCharacter
- Language.VHDL.Syntax: instance Show BasicIdentifier
- Language.VHDL.Syntax: instance Show BindingIndication
- Language.VHDL.Syntax: instance Show BitStringLiteral
- Language.VHDL.Syntax: instance Show BitValue
- Language.VHDL.Syntax: instance Show BlockConfiguration
- Language.VHDL.Syntax: instance Show BlockDeclarativeItem
- Language.VHDL.Syntax: instance Show BlockHeader
- Language.VHDL.Syntax: instance Show BlockSpecification
- Language.VHDL.Syntax: instance Show BlockStatement
- Language.VHDL.Syntax: instance Show CaseStatement
- Language.VHDL.Syntax: instance Show CaseStatementAlternative
- Language.VHDL.Syntax: instance Show CharacterLiteral
- Language.VHDL.Syntax: instance Show Choice
- Language.VHDL.Syntax: instance Show Choices
- Language.VHDL.Syntax: instance Show ComponentConfiguration
- Language.VHDL.Syntax: instance Show ComponentDeclaration
- Language.VHDL.Syntax: instance Show ComponentInstantiationStatement
- Language.VHDL.Syntax: instance Show ComponentSpecification
- Language.VHDL.Syntax: instance Show CompositeTypeDefinition
- Language.VHDL.Syntax: instance Show ConcurrentAssertionStatement
- Language.VHDL.Syntax: instance Show ConcurrentProcedureCallStatement
- Language.VHDL.Syntax: instance Show ConcurrentSignalAssignmentStatement
- Language.VHDL.Syntax: instance Show ConcurrentStatement
- Language.VHDL.Syntax: instance Show ConditionClause
- Language.VHDL.Syntax: instance Show ConditionalSignalAssignment
- Language.VHDL.Syntax: instance Show ConditionalWaveforms
- Language.VHDL.Syntax: instance Show ConfigurationDeclaration
- Language.VHDL.Syntax: instance Show ConfigurationDeclarativeItem
- Language.VHDL.Syntax: instance Show ConfigurationItem
- Language.VHDL.Syntax: instance Show ConfigurationSpecification
- Language.VHDL.Syntax: instance Show ConstantDeclaration
- Language.VHDL.Syntax: instance Show ConstrainedArrayDefinition
- Language.VHDL.Syntax: instance Show Constraint
- Language.VHDL.Syntax: instance Show ContextClause
- Language.VHDL.Syntax: instance Show ContextItem
- Language.VHDL.Syntax: instance Show DecimalLiteral
- Language.VHDL.Syntax: instance Show Declaration
- Language.VHDL.Syntax: instance Show DelayMechanism
- Language.VHDL.Syntax: instance Show DesignFile
- Language.VHDL.Syntax: instance Show DesignUnit
- Language.VHDL.Syntax: instance Show Designator
- Language.VHDL.Syntax: instance Show Direction
- Language.VHDL.Syntax: instance Show DisconnectionSpecification
- Language.VHDL.Syntax: instance Show DiscreteRange
- Language.VHDL.Syntax: instance Show ElementAssociation
- Language.VHDL.Syntax: instance Show ElementDeclaration
- Language.VHDL.Syntax: instance Show EntityAspect
- Language.VHDL.Syntax: instance Show EntityClass
- Language.VHDL.Syntax: instance Show EntityClassEntry
- Language.VHDL.Syntax: instance Show EntityDeclaration
- Language.VHDL.Syntax: instance Show EntityDeclarativeItem
- Language.VHDL.Syntax: instance Show EntityDesignator
- Language.VHDL.Syntax: instance Show EntityHeader
- Language.VHDL.Syntax: instance Show EntityNameList
- Language.VHDL.Syntax: instance Show EntitySpecification
- Language.VHDL.Syntax: instance Show EntityStatement
- Language.VHDL.Syntax: instance Show EntityTag
- Language.VHDL.Syntax: instance Show EnumerationLiteral
- Language.VHDL.Syntax: instance Show EnumerationTypeDefinition
- Language.VHDL.Syntax: instance Show ExitStatement
- Language.VHDL.Syntax: instance Show Exponent
- Language.VHDL.Syntax: instance Show Expression
- Language.VHDL.Syntax: instance Show ExtendedDigit
- Language.VHDL.Syntax: instance Show ExtendedIdentifier
- Language.VHDL.Syntax: instance Show Factor
- Language.VHDL.Syntax: instance Show FileDeclaration
- Language.VHDL.Syntax: instance Show FileOpenInformation
- Language.VHDL.Syntax: instance Show FileTypeDefinition
- Language.VHDL.Syntax: instance Show FormalDesignator
- Language.VHDL.Syntax: instance Show FormalPart
- Language.VHDL.Syntax: instance Show FullTypeDeclaration
- Language.VHDL.Syntax: instance Show FunctionCall
- Language.VHDL.Syntax: instance Show GenerateStatement
- Language.VHDL.Syntax: instance Show GenerationScheme
- Language.VHDL.Syntax: instance Show GenericClause
- Language.VHDL.Syntax: instance Show GenericMapAspect
- Language.VHDL.Syntax: instance Show GraphicCharacter
- Language.VHDL.Syntax: instance Show GroupConstituent
- Language.VHDL.Syntax: instance Show GroupDeclaration
- Language.VHDL.Syntax: instance Show GroupTemplateDeclaration
- Language.VHDL.Syntax: instance Show GuardedSignalSpecification
- Language.VHDL.Syntax: instance Show Identifier
- Language.VHDL.Syntax: instance Show IfStatement
- Language.VHDL.Syntax: instance Show IncompleteTypeDeclaration
- Language.VHDL.Syntax: instance Show IndexConstraint
- Language.VHDL.Syntax: instance Show IndexSpecification
- Language.VHDL.Syntax: instance Show IndexSubtypeDefinition
- Language.VHDL.Syntax: instance Show IndexedName
- Language.VHDL.Syntax: instance Show InstantiatedUnit
- Language.VHDL.Syntax: instance Show InstantiationList
- Language.VHDL.Syntax: instance Show InterfaceDeclaration
- Language.VHDL.Syntax: instance Show InterfaceList
- Language.VHDL.Syntax: instance Show IterationScheme
- Language.VHDL.Syntax: instance Show Letter
- Language.VHDL.Syntax: instance Show LetterOrDigit
- Language.VHDL.Syntax: instance Show LibraryClause
- Language.VHDL.Syntax: instance Show LibraryUnit
- Language.VHDL.Syntax: instance Show Literal
- Language.VHDL.Syntax: instance Show LogicalName
- Language.VHDL.Syntax: instance Show LogicalNameList
- Language.VHDL.Syntax: instance Show LogicalOperator
- Language.VHDL.Syntax: instance Show LoopStatement
- Language.VHDL.Syntax: instance Show MiscellaneousOperator
- Language.VHDL.Syntax: instance Show Mode
- Language.VHDL.Syntax: instance Show MultiplyingOperator
- Language.VHDL.Syntax: instance Show Name
- Language.VHDL.Syntax: instance Show NextStatement
- Language.VHDL.Syntax: instance Show NullStatement
- Language.VHDL.Syntax: instance Show NumericLiteral
- Language.VHDL.Syntax: instance Show ObjectDeclaration
- Language.VHDL.Syntax: instance Show Options
- Language.VHDL.Syntax: instance Show PackageBody
- Language.VHDL.Syntax: instance Show PackageBodyDeclarativeItem
- Language.VHDL.Syntax: instance Show PackageDeclaration
- Language.VHDL.Syntax: instance Show PackageDeclarativeItem
- Language.VHDL.Syntax: instance Show ParameterSpecification
- Language.VHDL.Syntax: instance Show PhysicalLiteral
- Language.VHDL.Syntax: instance Show PhysicalTypeDefinition
- Language.VHDL.Syntax: instance Show PortClause
- Language.VHDL.Syntax: instance Show PortMapAspect
- Language.VHDL.Syntax: instance Show Prefix
- Language.VHDL.Syntax: instance Show Primary
- Language.VHDL.Syntax: instance Show PrimaryUnit
- Language.VHDL.Syntax: instance Show ProcedureCall
- Language.VHDL.Syntax: instance Show ProcedureCallStatement
- Language.VHDL.Syntax: instance Show ProcessDeclarativeItem
- Language.VHDL.Syntax: instance Show ProcessStatement
- Language.VHDL.Syntax: instance Show QualifiedExpression
- Language.VHDL.Syntax: instance Show Range
- Language.VHDL.Syntax: instance Show RangeConstraint
- Language.VHDL.Syntax: instance Show RecordTypeDefinition
- Language.VHDL.Syntax: instance Show Relation
- Language.VHDL.Syntax: instance Show RelationalOperator
- Language.VHDL.Syntax: instance Show ReportStatement
- Language.VHDL.Syntax: instance Show ReturnStatement
- Language.VHDL.Syntax: instance Show ScalarTypeDefinition
- Language.VHDL.Syntax: instance Show SecondaryUnit
- Language.VHDL.Syntax: instance Show SecondaryUnitDeclaration
- Language.VHDL.Syntax: instance Show SelectedName
- Language.VHDL.Syntax: instance Show SelectedSignalAssignment
- Language.VHDL.Syntax: instance Show SelectedWaveforms
- Language.VHDL.Syntax: instance Show SensitivityClause
- Language.VHDL.Syntax: instance Show SensitivityList
- Language.VHDL.Syntax: instance Show SequentialStatement
- Language.VHDL.Syntax: instance Show ShiftExpression
- Language.VHDL.Syntax: instance Show ShiftOperator
- Language.VHDL.Syntax: instance Show Sign
- Language.VHDL.Syntax: instance Show SignalAssignmentStatement
- Language.VHDL.Syntax: instance Show SignalDeclaration
- Language.VHDL.Syntax: instance Show SignalKind
- Language.VHDL.Syntax: instance Show SignalList
- Language.VHDL.Syntax: instance Show Signature
- Language.VHDL.Syntax: instance Show SimpleExpression
- Language.VHDL.Syntax: instance Show SliceName
- Language.VHDL.Syntax: instance Show StringLiteral
- Language.VHDL.Syntax: instance Show SubprogramBody
- Language.VHDL.Syntax: instance Show SubprogramDeclarativeItem
- Language.VHDL.Syntax: instance Show SubprogramKind
- Language.VHDL.Syntax: instance Show SubprogramSpecification
- Language.VHDL.Syntax: instance Show SubtypeDeclaration
- Language.VHDL.Syntax: instance Show SubtypeIndication
- Language.VHDL.Syntax: instance Show Suffix
- Language.VHDL.Syntax: instance Show Target
- Language.VHDL.Syntax: instance Show Term
- Language.VHDL.Syntax: instance Show TimeoutClause
- Language.VHDL.Syntax: instance Show TypeConversion
- Language.VHDL.Syntax: instance Show TypeDeclaration
- Language.VHDL.Syntax: instance Show TypeDefinition
- Language.VHDL.Syntax: instance Show TypeMark
- Language.VHDL.Syntax: instance Show UnconstrainedArrayDefinition
- Language.VHDL.Syntax: instance Show UseClause
- Language.VHDL.Syntax: instance Show VariableAssignmentStatement
- Language.VHDL.Syntax: instance Show VariableDeclaration
- Language.VHDL.Syntax: instance Show WaitStatement
- Language.VHDL.Syntax: instance Show Waveform
- Language.VHDL.Syntax: instance Show WaveformElement
- Language.VHDL.Syntax: isig_bus :: InterfaceDeclaration -> Bool
- Language.VHDL.Syntax: isig_mode :: InterfaceDeclaration -> Maybe Mode
- Language.VHDL.Syntax: isig_static_expression :: InterfaceDeclaration -> Maybe Expression
- Language.VHDL.Syntax: isig_subtype_indication :: InterfaceDeclaration -> SubtypeIndication
- Language.VHDL.Syntax: ivar_mode :: InterfaceDeclaration -> Maybe Mode
- Language.VHDL.Syntax: ivar_static_expression :: InterfaceDeclaration -> Maybe Expression
- Language.VHDL.Syntax: ivar_subtype_indication :: InterfaceDeclaration -> SubtypeIndication
- Language.VHDL.Syntax: loop_iteration_scheme :: LoopStatement -> Maybe IterationScheme
- Language.VHDL.Syntax: loop_label :: LoopStatement -> Maybe Label
- Language.VHDL.Syntax: loop_statements :: LoopStatement -> SequenceOfStatements
- Language.VHDL.Syntax: next_label :: NextStatement -> Maybe Label
- Language.VHDL.Syntax: next_loop :: NextStatement -> Maybe Label
- Language.VHDL.Syntax: next_when :: NextStatement -> Maybe Condition
- Language.VHDL.Syntax: null_label :: NullStatement -> Maybe Label
- Language.VHDL.Syntax: options_delay_mechanism :: Options -> Maybe DelayMechanism
- Language.VHDL.Syntax: options_guarded :: Options -> Bool
- Language.VHDL.Syntax: packb_body_declarative_part :: PackageBody -> PackageBodyDeclarativePart
- Language.VHDL.Syntax: packb_simple_name :: PackageBody -> SimpleName
- Language.VHDL.Syntax: packd_declarative_part :: PackageDeclaration -> PackageDeclarativePart
- Language.VHDL.Syntax: packd_identifier :: PackageDeclaration -> Identifier
- Language.VHDL.Syntax: paramspec_discrete_range :: ParameterSpecification -> DiscreteRange
- Language.VHDL.Syntax: paramspec_identifier :: ParameterSpecification -> Identifier
- Language.VHDL.Syntax: physd_primary_unit_declaration :: PhysicalTypeDefinition -> PrimaryUnitDeclaration
- Language.VHDL.Syntax: physd_range_constraint :: PhysicalTypeDefinition -> RangeConstraint
- Language.VHDL.Syntax: physd_secondary_unit_declaration :: PhysicalTypeDefinition -> [SecondaryUnitDeclaration]
- Language.VHDL.Syntax: physd_simple_name :: PhysicalTypeDefinition -> Maybe SimpleName
- Language.VHDL.Syntax: physl_abstract_literal :: PhysicalLiteral -> Maybe Literal
- Language.VHDL.Syntax: physl_unit_name :: PhysicalLiteral -> Name
- Language.VHDL.Syntax: procs_declarative_part :: ProcessStatement -> ProcessDeclarativePart
- Language.VHDL.Syntax: procs_label :: ProcessStatement -> Maybe Label
- Language.VHDL.Syntax: procs_postponed :: ProcessStatement -> Bool
- Language.VHDL.Syntax: procs_sensitivity_list :: ProcessStatement -> Maybe SensitivityList
- Language.VHDL.Syntax: procs_statement_part :: ProcessStatement -> ProcessStatementPart
- Language.VHDL.Syntax: range_dir :: Range -> Direction
- Language.VHDL.Syntax: range_lower :: Range -> SimpleExpression
- Language.VHDL.Syntax: range_upper :: Range -> SimpleExpression
- Language.VHDL.Syntax: rectd_element_declaration :: RecordTypeDefinition -> [ElementDeclaration]
- Language.VHDL.Syntax: rectd_type_simple_name :: RecordTypeDefinition -> Maybe SimpleName
- Language.VHDL.Syntax: relation_operator :: Relation -> Maybe (RelationalOperator, ShiftExpression)
- Language.VHDL.Syntax: relation_shift_expression :: Relation -> ShiftExpression
- Language.VHDL.Syntax: return_expression :: ReturnStatement -> Maybe Expression
- Language.VHDL.Syntax: return_label :: ReturnStatement -> Maybe Label
- Language.VHDL.Syntax: sd_identifier :: SubtypeDeclaration -> Identifier
- Language.VHDL.Syntax: sd_indication :: SubtypeDeclaration -> SubtypeIndication
- Language.VHDL.Syntax: sexp_adding :: SimpleExpression -> [(AddingOperator, Term)]
- Language.VHDL.Syntax: sexp_sign :: SimpleExpression -> Maybe Sign
- Language.VHDL.Syntax: sexp_term :: SimpleExpression -> Term
- Language.VHDL.Syntax: shifte_shift_operator :: ShiftExpression -> Maybe (ShiftOperator, SimpleExpression)
- Language.VHDL.Syntax: shifte_simple_expression :: ShiftExpression -> SimpleExpression
- Language.VHDL.Syntax: si_constraint :: SubtypeIndication -> Maybe Constraint
- Language.VHDL.Syntax: si_resolution_function_name :: SubtypeIndication -> Maybe Name
- Language.VHDL.Syntax: si_type_mark :: SubtypeIndication -> TypeMark
- Language.VHDL.Syntax: signal_expression :: SignalDeclaration -> Maybe Expression
- Language.VHDL.Syntax: signal_identifier_list :: SignalDeclaration -> IdentifierList
- Language.VHDL.Syntax: signal_kind :: SignalDeclaration -> Maybe SignalKind
- Language.VHDL.Syntax: signal_subtype_indication :: SignalDeclaration -> SubtypeIndication
- Language.VHDL.Syntax: slice_discrete_range :: SliceName -> DiscreteRange
- Language.VHDL.Syntax: slice_prefix :: SliceName -> Prefix
- Language.VHDL.Syntax: sname_prefix :: SelectedName -> Prefix
- Language.VHDL.Syntax: sname_suffix :: SelectedName -> Suffix
- Language.VHDL.Syntax: ssa_expression :: SelectedSignalAssignment -> Expression
- Language.VHDL.Syntax: ssa_options :: SelectedSignalAssignment -> Options
- Language.VHDL.Syntax: ssa_selected_waveforms :: SelectedSignalAssignment -> SelectedWaveforms
- Language.VHDL.Syntax: ssa_target :: SelectedSignalAssignment -> Target
- Language.VHDL.Syntax: subfun_designator :: SubprogramSpecification -> Designator
- Language.VHDL.Syntax: subfun_formal_parameter_list :: SubprogramSpecification -> Maybe FormalParameterList
- Language.VHDL.Syntax: subfun_purity :: SubprogramSpecification -> Maybe Bool
- Language.VHDL.Syntax: subfun_type_mark :: SubprogramSpecification -> TypeMark
- Language.VHDL.Syntax: subproc_designator :: SubprogramSpecification -> Designator
- Language.VHDL.Syntax: subproc_formal_parameter_list :: SubprogramSpecification -> Maybe FormalParameterList
- Language.VHDL.Syntax: subprog_declarative_part :: SubprogramBody -> SubprogramDeclarativePart
- Language.VHDL.Syntax: subprog_designator :: SubprogramBody -> Maybe Designator
- Language.VHDL.Syntax: subprog_kind :: SubprogramBody -> Maybe SubprogramKind
- Language.VHDL.Syntax: subprog_specification :: SubprogramBody -> SubprogramSpecification
- Language.VHDL.Syntax: subprog_statement_part :: SubprogramBody -> SubprogramStatementPart
- Language.VHDL.Syntax: sw_last :: SelectedWaveforms -> (Waveform, Choices)
- Language.VHDL.Syntax: sw_optional :: SelectedWaveforms -> Maybe [(Waveform, Choices)]
- Language.VHDL.Syntax: term_factor :: Term -> Factor
- Language.VHDL.Syntax: term_multiplying :: Term -> [(MultiplyingOperator, Factor)]
- Language.VHDL.Syntax: type_mark :: TypeConversion -> TypeMark
- Language.VHDL.Syntax: var_expression :: VariableDeclaration -> Maybe Expression
- Language.VHDL.Syntax: var_identifier_list :: VariableDeclaration -> IdentifierList
- Language.VHDL.Syntax: var_shared :: VariableDeclaration -> Bool
- Language.VHDL.Syntax: var_subtype_indication :: VariableDeclaration -> SubtypeIndication
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty GHC.Integer.Type.Integer
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AbstractLiteral
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AccessTypeDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ActualDesignator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ActualPart
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AddingOperator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Aggregate
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AliasDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AliasDesignator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Allocator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ArchitectureBody
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ArrayTypeDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Assertion
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AssertionStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AssociationElement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AssociationList
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AttributeDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AttributeName
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.AttributeSpecification
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Base
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BaseSpecifier
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BaseUnitDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BasedInteger
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BasedLiteral
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BasicCharacter
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BasicGraphicCharacter
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BasicIdentifier
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BindingIndication
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BitStringLiteral
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BitValue
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BlockConfiguration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BlockDeclarativeItem
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BlockHeader
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BlockSpecification
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.BlockStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.CaseStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.CaseStatementAlternative
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.CharacterLiteral
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Choice
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Choices
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ComponentConfiguration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ComponentDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ComponentInstantiationStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ComponentSpecification
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.CompositeTypeDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConcurrentAssertionStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConcurrentProcedureCallStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConcurrentSignalAssignmentStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConcurrentStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConditionClause
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConditionalSignalAssignment
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConditionalWaveforms
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConfigurationDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConfigurationDeclarativeItem
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConfigurationItem
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConfigurationSpecification
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConstantDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ConstrainedArrayDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Constraint
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ContextItem
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.DecimalLiteral
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Declaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.DelayMechanism
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.DesignUnit
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Designator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Direction
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.DisconnectionSpecification
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.DiscreteRange
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ElementAssociation
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ElementDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntityAspect
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntityClass
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntityClassEntry
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntityDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntityDeclarativeItem
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntityDesignator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntityHeader
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntityNameList
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntitySpecification
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntityStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EntityTag
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EnumerationLiteral
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.EnumerationTypeDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ExitStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Exponent
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Expression
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ExtendedDigit
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ExtendedIdentifier
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Factor
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.FileDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.FileOpenInformation
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.FileTypeDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.FormalDesignator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.FormalPart
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.FullTypeDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.FunctionCall
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.GenerateStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.GenerationScheme
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.GenericClause
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.GenericMapAspect
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.GraphicCharacter
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.GroupConstituent
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.GroupDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.GroupTemplateDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.GuardedSignalSpecification
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Identifier
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.IfStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.IncompleteTypeDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.IndexConstraint
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.IndexSpecification
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.IndexSubtypeDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.IndexedName
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.InstantiatedUnit
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.InstantiationList
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.InterfaceDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.InterfaceList
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.IterationScheme
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Letter
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.LetterOrDigit
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.LibraryClause
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.LibraryUnit
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Literal
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.LogicalNameList
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.LogicalOperator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.LoopStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.MiscellaneousOperator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Mode
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.MultiplyingOperator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Name
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.NextStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.NullStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.NumericLiteral
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ObjectDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Options
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.PackageBody
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.PackageBodyDeclarativeItem
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.PackageDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.PackageDeclarativeItem
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ParameterSpecification
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.PhysicalLiteral
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.PhysicalTypeDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.PortClause
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.PortMapAspect
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Prefix
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Primary
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.PrimaryUnit
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ProcedureCall
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ProcedureCallStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ProcessDeclarativeItem
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ProcessStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.QualifiedExpression
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Range
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.RangeConstraint
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.RecordTypeDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Relation
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.RelationalOperator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ReportStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ReturnStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ScalarTypeDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SecondaryUnit
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SecondaryUnitDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SelectedName
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SelectedSignalAssignment
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SelectedWaveforms
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SensitivityClause
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SensitivityList
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SequentialStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ShiftExpression
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.ShiftOperator
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Sign
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SignalAssignmentStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SignalDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SignalKind
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SignalList
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Signature
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SimpleExpression
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SliceName
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.StringLiteral
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SubprogramBody
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SubprogramDeclarativeItem
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SubprogramKind
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SubprogramSpecification
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SubtypeDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.SubtypeIndication
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Suffix
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Target
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Term
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.TimeoutClause
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.TypeConversion
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.TypeDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.TypeDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.TypeMark
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.UnconstrainedArrayDefinition
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.UseClause
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.VariableAssignmentStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.VariableDeclaration
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.WaitStatement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.Waveform
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty Language.VHDL.Syntax.WaveformElement
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty a => Language.VHDL.Pretty.Pretty (GHC.Base.Maybe a)
+ Language.VHDL.Pretty: instance Language.VHDL.Pretty.Pretty a => Language.VHDL.Pretty.Pretty [a]
+ Language.VHDL.Syntax: ContextLibrary :: LibraryClause -> ContextItem
+ Language.VHDL.Syntax: ContextUse :: UseClause -> ContextItem
+ Language.VHDL.Syntax: PrimaryConfig :: ConfigurationDeclaration -> PrimaryUnit
+ Language.VHDL.Syntax: PrimaryEntity :: EntityDeclaration -> PrimaryUnit
+ Language.VHDL.Syntax: PrimaryPackage :: PackageDeclaration -> PrimaryUnit
+ Language.VHDL.Syntax: SecondaryArchitecture :: ArchitectureBody -> SecondaryUnit
+ Language.VHDL.Syntax: SecondaryPackage :: PackageBody -> SecondaryUnit
+ Language.VHDL.Syntax: [agg_element_association] :: Aggregate -> [ElementAssociation]
+ Language.VHDL.Syntax: [alias_designator] :: AliasDeclaration -> AliasDesignator
+ Language.VHDL.Syntax: [alias_name] :: AliasDeclaration -> Name
+ Language.VHDL.Syntax: [alias_signature] :: AliasDeclaration -> Maybe Signature
+ Language.VHDL.Syntax: [alias_subtype_indication] :: AliasDeclaration -> Maybe SubtypeIndication
+ Language.VHDL.Syntax: [aname_attribute_designator] :: AttributeName -> AttributeDesignator
+ Language.VHDL.Syntax: [aname_expression] :: AttributeName -> Maybe Expression
+ Language.VHDL.Syntax: [aname_prefix] :: AttributeName -> Prefix
+ Language.VHDL.Syntax: [aname_signature] :: AttributeName -> Maybe Signature
+ Language.VHDL.Syntax: [archi_declarative_part] :: ArchitectureBody -> ArchitectureDeclarativePart
+ Language.VHDL.Syntax: [archi_entity_name] :: ArchitectureBody -> Name
+ Language.VHDL.Syntax: [archi_identifier] :: ArchitectureBody -> Identifier
+ Language.VHDL.Syntax: [archi_statement_part] :: ArchitectureBody -> ArchitectureStatementPart
+ Language.VHDL.Syntax: [arrc_index_constraint] :: ConstrainedArrayDefinition -> IndexConstraint
+ Language.VHDL.Syntax: [arrc_subtype_indication] :: ConstrainedArrayDefinition -> SubtypeIndication
+ Language.VHDL.Syntax: [arru_element_subtype_indication] :: UnconstrainedArrayDefinition -> (SubtypeIndication)
+ Language.VHDL.Syntax: [arru_index_subtype_definition] :: UnconstrainedArrayDefinition -> [IndexSubtypeDefinition]
+ Language.VHDL.Syntax: [as_attribute_designator] :: AttributeSpecification -> AttributeDesignator
+ Language.VHDL.Syntax: [as_entity_specification] :: AttributeSpecification -> EntitySpecification
+ Language.VHDL.Syntax: [as_expression] :: AttributeSpecification -> Expression
+ Language.VHDL.Syntax: [assoc_actual_part] :: AssociationElement -> ActualPart
+ Language.VHDL.Syntax: [assoc_formal_part] :: AssociationElement -> Maybe FormalPart
+ Language.VHDL.Syntax: [attr_identifier] :: AttributeDeclaration -> Identifier
+ Language.VHDL.Syntax: [attr_type_marke] :: AttributeDeclaration -> TypeMark
+ Language.VHDL.Syntax: [bi_entity_aspect] :: BindingIndication -> Maybe EntityAspect
+ Language.VHDL.Syntax: [bi_generic_map_aspect] :: BindingIndication -> Maybe GenericMapAspect
+ Language.VHDL.Syntax: [bi_port_map_aspect] :: BindingIndication -> Maybe PortMapAspect
+ Language.VHDL.Syntax: [block_configuration_item] :: BlockConfiguration -> [ConfigurationItem]
+ Language.VHDL.Syntax: [block_specification] :: BlockConfiguration -> BlockSpecification
+ Language.VHDL.Syntax: [block_use_clause] :: BlockConfiguration -> [UseClause]
+ Language.VHDL.Syntax: [blockh_generic_clause] :: BlockHeader -> Maybe (GenericClause, Maybe GenericMapAspect)
+ Language.VHDL.Syntax: [blockh_port_clause] :: BlockHeader -> Maybe (PortClause, Maybe PortMapAspect)
+ Language.VHDL.Syntax: [blocks_declarative_part] :: BlockStatement -> BlockDeclarativePart
+ Language.VHDL.Syntax: [blocks_guard_expression] :: BlockStatement -> Maybe Expression
+ Language.VHDL.Syntax: [blocks_header] :: BlockStatement -> BlockHeader
+ Language.VHDL.Syntax: [blocks_label] :: BlockStatement -> Label
+ Language.VHDL.Syntax: [blocks_statment_part] :: BlockStatement -> BlockStatementPart
+ Language.VHDL.Syntax: [cas_assertion] :: ConcurrentAssertionStatement -> Assertion
+ Language.VHDL.Syntax: [cas_label] :: ConcurrentAssertionStatement -> Maybe Label
+ Language.VHDL.Syntax: [cas_postponed] :: ConcurrentAssertionStatement -> Bool
+ Language.VHDL.Syntax: [case_alternatives] :: CaseStatement -> [CaseStatementAlternative]
+ Language.VHDL.Syntax: [case_expression] :: CaseStatement -> Expression
+ Language.VHDL.Syntax: [case_label] :: CaseStatement -> Maybe Label
+ Language.VHDL.Syntax: [cis_generic_map_aspect] :: ComponentInstantiationStatement -> Maybe GenericMapAspect
+ Language.VHDL.Syntax: [cis_instantiated_unit] :: ComponentInstantiationStatement -> InstantiatedUnit
+ Language.VHDL.Syntax: [cis_instantiation_label] :: ComponentInstantiationStatement -> Label
+ Language.VHDL.Syntax: [cis_port_map_aspect] :: ComponentInstantiationStatement -> Maybe PortMapAspect
+ Language.VHDL.Syntax: [comp_binding_indication] :: ComponentConfiguration -> Maybe BindingIndication
+ Language.VHDL.Syntax: [comp_block_configuration] :: ComponentConfiguration -> Maybe BlockConfiguration
+ Language.VHDL.Syntax: [comp_identifier] :: ComponentDeclaration -> Identifier
+ Language.VHDL.Syntax: [comp_local_generic_clause] :: ComponentDeclaration -> Maybe GenericClause
+ Language.VHDL.Syntax: [comp_local_port_clause] :: ComponentDeclaration -> Maybe PortClause
+ Language.VHDL.Syntax: [comp_simple_name] :: ComponentDeclaration -> Maybe SimpleName
+ Language.VHDL.Syntax: [comp_specification] :: ComponentConfiguration -> ComponentSpecification
+ Language.VHDL.Syntax: [config_block_configuration] :: ConfigurationDeclaration -> BlockConfiguration
+ Language.VHDL.Syntax: [config_declarative_part] :: ConfigurationDeclaration -> ConfigurationDeclarativePart
+ Language.VHDL.Syntax: [config_entity_name] :: ConfigurationDeclaration -> Name
+ Language.VHDL.Syntax: [config_identifier] :: ConfigurationDeclaration -> Identifier
+ Language.VHDL.Syntax: [const_expression] :: ConstantDeclaration -> Maybe Expression
+ Language.VHDL.Syntax: [const_identifier_list] :: ConstantDeclaration -> IdentifierList
+ Language.VHDL.Syntax: [const_subtype_indication] :: ConstantDeclaration -> SubtypeIndication
+ Language.VHDL.Syntax: [cpcs_label] :: ConcurrentProcedureCallStatement -> Maybe Label
+ Language.VHDL.Syntax: [cpcs_postponed] :: ConcurrentProcedureCallStatement -> Bool
+ Language.VHDL.Syntax: [cpcs_procedure_call] :: ConcurrentProcedureCallStatement -> ProcedureCall
+ Language.VHDL.Syntax: [cs_binding_indication] :: ConfigurationSpecification -> BindingIndication
+ Language.VHDL.Syntax: [cs_component_name] :: ComponentSpecification -> Name
+ Language.VHDL.Syntax: [cs_component_specification] :: ConfigurationSpecification -> ComponentSpecification
+ Language.VHDL.Syntax: [cs_instantiation_list] :: ComponentSpecification -> InstantiationList
+ Language.VHDL.Syntax: [csa_conditional_waveforms] :: ConditionalSignalAssignment -> ConditionalWaveforms
+ Language.VHDL.Syntax: [csa_options] :: ConditionalSignalAssignment -> Options
+ Language.VHDL.Syntax: [csa_target] :: ConditionalSignalAssignment -> Target
+ Language.VHDL.Syntax: [csas_cond_label] :: ConcurrentSignalAssignmentStatement -> Maybe Label
+ Language.VHDL.Syntax: [csas_cond_postponed] :: ConcurrentSignalAssignmentStatement -> Bool
+ Language.VHDL.Syntax: [csas_cond_signal_assignment] :: ConcurrentSignalAssignmentStatement -> ConditionalSignalAssignment
+ Language.VHDL.Syntax: [csas_select_label] :: ConcurrentSignalAssignmentStatement -> Maybe Label
+ Language.VHDL.Syntax: [csas_select_postponed] :: ConcurrentSignalAssignmentStatement -> Bool
+ Language.VHDL.Syntax: [csas_select_signal_assignment] :: ConcurrentSignalAssignmentStatement -> SelectedSignalAssignment
+ Language.VHDL.Syntax: [cw_optional] :: ConditionalWaveforms -> [(Waveform, Condition)]
+ Language.VHDL.Syntax: [cw_wave] :: ConditionalWaveforms -> (Waveform, Maybe Condition)
+ Language.VHDL.Syntax: [design_primary_unit] :: DesignUnit -> PrimaryUnit
+ Language.VHDL.Syntax: [design_secondary_unit] :: DesignUnit -> SecondaryUnit
+ Language.VHDL.Syntax: [ds_guarded_signal_specification] :: DisconnectionSpecification -> GuardedSignalSpecification
+ Language.VHDL.Syntax: [ds_time_expression] :: DisconnectionSpecification -> Expression
+ Language.VHDL.Syntax: [eassoc_choices'] :: ElementAssociation -> Maybe Choices
+ Language.VHDL.Syntax: [eassoc_expression] :: ElementAssociation -> Expression
+ Language.VHDL.Syntax: [ed_entity_tag] :: EntityDesignator -> EntityTag
+ Language.VHDL.Syntax: [ed_signature] :: EntityDesignator -> Maybe Signature
+ Language.VHDL.Syntax: [elemd_identifier_list] :: ElementDeclaration -> IdentifierList
+ Language.VHDL.Syntax: [elemd_subtype_definition] :: ElementDeclaration -> ElementSubtypeDefinition
+ Language.VHDL.Syntax: [entc_entity_class] :: EntityClassEntry -> EntityClass
+ Language.VHDL.Syntax: [entc_multiple] :: EntityClassEntry -> Bool
+ Language.VHDL.Syntax: [entity_declarative_part] :: EntityDeclaration -> EntityDeclarativePart
+ Language.VHDL.Syntax: [entity_header] :: EntityDeclaration -> EntityHeader
+ Language.VHDL.Syntax: [entity_identifier] :: EntityDeclaration -> Identifier
+ Language.VHDL.Syntax: [entity_statement_part] :: EntityDeclaration -> Maybe EntityStatementPart
+ Language.VHDL.Syntax: [es_entity_class] :: EntitySpecification -> EntityClass
+ Language.VHDL.Syntax: [es_entity_name_list] :: EntitySpecification -> EntityNameList
+ Language.VHDL.Syntax: [exit_label] :: ExitStatement -> Maybe Label
+ Language.VHDL.Syntax: [exit_loop] :: ExitStatement -> Maybe Label
+ Language.VHDL.Syntax: [exit_when] :: ExitStatement -> Maybe Condition
+ Language.VHDL.Syntax: [expression] :: TypeConversion -> Expression
+ Language.VHDL.Syntax: [fc_actual_parameter_part] :: FunctionCall -> Maybe ActualParameterPart
+ Language.VHDL.Syntax: [fc_function_name] :: FunctionCall -> Name
+ Language.VHDL.Syntax: [fd_identifier_list] :: FileDeclaration -> IdentifierList
+ Language.VHDL.Syntax: [fd_open_information] :: FileDeclaration -> Maybe FileOpenInformation
+ Language.VHDL.Syntax: [fd_subtype_indication] :: FileDeclaration -> SubtypeIndication
+ Language.VHDL.Syntax: [foi_logical_name] :: FileOpenInformation -> FileLogicalName
+ Language.VHDL.Syntax: [foi_open_kind_expression] :: FileOpenInformation -> Maybe Expression
+ Language.VHDL.Syntax: [formal_generic_clause] :: EntityHeader -> Maybe GenericClause
+ Language.VHDL.Syntax: [formal_port_clause] :: EntityHeader -> Maybe PortClause
+ Language.VHDL.Syntax: [ftd_identifier] :: FullTypeDeclaration -> Identifier
+ Language.VHDL.Syntax: [ftd_type_definition] :: FullTypeDeclaration -> TypeDefinition
+ Language.VHDL.Syntax: [gens_block_declarative_item] :: GenerateStatement -> Maybe (BlockDeclarativeItem)
+ Language.VHDL.Syntax: [gens_concurrent_statement] :: GenerateStatement -> [ConcurrentStatement]
+ Language.VHDL.Syntax: [gens_generation_scheme] :: GenerateStatement -> GenerationScheme
+ Language.VHDL.Syntax: [gens_label] :: GenerateStatement -> Label
+ Language.VHDL.Syntax: [group_constituent_list] :: GroupDeclaration -> GroupConstituentList
+ Language.VHDL.Syntax: [group_identifier] :: GroupDeclaration -> Identifier
+ Language.VHDL.Syntax: [group_template_name] :: GroupDeclaration -> Name
+ Language.VHDL.Syntax: [gs_guarded_signal_list] :: GuardedSignalSpecification -> SignalList
+ Language.VHDL.Syntax: [gs_type_mark] :: GuardedSignalSpecification -> TypeMark
+ Language.VHDL.Syntax: [gtd_entity_class_entry_list] :: GroupTemplateDeclaration -> EntityClassEntryList
+ Language.VHDL.Syntax: [gtd_identifier] :: GroupTemplateDeclaration -> Identifier
+ Language.VHDL.Syntax: [iconst_static_expression] :: InterfaceDeclaration -> Maybe Expression
+ Language.VHDL.Syntax: [iconst_subtype_indication] :: InterfaceDeclaration -> SubtypeIndication
+ Language.VHDL.Syntax: [idecl_identifier_list] :: InterfaceDeclaration -> IdentifierList
+ Language.VHDL.Syntax: [if_also] :: IfStatement -> [(Condition, SequenceOfStatements)]
+ Language.VHDL.Syntax: [if_else] :: IfStatement -> Maybe SequenceOfStatements
+ Language.VHDL.Syntax: [if_label] :: IfStatement -> Maybe Label
+ Language.VHDL.Syntax: [if_then] :: IfStatement -> (Condition, SequenceOfStatements)
+ Language.VHDL.Syntax: [ifile_subtype_indication] :: InterfaceDeclaration -> SubtypeIndication
+ Language.VHDL.Syntax: [iname_expression] :: IndexedName -> [Expression]
+ Language.VHDL.Syntax: [iname_prefix] :: IndexedName -> Prefix
+ Language.VHDL.Syntax: [isig_bus] :: InterfaceDeclaration -> Bool
+ Language.VHDL.Syntax: [isig_mode] :: InterfaceDeclaration -> Maybe Mode
+ Language.VHDL.Syntax: [isig_static_expression] :: InterfaceDeclaration -> Maybe Expression
+ Language.VHDL.Syntax: [isig_subtype_indication] :: InterfaceDeclaration -> SubtypeIndication
+ Language.VHDL.Syntax: [ivar_mode] :: InterfaceDeclaration -> Maybe Mode
+ Language.VHDL.Syntax: [ivar_static_expression] :: InterfaceDeclaration -> Maybe Expression
+ Language.VHDL.Syntax: [ivar_subtype_indication] :: InterfaceDeclaration -> SubtypeIndication
+ Language.VHDL.Syntax: [loop_iteration_scheme] :: LoopStatement -> Maybe IterationScheme
+ Language.VHDL.Syntax: [loop_label] :: LoopStatement -> Maybe Label
+ Language.VHDL.Syntax: [loop_statements] :: LoopStatement -> SequenceOfStatements
+ Language.VHDL.Syntax: [next_label] :: NextStatement -> Maybe Label
+ Language.VHDL.Syntax: [next_loop] :: NextStatement -> Maybe Label
+ Language.VHDL.Syntax: [next_when] :: NextStatement -> Maybe Condition
+ Language.VHDL.Syntax: [null_label] :: NullStatement -> Maybe Label
+ Language.VHDL.Syntax: [options_delay_mechanism] :: Options -> Maybe DelayMechanism
+ Language.VHDL.Syntax: [options_guarded] :: Options -> Bool
+ Language.VHDL.Syntax: [packb_body_declarative_part] :: PackageBody -> PackageBodyDeclarativePart
+ Language.VHDL.Syntax: [packb_simple_name] :: PackageBody -> SimpleName
+ Language.VHDL.Syntax: [packd_declarative_part] :: PackageDeclaration -> PackageDeclarativePart
+ Language.VHDL.Syntax: [packd_identifier] :: PackageDeclaration -> Identifier
+ Language.VHDL.Syntax: [paramspec_discrete_range] :: ParameterSpecification -> DiscreteRange
+ Language.VHDL.Syntax: [paramspec_identifier] :: ParameterSpecification -> Identifier
+ Language.VHDL.Syntax: [physd_primary_unit_declaration] :: PhysicalTypeDefinition -> PrimaryUnitDeclaration
+ Language.VHDL.Syntax: [physd_range_constraint] :: PhysicalTypeDefinition -> RangeConstraint
+ Language.VHDL.Syntax: [physd_secondary_unit_declaration] :: PhysicalTypeDefinition -> [SecondaryUnitDeclaration]
+ Language.VHDL.Syntax: [physd_simple_name] :: PhysicalTypeDefinition -> Maybe SimpleName
+ Language.VHDL.Syntax: [physl_abstract_literal] :: PhysicalLiteral -> Maybe Literal
+ Language.VHDL.Syntax: [physl_unit_name] :: PhysicalLiteral -> Name
+ Language.VHDL.Syntax: [procs_declarative_part] :: ProcessStatement -> ProcessDeclarativePart
+ Language.VHDL.Syntax: [procs_label] :: ProcessStatement -> Maybe Label
+ Language.VHDL.Syntax: [procs_postponed] :: ProcessStatement -> Bool
+ Language.VHDL.Syntax: [procs_sensitivity_list] :: ProcessStatement -> Maybe SensitivityList
+ Language.VHDL.Syntax: [procs_statement_part] :: ProcessStatement -> ProcessStatementPart
+ Language.VHDL.Syntax: [range_dir] :: Range -> Direction
+ Language.VHDL.Syntax: [range_lower] :: Range -> SimpleExpression
+ Language.VHDL.Syntax: [range_upper] :: Range -> SimpleExpression
+ Language.VHDL.Syntax: [rectd_element_declaration] :: RecordTypeDefinition -> [ElementDeclaration]
+ Language.VHDL.Syntax: [rectd_type_simple_name] :: RecordTypeDefinition -> Maybe SimpleName
+ Language.VHDL.Syntax: [relation_operator] :: Relation -> Maybe (RelationalOperator, ShiftExpression)
+ Language.VHDL.Syntax: [relation_shift_expression] :: Relation -> ShiftExpression
+ Language.VHDL.Syntax: [return_expression] :: ReturnStatement -> Maybe Expression
+ Language.VHDL.Syntax: [return_label] :: ReturnStatement -> Maybe Label
+ Language.VHDL.Syntax: [sd_identifier] :: SubtypeDeclaration -> Identifier
+ Language.VHDL.Syntax: [sd_indication] :: SubtypeDeclaration -> SubtypeIndication
+ Language.VHDL.Syntax: [sexp_adding] :: SimpleExpression -> [(AddingOperator, Term)]
+ Language.VHDL.Syntax: [sexp_sign] :: SimpleExpression -> Maybe Sign
+ Language.VHDL.Syntax: [sexp_term] :: SimpleExpression -> Term
+ Language.VHDL.Syntax: [shifte_shift_operator] :: ShiftExpression -> Maybe (ShiftOperator, SimpleExpression)
+ Language.VHDL.Syntax: [shifte_simple_expression] :: ShiftExpression -> SimpleExpression
+ Language.VHDL.Syntax: [si_constraint] :: SubtypeIndication -> Maybe Constraint
+ Language.VHDL.Syntax: [si_resolution_function_name] :: SubtypeIndication -> Maybe Name
+ Language.VHDL.Syntax: [si_type_mark] :: SubtypeIndication -> TypeMark
+ Language.VHDL.Syntax: [signal_expression] :: SignalDeclaration -> Maybe Expression
+ Language.VHDL.Syntax: [signal_identifier_list] :: SignalDeclaration -> IdentifierList
+ Language.VHDL.Syntax: [signal_kind] :: SignalDeclaration -> Maybe SignalKind
+ Language.VHDL.Syntax: [signal_subtype_indication] :: SignalDeclaration -> SubtypeIndication
+ Language.VHDL.Syntax: [slice_discrete_range] :: SliceName -> DiscreteRange
+ Language.VHDL.Syntax: [slice_prefix] :: SliceName -> Prefix
+ Language.VHDL.Syntax: [sname_prefix] :: SelectedName -> Prefix
+ Language.VHDL.Syntax: [sname_suffix] :: SelectedName -> Suffix
+ Language.VHDL.Syntax: [ssa_expression] :: SelectedSignalAssignment -> Expression
+ Language.VHDL.Syntax: [ssa_options] :: SelectedSignalAssignment -> Options
+ Language.VHDL.Syntax: [ssa_selected_waveforms] :: SelectedSignalAssignment -> SelectedWaveforms
+ Language.VHDL.Syntax: [ssa_target] :: SelectedSignalAssignment -> Target
+ Language.VHDL.Syntax: [subfun_designator] :: SubprogramSpecification -> Designator
+ Language.VHDL.Syntax: [subfun_formal_parameter_list] :: SubprogramSpecification -> Maybe FormalParameterList
+ Language.VHDL.Syntax: [subfun_purity] :: SubprogramSpecification -> Maybe Bool
+ Language.VHDL.Syntax: [subfun_type_mark] :: SubprogramSpecification -> TypeMark
+ Language.VHDL.Syntax: [subproc_designator] :: SubprogramSpecification -> Designator
+ Language.VHDL.Syntax: [subproc_formal_parameter_list] :: SubprogramSpecification -> Maybe FormalParameterList
+ Language.VHDL.Syntax: [subprog_declarative_part] :: SubprogramBody -> SubprogramDeclarativePart
+ Language.VHDL.Syntax: [subprog_designator] :: SubprogramBody -> Maybe Designator
+ Language.VHDL.Syntax: [subprog_kind] :: SubprogramBody -> Maybe SubprogramKind
+ Language.VHDL.Syntax: [subprog_specification] :: SubprogramBody -> SubprogramSpecification
+ Language.VHDL.Syntax: [subprog_statement_part] :: SubprogramBody -> SubprogramStatementPart
+ Language.VHDL.Syntax: [sw_last] :: SelectedWaveforms -> (Waveform, Choices)
+ Language.VHDL.Syntax: [sw_optional] :: SelectedWaveforms -> Maybe [(Waveform, Choices)]
+ Language.VHDL.Syntax: [term_factor] :: Term -> Factor
+ Language.VHDL.Syntax: [term_multiplying] :: Term -> [(MultiplyingOperator, Factor)]
+ Language.VHDL.Syntax: [type_mark] :: TypeConversion -> TypeMark
+ Language.VHDL.Syntax: [var_expression] :: VariableDeclaration -> Maybe Expression
+ Language.VHDL.Syntax: [var_identifier_list] :: VariableDeclaration -> IdentifierList
+ Language.VHDL.Syntax: [var_shared] :: VariableDeclaration -> Bool
+ Language.VHDL.Syntax: [var_subtype_indication] :: VariableDeclaration -> SubtypeIndication
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AbstractLiteral
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AccessTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ActualDesignator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ActualPart
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AddingOperator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Aggregate
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AliasDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AliasDesignator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Allocator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ArchitectureBody
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ArrayTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Assertion
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AssertionStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AssociationElement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AssociationList
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AttributeDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AttributeName
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.AttributeSpecification
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Base
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BaseSpecifier
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BaseUnitDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BasedInteger
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BasedLiteral
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BasicCharacter
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BasicGraphicCharacter
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BasicIdentifier
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BindingIndication
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BitStringLiteral
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BitValue
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BlockConfiguration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BlockDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BlockHeader
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BlockSpecification
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.BlockStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.CaseStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.CaseStatementAlternative
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.CharacterLiteral
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Choice
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Choices
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ComponentConfiguration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ComponentDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ComponentInstantiationStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ComponentSpecification
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.CompositeTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConcurrentAssertionStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConcurrentProcedureCallStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConcurrentSignalAssignmentStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConcurrentStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConditionClause
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConditionalSignalAssignment
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConditionalWaveforms
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConfigurationDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConfigurationDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConfigurationItem
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConfigurationSpecification
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConstantDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ConstrainedArrayDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Constraint
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ContextItem
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.DecimalLiteral
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Declaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.DelayMechanism
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.DesignUnit
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Designator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Direction
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.DisconnectionSpecification
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.DiscreteRange
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ElementAssociation
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ElementDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntityAspect
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntityClass
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntityClassEntry
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntityDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntityDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntityDesignator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntityHeader
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntityNameList
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntitySpecification
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntityStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EntityTag
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EnumerationLiteral
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.EnumerationTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ExitStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Exponent
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Expression
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ExtendedDigit
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ExtendedIdentifier
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Factor
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.FileDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.FileOpenInformation
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.FileTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.FormalDesignator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.FormalPart
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.FullTypeDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.FunctionCall
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.GenerateStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.GenerationScheme
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.GenericClause
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.GenericMapAspect
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.GraphicCharacter
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.GroupConstituent
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.GroupDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.GroupTemplateDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.GuardedSignalSpecification
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Identifier
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.IfStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.IncompleteTypeDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.IndexConstraint
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.IndexSpecification
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.IndexSubtypeDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.IndexedName
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.InstantiatedUnit
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.InstantiationList
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.InterfaceDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.InterfaceList
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.IterationScheme
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Letter
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.LetterOrDigit
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.LibraryClause
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.LibraryUnit
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Literal
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.LogicalNameList
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.LogicalOperator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.LoopStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.MiscellaneousOperator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Mode
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.MultiplyingOperator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Name
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.NextStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.NullStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.NumericLiteral
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ObjectDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Options
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.PackageBody
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.PackageBodyDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.PackageDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.PackageDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ParameterSpecification
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.PhysicalLiteral
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.PhysicalTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.PortClause
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.PortMapAspect
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Prefix
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Primary
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.PrimaryUnit
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ProcedureCall
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ProcedureCallStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ProcessDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ProcessStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.QualifiedExpression
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Range
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.RangeConstraint
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.RecordTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Relation
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.RelationalOperator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ReportStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ReturnStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ScalarTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SecondaryUnit
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SecondaryUnitDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SelectedName
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SelectedSignalAssignment
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SelectedWaveforms
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SensitivityClause
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SensitivityList
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SequentialStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ShiftExpression
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.ShiftOperator
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Sign
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SignalAssignmentStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SignalDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SignalKind
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SignalList
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Signature
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SimpleExpression
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SliceName
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.StringLiteral
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SubprogramBody
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SubprogramDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SubprogramKind
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SubprogramSpecification
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SubtypeDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.SubtypeIndication
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Suffix
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Target
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Term
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.TimeoutClause
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.TypeConversion
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.TypeDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.TypeDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.TypeMark
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.UnconstrainedArrayDefinition
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.UseClause
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.VariableAssignmentStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.VariableDeclaration
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.WaitStatement
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.Waveform
+ Language.VHDL.Syntax: instance GHC.Classes.Eq Language.VHDL.Syntax.WaveformElement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AbstractLiteral
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AccessTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ActualDesignator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ActualPart
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AddingOperator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Aggregate
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AliasDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AliasDesignator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Allocator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ArchitectureBody
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ArrayTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Assertion
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AssertionStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AssociationElement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AssociationList
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AttributeDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AttributeName
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.AttributeSpecification
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Base
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BaseSpecifier
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BaseUnitDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BasedInteger
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BasedLiteral
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BasicCharacter
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BasicGraphicCharacter
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BasicIdentifier
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BindingIndication
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BitStringLiteral
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BitValue
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BlockConfiguration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BlockDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BlockHeader
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BlockSpecification
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.BlockStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.CaseStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.CaseStatementAlternative
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.CharacterLiteral
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Choice
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Choices
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ComponentConfiguration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ComponentDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ComponentInstantiationStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ComponentSpecification
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.CompositeTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConcurrentAssertionStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConcurrentProcedureCallStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConcurrentSignalAssignmentStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConcurrentStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConditionClause
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConditionalSignalAssignment
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConditionalWaveforms
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConfigurationDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConfigurationDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConfigurationItem
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConfigurationSpecification
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConstantDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ConstrainedArrayDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Constraint
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ContextItem
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.DecimalLiteral
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Declaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.DelayMechanism
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.DesignUnit
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Designator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Direction
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.DisconnectionSpecification
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.DiscreteRange
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ElementAssociation
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ElementDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntityAspect
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntityClass
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntityClassEntry
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntityDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntityDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntityDesignator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntityHeader
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntityNameList
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntitySpecification
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntityStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EntityTag
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EnumerationLiteral
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.EnumerationTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ExitStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Exponent
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Expression
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ExtendedDigit
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ExtendedIdentifier
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Factor
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.FileDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.FileOpenInformation
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.FileTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.FormalDesignator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.FormalPart
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.FullTypeDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.FunctionCall
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.GenerateStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.GenerationScheme
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.GenericClause
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.GenericMapAspect
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.GraphicCharacter
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.GroupConstituent
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.GroupDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.GroupTemplateDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.GuardedSignalSpecification
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Identifier
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.IfStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.IncompleteTypeDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.IndexConstraint
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.IndexSpecification
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.IndexSubtypeDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.IndexedName
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.InstantiatedUnit
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.InstantiationList
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.InterfaceDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.InterfaceList
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.IterationScheme
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Letter
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.LetterOrDigit
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.LibraryClause
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.LibraryUnit
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Literal
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.LogicalNameList
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.LogicalOperator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.LoopStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.MiscellaneousOperator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Mode
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.MultiplyingOperator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Name
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.NextStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.NullStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.NumericLiteral
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ObjectDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Options
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.PackageBody
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.PackageBodyDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.PackageDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.PackageDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ParameterSpecification
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.PhysicalLiteral
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.PhysicalTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.PortClause
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.PortMapAspect
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Prefix
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Primary
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.PrimaryUnit
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ProcedureCall
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ProcedureCallStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ProcessDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ProcessStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.QualifiedExpression
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Range
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.RangeConstraint
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.RecordTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Relation
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.RelationalOperator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ReportStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ReturnStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ScalarTypeDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SecondaryUnit
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SecondaryUnitDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SelectedName
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SelectedSignalAssignment
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SelectedWaveforms
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SensitivityClause
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SensitivityList
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SequentialStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ShiftExpression
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.ShiftOperator
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Sign
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SignalAssignmentStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SignalDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SignalKind
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SignalList
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Signature
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SimpleExpression
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SliceName
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.StringLiteral
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SubprogramBody
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SubprogramDeclarativeItem
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SubprogramKind
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SubprogramSpecification
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SubtypeDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.SubtypeIndication
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Suffix
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Target
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Term
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.TimeoutClause
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.TypeConversion
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.TypeDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.TypeDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.TypeMark
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.UnconstrainedArrayDefinition
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.UseClause
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.VariableAssignmentStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.VariableDeclaration
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.WaitStatement
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.Waveform
+ Language.VHDL.Syntax: instance GHC.Show.Show Language.VHDL.Syntax.WaveformElement
+ Language.VHDL.Syntax: type ContextClause = Maybe (ContextItem)
+ Language.VHDL.Syntax: type DesignFile = [DesignUnit]
+ Language.VHDL.Syntax: type LogicalName = Identifier
- Language.VHDL.Syntax: DesignUnit :: DesignUnit
+ Language.VHDL.Syntax: DesignUnit :: PrimaryUnit -> SecondaryUnit -> DesignUnit
- Language.VHDL.Syntax: LibraryClause :: LibraryClause
+ Language.VHDL.Syntax: LibraryClause :: LogicalNameList -> LibraryClause
- Language.VHDL.Syntax: LogicalNameList :: LogicalNameList
+ Language.VHDL.Syntax: LogicalNameList :: [LogicalName] -> LogicalNameList
Files
- language-vhdl.cabal +2/−2
- src/Language/VHDL/Pretty.hs +20/−12
- src/Language/VHDL/Syntax.hs +141/−32
language-vhdl.cabal view
@@ -2,8 +2,8 @@ -- documentation, see http://haskell.org/cabal/users-guide/ name: language-vhdl-version: 0.1.1.0-synopsis: VHDL AST and pretty printer in Haskell+version: 0.1.2.0+synopsis: VHDL AST and pretty printer in Haskell. -- description: license: BSD3 license-file: LICENSE
src/Language/VHDL/Pretty.hs view
@@ -18,6 +18,10 @@ where pp = hsep . map pp +instance Pretty a => Pretty (Maybe a)+ where+ pp = maybe empty pp+ -------------------------------------------------------------------------------- -- ** Pretty printing instances @@ -313,9 +317,9 @@ pp (CRange r) = pp r pp (CIndex i) = pp i -instance Pretty ContextClause where pp = error "missing: ContextClause" -- todo--instance Pretty ContextItem where pp = error "missing: ContextItem" -- todo+instance Pretty ContextItem where+ pp (ContextLibrary l) = pp l+ pp (ContextUse u) = pp u instance Pretty DecimalLiteral where pp = error "missing: DecimalLiteral" -- todo @@ -337,9 +341,8 @@ pp (DMechTransport) = text "TRANSPORT" pp (DMechInertial e) = condL (text "REJECT") e <+> text "INERTIAL" -instance Pretty DesignFile where pp = error "missing: DesignFile" -- todo--instance Pretty DesignUnit where pp = error "missing: DesignUnit" -- todo+instance Pretty DesignUnit where+ pp (DesignUnit primary secondary) = pp primary <+> pp secondary instance Pretty Designator where pp (DId i) = pp i@@ -627,7 +630,8 @@ instance Pretty LetterOrDigit where pp = error "missing: LetterOrDigit" -- todo -instance Pretty LibraryClause where pp = error "missing: LibraryClause" -- todo+instance Pretty LibraryClause where+ pp (LibraryClause ns) = text "LIBRARY" <+> pp ns <+> semi instance Pretty LibraryUnit where pp = error "missing: LibraryUnit" -- todo @@ -638,9 +642,8 @@ pp (LitBitString b) = pp b pp (LitNull) = text "NULL" -instance Pretty LogicalName where pp = error "missing: LogicalName" -- todo--instance Pretty LogicalNameList where pp = error "missing: LogicalNameList" -- todo+instance Pretty LogicalNameList where+ pp (LogicalNameList ns) = commaSep $ fmap pp ns instance Pretty LogicalOperator where pp (And) = text "AND"@@ -793,7 +796,10 @@ pp (PrimAlloc a) = pp a pp (PrimExp e) = parens (pp e) -instance Pretty PrimaryUnit where pp = error "missing: PrimaryUnit" -- todo+instance Pretty PrimaryUnit where+ pp (PrimaryEntity e) = pp e+ pp (PrimaryConfig c) = pp c+ pp (PrimaryPackage p) = pp p instance Pretty ProcedureCall where pp (ProcedureCall n ap) = pp n <+> cond parens ap@@ -873,7 +879,9 @@ pp (ScalarFloat f) = pp f pp (ScalarPhys p) = pp p -instance Pretty SecondaryUnit where pp = error "missing: SecondaryUnit" -- todo+instance Pretty SecondaryUnit where+ pp (SecondaryArchitecture a) = pp a+ pp (SecondaryPackage p) = pp p instance Pretty SecondaryUnitDeclaration where pp (SecondaryUnitDeclaration i p) = pp i <+> equals <+> pp p
src/Language/VHDL/Syntax.hs view
@@ -2584,31 +2584,167 @@ deriving (Eq, Show) type Label = Identifier+--------------------------------------------------------------------------------+--+-- -- 10 --+--+-- Scope and visibility+--+-------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- ?+-- ** 10.1 Declarative region -data UseClause = UseClause [SelectedName]+--------------------------------------------------------------------------------+-- ** 10.2 Scope of declarations++--------------------------------------------------------------------------------+-- ** 10.3 Visibility++--------------------------------------------------------------------------------+-- ** 10.4 Use clauses++{-+ use_clause ::=+ USE selected_name { , selected_name } ;+-}++data UseClause = UseClause [SelectedName] deriving (Eq, Show) -data Identifier = Ident String+--------------------------------------------------------------------------------+-- ** 10.5 The context of overload resolution++--------------------------------------------------------------------------------+--+-- -- 11 --+--+-- Design units and their analysis+--+--------------------------------------------------------------------------------++--------------------------------------------------------------------------------+-- ** 11.1 Design units++{-+ design_file ::= design_unit { design_unit }++ design_unit ::= context_clause library_unit++ library_unit ::=+ primary_unit+ | secondary_unit++ primary_unit ::=+ entity_declaration+ | configuration_declaration+ | package_declaration++ secondary_unit ::=+ architecture_body+ | package_body+-}+++type DesignFile = [DesignUnit]++data DesignUnit = DesignUnit {+ design_primary_unit :: PrimaryUnit+ , design_secondary_unit :: SecondaryUnit+ } deriving (Eq, Show) -data CharacterLiteral = CLit Char+data PrimaryUnit =+ PrimaryEntity EntityDeclaration+ | PrimaryConfig ConfigurationDeclaration+ | PrimaryPackage PackageDeclaration deriving (Eq, Show) -data StringLiteral = SLit String+data SecondaryUnit =+ SecondaryArchitecture ArchitectureBody+ | SecondaryPackage PackageBody deriving (Eq, Show) --------------------------------------------------------------------------------+-- ** 11.2 Design libraries++{-+ library_clause ::= LIBRARY logical_name_list ;++ logical_name_list ::= logical_name { , logical_name }++ logical_name ::= identifier+-}++data LibraryClause = LibraryClause LogicalNameList+ deriving (Eq, Show)++data LogicalNameList = LogicalNameList [LogicalName]+ deriving (Eq, Show)++type LogicalName = Identifier++--------------------------------------------------------------------------------+-- ** 11.3 Context clauses++{-+ context_clause ::= { context_item }++ context_item ::=+ library_clause+ | use_clause+-}++type ContextClause = Maybe (ContextItem)++data ContextItem =+ ContextLibrary LibraryClause+ | ContextUse UseClause+ deriving (Eq, Show)++--------------------------------------------------------------------------------+-- ** 11.3 Order of analysis++-------------------------------------------------------------------------------- --+-- -- 12 --+--+-- Elaboration and execution+--+--------------------------------------------------------------------------------++-- ...++--------------------------------------------------------------------------------+--+-- -- 13 --+--+-- Lexical elements+--+--------------------------------------------------------------------------------++-- ...++--------------------------------------------------------------------------------+-- -- - ToDo - -- -------------------------------------------------------------------------------- +data Identifier = Ident String+ deriving (Eq, Show)++data CharacterLiteral = CLit Char+ deriving (Eq, Show)++data StringLiteral = SLit String+ deriving (Eq, Show)+ data AbstractLiteral = AbstractLiteral deriving (Eq, Show) +--------------------------------------------------------------------------------+ data Base = Base deriving (Eq, Show) @@ -2639,21 +2775,9 @@ data BitValue = BitValue deriving (Eq, Show) -data ContextClause = ContextClause- deriving (Eq, Show)--data ContextItem = ContextItem- deriving (Eq, Show)- data DecimalLiteral = DecimalLiteral deriving (Eq, Show) -data DesignFile = DesignFile- deriving (Eq, Show)--data DesignUnit = DesignUnit- deriving (Eq, Show)- data Exponent = Exponent deriving (Eq, Show) @@ -2672,22 +2796,7 @@ data LetterOrDigit = LetterOrDigit deriving (Eq, Show) -data LibraryClause = LibraryClause- deriving (Eq, Show)- data LibraryUnit = LibraryUnit- deriving (Eq, Show)--data LogicalName = LogicalName- deriving (Eq, Show)--data LogicalNameList = LogicalNameList- deriving (Eq, Show)--data PrimaryUnit = PrimaryUnit- deriving (Eq, Show)--data SecondaryUnit = SecondaryUnit deriving (Eq, Show) --------------------------------------------------------------------------------