diff --git a/kansas-lava-papilio.cabal b/kansas-lava-papilio.cabal
--- a/kansas-lava-papilio.cabal
+++ b/kansas-lava-papilio.cabal
@@ -1,5 +1,5 @@
 Name:               kansas-lava-papilio
-Version:            0.2.0
+Version:            0.3.0
 Synopsis:           Kansas Lava support files for the Papilio FPGA board
 Description:
         IO definitions of the Papilio FPGA board and its Wings and MegaWings
@@ -40,12 +40,12 @@
         Hardware.KansasLava.Boards.Papilio.UCF
         Hardware.KansasLava.Boards.Papilio.LogicStart
         Hardware.KansasLava.Boards.Papilio.Arcade
+        Hardware.KansasLava.Xilinx.DCM
   Other-modules:
         Paths_kansas_lava_papilio
 
   Hs-Source-Dirs: src
   Other-modules:
-  -- Ghc-Options: -fcontext-stack=100
   Ghc-Options: -Werror -fwarn-unused-imports -fwarn-unused-matches -fwarn-unused-binds
   default-language:    Haskell2010
 
diff --git a/src/Hardware/KansasLava/VGA/Driver.hs b/src/Hardware/KansasLava/VGA/Driver.hs
--- a/src/Hardware/KansasLava/VGA/Driver.hs
+++ b/src/Hardware/KansasLava/VGA/Driver.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE ScopedTypeVariables #-}
 {-# LANGUAGE RecordWildCards #-}
 module Hardware.KansasLava.VGA.Driver
        ( -- * Generic VGA driver
@@ -39,19 +40,22 @@
 
 data VGATiming a = VGATiming{ visibleSize, pre, syncPulse, post :: Unsigned a }
 
-driveVGA :: (Clock clk, Rep n, Eq n, Num n, Rep r, Rep g, Rep b, Size w, Size h)
-         => n                           -- ^ clock divider
+driveVGA :: forall clk n r g b w h.
+            (Clock clk,
+             Rep n, Eq n, Num n, Bounded n,
+             Rep r, Rep g, Rep b, Size w, Size h)
+         => Witness n                           -- ^ clock divider
          -> VGAParams w h
          -> VGADriverIn clk r g b
          -> VGADriverOut clk w h r g b
-driveVGA divider VGAParams{..} VGADriverIn{..} = runRTL $ do
+driveVGA _divider VGAParams{..} VGADriverIn{..} = runRTL $ do
     hCount <- newReg 0
     vCount <- newReg 0
 
     let hEnd = reg hCount .==. pureS hMax
         vEnd = reg vCount .==. pureS vMax
 
-    let counter = iterateS (\s -> mux (s + 1 .==. pureS divider) (s + 1, 0)) 0
+    let counter = register (0 :: n) $ loopingIncS counter
         phase = counter .==. 0
 
     WHEN phase $ do
diff --git a/src/Hardware/KansasLava/Xilinx/DCM.hs b/src/Hardware/KansasLava/Xilinx/DCM.hs
new file mode 100644
--- /dev/null
+++ b/src/Hardware/KansasLava/Xilinx/DCM.hs
@@ -0,0 +1,44 @@
+{-# LANGUAGE RecordWildCards #-}
+module Hardware.KansasLava.Xilinx.DCM (dcm) where
+
+import Language.Netlist.AST
+
+-- | Interface to the Xilinx Digital Clock Manager module.
+--
+-- The DCM definition itself must be created separately in the Xilinx ISE as a
+-- @.xaw@ file.
+--
+-- The following example creates a circuit running at 16 MHz with a native
+-- clock signal of 32 MHz.
+--
+-- > kleg <- reifyFabric $ do
+-- >     theClk "CLK_16MHZ"
+-- >     fabric
+-- > mod <- netlistCircuit modName kleg
+-- > let mod' = dcm "dcm_32_to_16" "CLK_32MHZ" "CLK_16MHZ" mod
+-- >     vhdl = genVHDL mod' ["work.lava.all", "work.all"]
+-- > return vhdl
+dcm :: Ident  -- ^ Name of the instantiated DCM module
+    -> Ident  -- ^ @rawClock@: Name of the raw clock signal
+             --   (usually, connected via the UCF to some crystal)
+    -> Ident  -- ^ @newClock@: Name of the new clock signal (the output of the DCM)
+    -> Module -- ^ Module using @newClock@ as its clock signal, to be wrapped
+    -> Module
+dcm dcmName rawClock newClock Module{..} = Module name inputs outputs [] decls
+  where
+    name = module_name
+    inputs = (rawClock, Nothing) : filter ((/= newClock) . fst) module_inputs
+    outputs = module_outputs
+    decls = routing : dcmInst : module_decls
+
+    routing = NetDecl newClock Nothing Nothing
+
+    dcmInst = InstDecl ("work." ++ dcmName) ("inst_" ++ dcmName) []
+              [ ("clkin_in",        ExprVar rawClock)
+              , ("clkin_ibufg_out", open)
+              ]
+              [ ("clkfx_out",       ExprVar newClock)
+              , ("clk0_out",        open)
+              ]
+
+    open = ExprVar "open"