kansas-lava-papilio 0.1.0 → 0.2.0
raw patch · 6 files changed
+46/−26 lines, 6 filessetup-changedPVP ok
version bump matches the API change (PVP)
API changes (from Hackage documentation)
+ Hardware.KansasLava.VGA.Driver: vga800x600at60 :: VGAParams X11 X10
+ Hardware.KansasLava.VGA.Driver: vga800x600at72 :: VGAParams X11 X10
- Hardware.KansasLava.VGA.Driver: driveVGA :: (Clock clk, Rep r, Rep g, Rep b, Size w, Size h) => VGAParams w h -> VGADriverIn clk r g b -> VGADriverOut clk w h r g b
+ Hardware.KansasLava.VGA.Driver: driveVGA :: (Clock clk, Rep n, Eq n, Num n, Rep r, Rep g, Rep b, Size w, Size h) => n -> VGAParams w h -> VGADriverIn clk r g b -> VGADriverOut clk w h r g b
Files
- LICENSE +1/−1
- Setup.hs +4/−0
- kansas-lava-papilio.cabal +4/−4
- src/Hardware/KansasLava/VGA/Driver.hs +22/−6
- ucf/Arcade-One.ucf +4/−4
- ucf/Arcade-Pro.ucf +11/−11
LICENSE view
@@ -1,4 +1,4 @@-Copyright (c) 2012 Gergo Erdi+Copyright (c) 2012 Gergő Érdi <gergo@erdi.hu> All rights reserved. Redistribution and use in source and binary forms, with or without
Setup.hs view
@@ -1,2 +1,6 @@+module Main (main) where+ import Distribution.Simple++main :: IO () main = defaultMain
kansas-lava-papilio.cabal view
@@ -1,5 +1,5 @@ Name: kansas-lava-papilio-Version: 0.1.0+Version: 0.2.0 Synopsis: Kansas Lava support files for the Papilio FPGA board Description: IO definitions of the Papilio FPGA board and its Wings and MegaWings@@ -7,9 +7,9 @@ Category: Hardware License: BSD3 License-file: LICENSE-Copyright: (C) 2012-2014 Gergo Erdi-Author: Gergo Erdi-Maintainer: Gergo Erdi <gergo@erdi.hu>+Copyright: (C) 2012 Gergő Érdi+Author: Gergő Érdi+Maintainer: Gergő Érdi <gergo@erdi.hu> Stability: alpha build-type: Simple Cabal-Version: >= 1.10
src/Hardware/KansasLava/VGA/Driver.hs view
@@ -8,6 +8,8 @@ , driveVGA -- * Timing parameters for predefined VGA modes , vga640x480at60+ , vga800x600at72+ , vga800x600at60 ) where import Language.KansasLava@@ -37,19 +39,21 @@ data VGATiming a = VGATiming{ visibleSize, pre, syncPulse, post :: Unsigned a } --- | Assumes a circuit clock at double the frequency of the pixel clock-driveVGA :: (Clock clk, Rep r, Rep g, Rep b, Size w, Size h)- => VGAParams w h+driveVGA :: (Clock clk, Rep n, Eq n, Num n, Rep r, Rep g, Rep b, Size w, Size h)+ => n -- ^ clock divider+ -> VGAParams w h -> VGADriverIn clk r g b -> VGADriverOut clk w h r g b-driveVGA VGAParams{..} VGADriverIn{..} = runRTL $ do+driveVGA divider VGAParams{..} VGADriverIn{..} = runRTL $ do hCount <- newReg 0 vCount <- newReg 0 let hEnd = reg hCount .==. pureS hMax vEnd = reg vCount .==. pureS vMax - let phase = iterateS bitNot False+ let counter = iterateS (\s -> mux (s + 1 .==. pureS divider) (s + 1, 0)) 0+ phase = counter .==. 0+ WHEN phase $ do hCount := mux hEnd (reg hCount + 1, 0) WHEN hEnd $ do@@ -97,5 +101,17 @@ -- | VGA 640*480@60Hz, 25.175 MHz pixel clock vga640x480at60 :: VGAParams X10 X10 vga640x480at60 = VGAParams{ vgaHorizTiming = VGATiming 640 16 96 48- , vgaVertTiming = VGATiming 480 16 2 33+ , vgaVertTiming = VGATiming 480 10 2 33+ }++-- | VGA 800x600@72Hz, 50 MHz pixel clock+vga800x600at72 :: VGAParams X11 X10+vga800x600at72 = VGAParams{ vgaHorizTiming = VGATiming 800 56 120 64+ , vgaVertTiming = VGATiming 600 37 6 23+ }++-- | VGA 800x600@60Hz, 40 MHz pixel clock+vga800x600at60 :: VGAParams X11 X10+vga800x600at60 = VGAParams{ vgaHorizTiming = VGATiming 800 40 128 88+ , vgaVertTiming = VGATiming 600 1 4 23 }
ucf/Arcade-One.ucf view
@@ -61,9 +61,9 @@ NET "VGA_G<1>" LOC="P66" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B5 NET "VGA_G<2>" LOC="P63" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B6 NET "VGA_G<3>" LOC="P61" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B7-NET "VGA_B<0>" LOC="P85" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B0-NET "VGA_B<1>" LOC="P83" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B1-NET "VGA_B<2>" LOC="P78" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B2-NET "VGA_B<3>" LOC="P71" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3+NET "VGA_B<0>" LOC="P83" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B1+NET "VGA_B<1>" LOC="P78" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B2+NET "VGA_B<2>" LOC="P71" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3+NET "VGA_B<3>" LOC="P85" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B0 NET "VGA_VSYNC" LOC="P94" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3 NET "VGA_HSYNC" LOC="P95" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3
ucf/Arcade-Pro.ucf view
@@ -50,16 +50,16 @@ # VGA NET "VGA_R<0>" LOC="P118" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C4-NET "VGA_R<1>" LOC="P119" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C5-NET "VGA_R<2>" LOC="P120" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C6-NET "VGA_R<3>" LOC="P121" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C7-NET "VGA_G<0>" LOC="P84" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B4-NET "VGA_G<1>" LOC="P82" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B5-NET "VGA_G<2>" LOC="P80" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B6-NET "VGA_G<3>" LOC="P78" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B7-NET "VGA_B<0>" LOC="P99" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B0-NET "VGA_B<1>" LOC="P97" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B1-NET "VGA_B<2>" LOC="P92" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B2-NET "VGA_B<3>" LOC="P87" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3+NET "VGA_R<1>" LOC="P119" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C5+NET "VGA_R<2>" LOC="P120" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C6+NET "VGA_R<3>" LOC="P121" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C7+NET "VGA_G<0>" LOC="P84" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B4+NET "VGA_G<1>" LOC="P82" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B5+NET "VGA_G<2>" LOC="P80" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B6+NET "VGA_G<3>" LOC="P78" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B7+NET "VGA_B<0>" LOC="P97" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B1+NET "VGA_B<1>" LOC="P92" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B2+NET "VGA_B<2>" LOC="P87" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3+NET "VGA_B<3>" LOC="P99" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B0 NET "VGA_VSYNC" LOC="P116" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3 NET "VGA_HSYNC" LOC="P117" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3