diff --git a/CHANGELOG.md b/CHANGELOG.md --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,8 @@ # Revision history for ice40-prim +## 0.3.1.4 -- 2024-01-15 +* Update dependency bounds: clash-prelude-1.8 + ## 0.3.1.3 -- 2022-02-13 * Update dependency bounds: clash-prelude-1.6.1 * clash-prelude >= 1.2.5 && < 1.7 diff --git a/README.md b/README.md --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # ice40-prim -![Haskell CI](https://github.com/standardsemiconductor/ice40-prim/workflows/Haskell%20CI/badge.svg) +![Haskell CI](https://github.com/standardsemiconductor/ice40-prim/actions/workflows/haskell.yml/badge.svg) [![Hackage][hackage-badge]][hackage] [![Hackage Dependencies][hackage-deps-badge]][hackage-deps] diff --git a/ice40-prim.cabal b/ice40-prim.cabal --- a/ice40-prim.cabal +++ b/ice40-prim.cabal @@ -1,6 +1,6 @@ cabal-version: >=1.10 name: ice40-prim -version: 0.3.1.3 +version: 0.3.1.4 synopsis: Lattice iCE40 Primitive IP description: Clash primitives to instantiate Lattice Semiconductor's iCE40 FPGA hard IP bug-reports: https://github.com/standardsemiconductor/ice40-prim/issues @@ -8,7 +8,7 @@ license-file: LICENSE author: dopamane maintainer: dopamane -copyright: Copyright (c) 2020-2022 David Cox +copyright: Copyright (c) 2020-2024 David Cox category: Hardware build-type: Simple extra-source-files: CHANGELOG.md, README.md @@ -32,21 +32,23 @@ Ice40.Spi, Ice40.Spram hs-source-dirs: src - build-depends: base >= 4.12 && < 4.17, + build-depends: base >= 4.12 && < 4.20, interpolate >= 0.2 && < 0.3, - clash-prelude >= 1.2.5 && < 1.7, + clash-prelude >= 1.2.5 && < 1.9, ghc-typelits-natnormalise, ghc-typelits-extra, ghc-typelits-knownnat ghc-options: -Wall -Wcompat -haddock - -fplugin GHC.TypeLits.Extra.Solver -fplugin GHC.TypeLits.Normalise -fplugin GHC.TypeLits.KnownNat.Solver -fexpose-all-unfoldings -fno-worker-wrapper + -fconstraint-solver-iterations=0 + -fno-unbox-small-strict-fields + -fno-unbox-strict-fields default-language: Haskell2010 default-extensions: BangPatterns diff --git a/src/Ice40/Clock.hs b/src/Ice40/Clock.hs --- a/src/Ice40/Clock.hs +++ b/src/Ice40/Clock.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.Clock Description : Ice40 Clock domains -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com @@ -33,4 +33,4 @@ -- | Lattice reset signal, always inactive latticeRst :: KnownDomain dom => Reset dom -latticeRst = unsafeFromHighPolarity $ pure False +latticeRst = unsafeFromActiveHigh $ pure False diff --git a/src/Ice40/GB.hs b/src/Ice40/GB.hs --- a/src/Ice40/GB.hs +++ b/src/Ice40/GB.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.GB Description : Ice40 Global Buffer IP primtive -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD-3-Clause Maintainer : standardsemiconductor@gmail.com diff --git a/src/Ice40/I2c.hs b/src/Ice40/I2c.hs --- a/src/Ice40/I2c.hs +++ b/src/Ice40/I2c.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.I2c Description : Ice40 I2C hard IP primitive -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com diff --git a/src/Ice40/IO.hs b/src/Ice40/IO.hs --- a/src/Ice40/IO.hs +++ b/src/Ice40/IO.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.IO Description : Ice40 IO hard IP primitives -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com diff --git a/src/Ice40/Led.hs b/src/Ice40/Led.hs --- a/src/Ice40/Led.hs +++ b/src/Ice40/Led.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.Led Description : LED Ice40 hard IP primitive -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com diff --git a/src/Ice40/Mac.hs b/src/Ice40/Mac.hs --- a/src/Ice40/Mac.hs +++ b/src/Ice40/Mac.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.Mac Description : Ice40 Multiply-Accumulate primitive wrapper -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD-3-Clause Maintainer : standardsemiconductor@gmail.com diff --git a/src/Ice40/Mac/Prim.hs b/src/Ice40/Mac/Prim.hs --- a/src/Ice40/Mac/Prim.hs +++ b/src/Ice40/Mac/Prim.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.Mac.Prim Description : Ice40 Multiply-Accumulate (DSP) hard IP primitive -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com diff --git a/src/Ice40/Osc.hs b/src/Ice40/Osc.hs --- a/src/Ice40/Osc.hs +++ b/src/Ice40/Osc.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.Osc Description : Ice40 oscillator hard IP primitives -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com @@ -54,7 +54,7 @@ :: Signal dom Bool -- ^ CLKLFPU - Power up the LFOSC circuit. After power up, oscillator output will be stable after 100us. Active High. -> Signal dom Bool -- ^ CLKLFEN - Enable the clock output. Enable should be low for the 100us power up period. Active High. -> Clock Lattice10kHz -- ^ LF Oscillator output -lf10kHz !_ !_ = Clock SSymbol +lf10kHz !_ !_ = Clock SSymbol Nothing ------------------------------- -- High Frequency Oscillator -- @@ -94,7 +94,7 @@ -> Signal dom Bool -- ARG[3] clkhfen -> Signal dom Bool -- ARG[4] clkhfpu -> Clock dom' -- clkhf" -hfPrim !_ !_ !_ = Clock SSymbol +hfPrim !_ !_ !_ = Clock SSymbol Nothing -- | High frequency oscillator 48 Mhz hf48Mhz diff --git a/src/Ice40/Pll/Core.hs b/src/Ice40/Pll/Core.hs --- a/src/Ice40/Pll/Core.hs +++ b/src/Ice40/Pll/Core.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.Pll.Core Description : Ice40 PLL hard IP primitive -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com PLL Core hard IP primitive from [Lattice Ice Technology Library](https://github.com/standardsemiconductor/VELDT-info/blob/master/SBTICETechnologyLibrary201708.pdf). The PLL core primitive should be used when the source clock of the PLL is driven by FPGA routing i.e. when the PLL source clock originates on the FPGA or is driven by an input pad the is not in the bottom IO bank (IO Bank 2). diff --git a/src/Ice40/Pll/Pad.hs b/src/Ice40/Pll/Pad.hs --- a/src/Ice40/Pll/Pad.hs +++ b/src/Ice40/Pll/Pad.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.Pll.Pad Description : Ice40 PLL Pad hard IP primitive -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com diff --git a/src/Ice40/Rgb.hs b/src/Ice40/Rgb.hs --- a/src/Ice40/Rgb.hs +++ b/src/Ice40/Rgb.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.Rgb Description : Ice40 RGB hard IP primitive -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com diff --git a/src/Ice40/Spi.hs b/src/Ice40/Spi.hs --- a/src/Ice40/Spi.hs +++ b/src/Ice40/Spi.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.Spi Description : Ice40 SPI hard IP primitive -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com diff --git a/src/Ice40/Spram.hs b/src/Ice40/Spram.hs --- a/src/Ice40/Spram.hs +++ b/src/Ice40/Spram.hs @@ -1,7 +1,7 @@ {-| Module : Ice40.Spram Description : Ice40 single-port RAM hard IP primitive -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2021-2024 License : BSD 3-Clause Maintainer : standardsemiconductor@gmail.com