ice40-prim 0.3.1.0 → 0.3.1.1

raw patch · 6 files changed

+13/−9 lines, 6 filesPVP ok

version bump matches the API change (PVP)

API changes (from Hackage documentation)

Files

CHANGELOG.md +4/−0
ice40-prim.cabal +2/−2
src/Ice40/I2c.hs +1/−1
src/Ice40/Led.hs +1/−1
src/Ice40/Spi.hs +1/−1
src/Ice40/Spram.hs +4/−4

CHANGELOG.md view

@@ -1,5 +1,9 @@ # Revision history for ice40-prim +## 0.3.1.1 -- 2021-07-1++* Fix bit index operator spacing for GHC 9.0+ ## 0.3.1.0 -- 2021-03-30 * Add Global Buffer IP, Ice40.GB * Update documentation

ice40-prim.cabal view

@@ -1,6 +1,6 @@ cabal-version:       >=1.10 name:                ice40-prim-version:             0.3.1.0+version:             0.3.1.1 synopsis:            Lattice iCE40 Primitive IP description:         Clash primitives to instantiate Lattice Semiconductor's iCE40 FPGA hard IP bug-reports:         https://github.com/standardsemiconductor/ice40-prim/issues@@ -45,7 +45,7 @@           -fplugin GHC.TypeLits.Extra.Solver           -fplugin GHC.TypeLits.Normalise           -fplugin GHC.TypeLits.KnownNat.Solver-+          -fexpose-all-unfoldings           -fno-worker-wrapper         default-language: Haskell2010         default-extensions:

src/Ice40/I2c.hs view

@@ -228,4 +228,4 @@           sdai  bitAt :: KnownNat n => Index n -> Signal dom (BitVector n) -> Signal dom Bit-bitAt n = fmap (!n)+bitAt n = fmap (! n)

src/Ice40/Led.hs view

@@ -162,4 +162,4 @@    bitAt :: KnownNat n => Index n -> Signal dom (BitVector n) -> Signal dom Bit-bitAt n = fmap (!n)+bitAt n = fmap (! n)

src/Ice40/Spi.hs view

@@ -67,7 +67,7 @@           wcsni  bitAt :: KnownNat n => Index n -> Signal dom (BitVector n) -> Signal dom Bit-bitAt n = fmap (!n)+bitAt n = fmap (! n)  {-# ANN spiPrim (InlinePrimitive [Verilog] $ unindent [i|   [  { "BlackBox" :

src/Ice40/Spram.hs view

@@ -88,10 +88,10 @@       Nyb1 -> slice d7  d4       Nyb0 -> slice d3  d0     nybMask = \case-      Nyb3 -> (!(3 :: Index 4))-      Nyb2 -> (!(2 :: Index 4))-      Nyb1 -> (!(1 :: Index 4))-      Nyb0 -> (!(0 :: Index 4))+      Nyb3 -> (! (3 :: Index 4))+      Nyb2 -> (! (2 :: Index 4))+      Nyb1 -> (! (1 :: Index 4))+      Nyb0 -> (! (0 :: Index 4))     writeGuard n dIn addr en mask       | bitToBool en && (not.bitToBool) (nybMask n mask) = Just (addr, nybSlice n dIn)       | otherwise = Nothing