diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,9 @@
 # Revision history for ice40-prim
 
+## 0.3.1.0 -- 2021-03-30
+* Add Global Buffer IP, Ice40.GB
+* Update documentation
+
 ## 0.3.0.1 -- 2021-03-28
 
 * Minor documentation updates
diff --git a/README.md b/README.md
--- a/README.md
+++ b/README.md
@@ -19,7 +19,7 @@
   * 32-bit, or two independent 16-bit adder/subtractor functions, registered or asynchronous
   * Cascadable to create wider accumulator blocks
 
-* [Ice40.Osc](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/Osc.hs) - For more information see the [
+* [Ice40.Osc](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/Osc.hs) - For more information see the [iCE40 Oscillator Usage Guide](https://github.com/standardsemiconductor/VELDT-info/blob/master/FPGA-TN-02008-1-7-iCE40-Oscillator-Usage-Guide.pdf)
   * on-chip oscillator
   * Low-power low frequency oscillator of 10 kHz
   * High frequency oscillator configurable to 48 Mhz, 24 Mhz, 12 Mhz, or 6 Mhz
@@ -56,7 +56,11 @@
   * LSB First or MSB First data transfer
 
 * [Ice40.IO](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/IO.hs)
-  * sysIO
+  * IO primitive
+
+* [Ice40.GB](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/GB.hs)
+  * Global buffer primitive
+  * Required for a user's internally generated FPGA signal that is heavily loaded and requires global buffering; for example, a user's logic-generated clock
 
 * [Ice40.I2c](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/I2c.hs) - For more information see the [Advanced SPI and I2C Usage Guide PDF](https://github.com/standardsemiconductor/VELDT-info/blob/master/AdvancediCE40SPII2CHardenedIPUsageGuide.pdf)
   * User I2C IP
diff --git a/ice40-prim.cabal b/ice40-prim.cabal
--- a/ice40-prim.cabal
+++ b/ice40-prim.cabal
@@ -1,6 +1,6 @@
 cabal-version:       >=1.10
 name:                ice40-prim
-version:             0.3.0.1
+version:             0.3.1.0
 synopsis:            Lattice iCE40 Primitive IP
 description:         Clash primitives to instantiate Lattice Semiconductor's iCE40 FPGA hard IP
 bug-reports:         https://github.com/standardsemiconductor/ice40-prim/issues
@@ -19,6 +19,7 @@
                      
 library
         exposed-modules: Ice40.Clock,
+                         Ice40.GB,
                          Ice40.I2c,
                          Ice40.IO
                          Ice40.Led,
@@ -32,7 +33,6 @@
                          Ice40.Spram
         hs-source-dirs: src
         build-depends: base          >= 4.12  && < 4.16,
-                       Cabal,
                        interpolate   >= 0.2   && < 0.3,
                        clash-prelude >= 1.2.5 && < 1.5,
                        ghc-typelits-natnormalise,
diff --git a/src/Ice40/GB.hs b/src/Ice40/GB.hs
new file mode 100644
--- /dev/null
+++ b/src/Ice40/GB.hs
@@ -0,0 +1,41 @@
+{-|
+Module      : Ice40.GB
+Description : Ice40 Global Buffer IP primtive
+Copyright   : (c) David Cox, 2021
+License     : BSD-3-Clause
+Maintainer  : standardsemiconductor@gmail.com
+
+Global buffer IP primitive from [Lattice Ice Technology Library](https://github.com/standardsemiconductor/VELDT-info/blob/master/SBTICETechnologyLibrary201708.pdf).
+Required for a user's internally generated FPGA signal that is heavily loaded and requires global buffering; for example, a user's logic-generated clock.
+-}
+module Ice40.GB where
+
+import Clash.Prelude
+import Clash.Annotations.Primitive
+import Data.String.Interpolate (i)
+import Data.String.Interpolate.Util (unindent)
+
+{-# ANN gbPrim (InlinePrimitive [Verilog] $ unindent [i|
+  [  { "BlackBox" :
+       { "name" : "Ice40.GB.gbPrim"
+       , "kind" : "Declaration"
+       , "type" :
+  "gbPrim
+    :: Clock dom -- ARG[0]
+    -> Clock dom"
+       , "template" :
+  "//SB_GB begin
+  SB_GB ~GENSYM[sb_gb_inst][0] (
+    .USER_SIGNAL_TO_GLOBAL_BUFFER ( ~ARG[0] ),
+    .GLOBAL_BUFFER_OUTPUT         ( ~RESULT )
+  );
+  //SB_GB end"
+       }
+     }
+  ]
+  |]) #-}
+
+-- | Global buffer primitive
+{-# NOINLINE gbPrim #-}
+gbPrim :: Clock dom -> Clock dom
+gbPrim !clk = clk
diff --git a/src/Ice40/IO.hs b/src/Ice40/IO.hs
--- a/src/Ice40/IO.hs
+++ b/src/Ice40/IO.hs
@@ -95,6 +95,7 @@
   deriving stock (Generic, Show, Read, Eq)
   deriving anyclass NFDataX
 
+-- | Convert `PinInput` to underlying `BitVector`
 fromPinInput :: PinInput -> BitVector 2
 fromPinInput = \case
   PinInput                -> 0b01
@@ -120,6 +121,7 @@
   deriving stock (Generic, Show, Read, Eq)
   deriving anyclass NFDataX
 
+-- | Convert `PinOutput` to underlying `BitVector`
 fromPinOutput :: PinOutput -> BitVector 4
 fromPinOutput = \case
   PinNoOutput                                 -> 0b0000
@@ -141,6 +143,7 @@
                 | SBLVDSINPUT
   deriving (Generic, Show, Read, Eq)
 
+-- | Convert `IOStandard` to underlying `String`
 fromIOStandard :: IOStandard -> String
 fromIOStandard = \case
   SBLVCMOS    -> "SB_LVCMOS"
diff --git a/src/Ice40/Pll/Core.hs b/src/Ice40/Pll/Core.hs
--- a/src/Ice40/Pll/Core.hs
+++ b/src/Ice40/Pll/Core.hs
@@ -75,6 +75,7 @@
   ]
   |]) #-}
 
+-- | PLL Core primitive
 {-# NOINLINE pllCorePrim #-}
 pllCorePrim 
   :: KnownDomain dom'            -- ARG[0]
diff --git a/src/Ice40/Pll/Pad.hs b/src/Ice40/Pll/Pad.hs
--- a/src/Ice40/Pll/Pad.hs
+++ b/src/Ice40/Pll/Pad.hs
@@ -76,6 +76,7 @@
   ]
   |]) #-}
 
+-- | PLL Pad primitive
 {-# NOINLINE pllPadPrim #-}
 pllPadPrim 
   :: KnownDomain dom'         -- ARG[0]