ice40-prim 0.2.0.0 → 0.3.0.0
raw patch · 6 files changed
+225/−7 lines, 6 filesdep ~clash-preludePVP ok
version bump matches the API change (PVP)
Dependency ranges changed: clash-prelude
API changes (from Hackage documentation)
+ Ice40.Pll.Core: pllCorePrim :: KnownDomain dom' => BitVector 7 -> BitVector 3 -> BitVector 4 -> String -> BitVector 3 -> String -> String -> String -> BitVector 4 -> BitVector 4 -> Bit -> Clock dom -> Signal dom (BitVector 8) -> Signal dom Bit -> Signal dom Bit -> (Clock dom', Clock dom', Signal dom' Bool)
+ Ice40.Pll.Pad: pllPadPrim :: KnownDomain dom' => BitVector 7 -> BitVector 3 -> BitVector 4 -> String -> BitVector 3 -> String -> String -> String -> BitVector 4 -> BitVector 4 -> Bit -> Clock dom -> Signal dom (BitVector 8) -> Signal dom Bit -> Signal dom Bit -> (Clock dom', Clock dom', Signal dom' Bool)
Files
- CHANGELOG.md +5/−0
- README.md +11/−1
- ice40-prim.cabal +7/−5
- src/Ice40/Osc.hs +1/−1
- src/Ice40/Pll/Core.hs +100/−0
- src/Ice40/Pll/Pad.hs +101/−0
CHANGELOG.md view
@@ -1,5 +1,10 @@ # Revision history for ice40-prim +## 0.3.0.0 -- 2021-03-12++* Add PLL IP, pad and core+* Generate ice40 High Frequency Oscillator primitive instance+ ## 0.2.0.0 -- 2021-03-3 * Add MAC wrapper as Ice40.Mac, move MAC primitive to Ice40.Mac.Prim
README.md view
@@ -19,12 +19,20 @@ * 32-bit, or two independent 16-bit adder/subtractor functions, registered or asynchronous * Cascadable to create wider accumulator blocks -* [Ice40.Osc](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/Osc.hs)+* [Ice40.Osc](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/Osc.hs) - For more information see the [ * on-chip oscillator * Low-power low frequency oscillator of 10 kHz * High frequency oscillator configurable to 48 Mhz, 24 Mhz, 12 Mhz, or 6 Mhz * See also [Ice40.Clock](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/Clock.hs) for clock domains and reset +* [Ice40.Pll](https://github.com/standardsemiconductor/ice40-prim/tree/main/src/Ice40/Pll) - For more information see the [iCE40 sysCLOCK PLL Design and Usage Guide](https://github.com/standardsemiconductor/VELDT-info/blob/master/iCE40sysCLOCKPLLDesignandUsageGuide.pdf)+ * [Pad](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/Pll/Pad.hs) and [Core](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/Pll/Core.hs) variants+ * Phase Lock Loop (PLL)+ * Provides a variety of user-synthesizable clock frequencies along with custom phase delays+ * Generates a new output clock freuquency via clock multiplication and division+ * De-skews or phase-aligns an output clock to the input reference clock+ * Corrects output clock to have nearly a 50% duty cycle, which is important for Double Data Rate (DDR) applications+ * [Ice40.Rgb](https://github.com/standardsemiconductor/ice40-prim/blob/main/src/Ice40/Rgb.hs) - For more information see the [iCE40 LED Driver Usage Guide](https://github.com/standardsemiconductor/VELDT-info/blob/master/ICE40LEDDriverUsageGuide.pdf) * RGB High Current Drive I/O Pins * Provides sinking current to an LED connecting to the positive supply@@ -74,6 +82,8 @@ [iCE40 SPRAM Usage Guide](https://github.com/standardsemiconductor/VELDT-info/blob/master/FPGA-TN-02022-1-2-iCE40-SPRAM-Usage-Guide.pdf) [DSP Function Usage Guide PDF](https://github.com/standardsemiconductor/VELDT-info/blob/master/DSPFunctionUsageGuideforICE40Devices.pdf)++[iCE40 sysCLOCK PLL Design and Usage Guide](https://github.com/standardsemiconductor/VELDT-info/blob/master/iCE40sysCLOCKPLLDesignandUsageGuide.pdf) [hackage]: <https://hackage.haskell.org/package/ice40-prim> [hackage-badge]: <https://img.shields.io/hackage/v/ice40-prim.svg?color=success>
ice40-prim.cabal view
@@ -1,6 +1,6 @@ cabal-version: >=1.10 name: ice40-prim-version: 0.2.0.0+version: 0.3.0.0 synopsis: Lattice iCE40 Primitive IP description: Clash primitives to instantiate Lattice Semiconductor's iCE40 FPGA hard IP bug-reports: https://github.com/standardsemiconductor/ice40-prim/issues@@ -19,20 +19,22 @@ library exposed-modules: Ice40.Clock,+ Ice40.I2c,+ Ice40.IO Ice40.Led, Ice40.Mac, Ice40.Mac.Prim, Ice40.Osc,- Ice40.Spram,+ Ice40.Pll.Core,+ Ice40.Pll.Pad, Ice40.Rgb, Ice40.Spi,- Ice40.I2c,- Ice40.IO+ Ice40.Spram hs-source-dirs: src build-depends: base >=4.12 && <4.15, Cabal, interpolate,- clash-prelude >=1.2.5 && <1.4,+ clash-prelude >=1.2.5 && <1.5, ghc-typelits-natnormalise, ghc-typelits-extra, ghc-typelits-knownnat
src/Ice40/Osc.hs view
@@ -75,7 +75,7 @@ -> Clock dom' -- clkhf" , "template" : "//SB_HFOSC begin- SB_HFOSC #( .CLKHF_DIV(~ARG[2]) ) sb_hfosc_inst (+ SB_HFOSC #( .CLKHF_DIV(~ARG[2]) ) ~GENSYM[sb_hfosc_inst][0] ( .CLKHFEN (~ARG[3]), .CLKHFPU (~ARG[4]), .CLKHF (~RESULT)
+ src/Ice40/Pll/Core.hs view
@@ -0,0 +1,100 @@+{-|+Module : Ice40.Pll.Core+Description : Ice40 PLL hard IP primitive+Copyright : (c) David Cox, 2021+License : BSD 3-Clause+Maintainer : standardsemiconductor@gmail.com+PLL Core hard IP primitive from [Lattice Ice Technology Library](https://github.com/standardsemiconductor/VELDT-info/blob/master/SBTICETechnologyLibrary201708.pdf). The PLL core primitive should be used when the source clock of the PLL is driven by FPGA routing i.e. when the PLL source clock originates on the FPGA or is driven by an input pad the is not in the bottom IO bank (IO Bank 2).+-}+module Ice40.Pll.Core where++import Clash.Prelude+import Clash.Annotations.Primitive+import Data.String.Interpolate (i)+import Data.String.Interpolate.Util (unindent)++{-# ANN pllCorePrim (InlinePrimitive [Verilog] $ unindent [i|+ [ { "BlackBox" :+ { "name" : "Ice40.Pll.Core.pllCorePrim"+ , "kind" : "Declaration"+ , "type" :+ "pllCorePrim+ :: KnownDomain dom' -- ARG[0]+ => BitVector 7 -- ARG[1] divf+ -> BitVector 3 -- ARG[2] divq+ -> BitVector 4 -- ARG[3] divr+ -> String -- ARG[4] feedbackPath+ -> BitVector 3 -- ARG[5] filterRange+ -> String -- ARG[6] pllOutSelect+ -> String -- ARG[7] delayAdjustmentModeFeedback+ -> String -- ARG[8] delayAdjustmentModeRelative+ -> BitVector 4 -- ARG[9] fdaFeedback+ -> BitVector 4 -- ARG[10] fdaRelative+ -> Bit -- ARG[11] enableIceGate+ -> Clock dom -- ARG[12] referenceClk+ -> Signal dom (BitVector 8) -- ARG[13] dynamicDelay+ -> Signal dom Bit -- ARG[14] resetb+ -> Signal dom Bit -- ARG[15] bypass+ -> ( Clock dom' -- pllOutCore+ , Clock dom' -- globalOutCore+ , Signal dom' Bool -- lock+ )"+ , "template" :+ "//SB_PLL40_CORE begin+ wire ~GENSYM[pllOutCore][0];+ wire ~GENSYM[globalOutCore][1];+ wire ~GENSYM[lock][2];+ + SB_PLL40_CORE #(+ .DIVF ( ~ARG[1] ),+ .DIVQ ( ~ARG[2] ),+ .DIVR ( ~ARG[3] ),+ .FEEDBACK_PATH ( ~ARG[4] ),+ .FILTER_RANGE ( ~ARG[5] ),+ .PLLOUT_SELECT ( ~ARG[6] ),+ .DELAY_ADJUSTMENT_MODE_FEEDBACK ( ~ARG[7] ),+ .DELAY_ADJUSTMENT_MODE_RELATIVE ( ~ARG[8] ),+ .FDA_FEEDBACK ( ~ARG[9] ),+ .FDA_RELATIVE ( ~ARG[10] ),+ .ENABLE_ICEGATE ( ~ARG[11] )+ ) ~GENSYM[sb_pll40_core_inst][3] (+ .REFERENCECLK ( ~ARG[12] ),+ .DYNAMICDELAY ( ~ARG[13] ),+ .RESETB ( ~ARG[14] ),+ .BYPASS ( ~ARG[15] ),+ + .PLLOUTCORE ( ~SYM[0] ),+ .PLLOUTGLOBAL ( ~SYM[1] ),+ .LOCK ( ~SYM[2] )+ );++ assign ~RESULT = { ~SYM[0], ~SYM[1], ~SYM[2] };+ // SB_PLL40_CORE end"+ }+ }+ ]+ |]) #-}++{-# NOINLINE pllCorePrim #-}+pllCorePrim + :: KnownDomain dom' -- ARG[0]+ => BitVector 7 -- ^ divf+ -> BitVector 3 -- ^ divq+ -> BitVector 4 -- ^ divr+ -> String -- ^ feedbackPath+ -> BitVector 3 -- ^ filterRange+ -> String -- ^ pllOutSelect+ -> String -- ^ delayAdjustmentModeFeedback+ -> String -- ^ delayAdjustmentModeRelative+ -> BitVector 4 -- ^ fdaFeedback+ -> BitVector 4 -- ^ fdaRelative+ -> Bit -- ^ enableIceGate+ -> Clock dom -- ^ referenceClk+ -> Signal dom (BitVector 8) -- ^ dynamicDelay+ -> Signal dom Bit -- ^ resetb+ -> Signal dom Bit -- ^ bypass+ -> ( Clock dom' -- pllOutCore+ , Clock dom' -- globalOutCore+ , Signal dom' Bool -- lock+ ) -- ^ (pllOutCore, globalOutCore, lock)+pllCorePrim !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ = (clockGen, clockGen, pure True)
+ src/Ice40/Pll/Pad.hs view
@@ -0,0 +1,101 @@+{-|+Module : Ice40.Pll.Pad+Description : Ice40 PLL Pad hard IP primitive+Copyright : (c) David Cox, 2021+License : BSD 3-Clause+Maintainer : standardsemiconductor@gmail.com++PLL Pad hard IP primitive from [Lattice Ice Technology Library](https://github.com/standardsemiconductor/VELDT-info/blob/master/SBTICETechnologyLibrary201708.pdf). The PLL pad primitive should be used when the source clock of the PLL is driven by an input pad that is located in the bottom IO bank (IO Bank 2) or the top IO bank (IO Bank 0), and the source clock is not required inside the FPGA.+-}++module Ice40.Pll.Pad where++import Clash.Prelude+import Clash.Annotations.Primitive+import Data.String.Interpolate (i)+import Data.String.Interpolate.Util (unindent)++{-# ANN pllPadPrim (InlinePrimitive [Verilog] $ unindent [i|+ [ { "BlackBox" :+ { "name" : "Ice40.Pll.Pad.pllPadPrim"+ , "kind" : "Declaration"+ , "type" :+ "pllPadPrim+ :: KnownDomain dom' -- ARG[0]+ -> BitVector 7 -- ARG[1] divf+ -> BitVector 3 -- ARG[2] divq+ -> BitVector 4 -- ARG[3] divr+ -> String -- ARG[4] feedbackPath+ -> BitVector 3 -- ARG[5] filterRange+ -> String -- ARG[6] pllOutSelect+ -> String -- ARG[7] delayAdjustmentModeFeedback+ -> String -- ARG[8] delayAdjustmentModeRelative+ -> BitVector 4 -- ARG[9] fdaFeedback+ -> BitVector 4 -- ARG[10] fdaRelative+ -> Bit -- ARG[11] enableIceGate+ -> Clock dom -- ARG[12] packagePin+ -> Signal dom (BitVector 8) -- ARG[13] dynamicDelay+ -> Signal dom Bit -- ARG[14] resetb+ -> Signal dom Bit -- ARG[15] bypass+ -> ( Clock dom' -- pllOutCore+ , Clock dom' -- globalOutCore+ , Signal dom' Bool -- lock+ )"+ , "template" :+ "//SB_PLL40_PAD begin+ wire ~GENSYM[pllOutCore][0];+ wire ~GENSYM[globalOutCore][1];+ wire ~GENSYM[lock][2];++ SB_PLL40_PAD #(+ .DIVF (~ARG[1] ),+ .DIVQ (~ARG[2] ),+ .DIVR (~ARG[3] ),+ .FEEDBACK_PATH (~ARG[4] ),+ .FILTER_RANGE (~ARG[5] ),+ .PLLOUT_SELECT (~ARG[6] ),+ .DELAY_ADJUSTMENT_MODE_FEEDBACK (~ARG[7] ),+ .DELAY_ADJUSTMENT_MODE_RELATIVE (~ARG[8] ),+ .FDA_FEEDBACK (~ARG[9] ),+ .FDA_RELATIVE (~ARG[10]),+ .ENABLE_ICEGATE (~ARG[11])+ ) ~GENSYM[sb_pll40_core_inst][3] (+ .PACKAGEPIN (~ARG[12]),+ .DYNAMICDELAY (~ARG[13]),+ .RESETB (~ARG[14]),+ .BYPASS (~ARG[15]),+ .PLLOUTCORE (~SYM[0] ),+ .PLLOUTGLOBAL (~SYM[1] ),+ .LOCK (~SYM[2] )+ );++ assign ~RESULT = { ~SYM[0], ~SYM[1], ~SYM[2] };+ // SB_PLL40_PAD end"+ }+ }+ ]+ |]) #-}++{-# NOINLINE pllPadPrim #-}+pllPadPrim + :: KnownDomain dom' -- ARG[0]+ => BitVector 7 -- ^ divf+ -> BitVector 3 -- ^ divq+ -> BitVector 4 -- ^ divr+ -> String -- ^ feedbackPath+ -> BitVector 3 -- ^ filterRange+ -> String -- ^ pllOutSelect+ -> String -- ^ delayAdjustmentModeFeedback+ -> String -- ^ delayAdjustmentModeRelative+ -> BitVector 4 -- ^ fdaFeedback+ -> BitVector 4 -- ^ fdaRelative+ -> Bit -- ^ enableIceGate+ -> Clock dom -- ^ packagePin+ -> Signal dom (BitVector 8) -- ^ dynamicDelay+ -> Signal dom Bit -- ^ resetb+ -> Signal dom Bit -- ^ bypass+ -> ( Clock dom' -- pllOutCore+ , Clock dom' -- globalOutCore+ , Signal dom' Bool -- lock+ ) -- ^ (pllOutCore, globalOutCore, lock)+pllPadPrim !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ !_ = (clockGen, clockGen, pure True)