packages feed

gpu-vulkan 0.1.0.159 → 0.1.0.160

raw patch · 10 files changed

+201/−19 lines, 10 filesPVP: minor bump suggested

API additions: PVP suggests at least a minor version bump

API changes (from Hackage documentation)

+ Gpu.Vulkan: AccessFlagBits2 :: Word64 -> AccessFlagBits2
+ Gpu.Vulkan: DependencyInfo :: M mn -> DependencyFlags -> PL Barrier2 mbas -> PL (U5 MemoryBarrier2) bmbas -> PL (U5 MemoryBarrier2) imbas -> DependencyInfo (mn :: Maybe Type) (mbas :: [Maybe Type]) (bmbas :: [(Maybe Type, Type, Type, Symbol, O)]) (imbas :: [(Maybe Type, Type, Type, Symbol, Format)])
+ Gpu.Vulkan: [dependencyInfoBufferMemoryBarriers] :: DependencyInfo (mn :: Maybe Type) (mbas :: [Maybe Type]) (bmbas :: [(Maybe Type, Type, Type, Symbol, O)]) (imbas :: [(Maybe Type, Type, Type, Symbol, Format)]) -> PL (U5 MemoryBarrier2) bmbas
+ Gpu.Vulkan: [dependencyInfoDependencyFlags] :: DependencyInfo (mn :: Maybe Type) (mbas :: [Maybe Type]) (bmbas :: [(Maybe Type, Type, Type, Symbol, O)]) (imbas :: [(Maybe Type, Type, Type, Symbol, Format)]) -> DependencyFlags
+ Gpu.Vulkan: [dependencyInfoImageMemoryBarriers] :: DependencyInfo (mn :: Maybe Type) (mbas :: [Maybe Type]) (bmbas :: [(Maybe Type, Type, Type, Symbol, O)]) (imbas :: [(Maybe Type, Type, Type, Symbol, Format)]) -> PL (U5 MemoryBarrier2) imbas
+ Gpu.Vulkan: [dependencyInfoMemoryBarriers] :: DependencyInfo (mn :: Maybe Type) (mbas :: [Maybe Type]) (bmbas :: [(Maybe Type, Type, Type, Symbol, O)]) (imbas :: [(Maybe Type, Type, Type, Symbol, Format)]) -> PL Barrier2 mbas
+ Gpu.Vulkan: [dependencyInfoNext] :: DependencyInfo (mn :: Maybe Type) (mbas :: [Maybe Type]) (bmbas :: [(Maybe Type, Type, Type, Symbol, O)]) (imbas :: [(Maybe Type, Type, Type, Symbol, Format)]) -> M mn
+ Gpu.Vulkan: data DependencyInfo (mn :: Maybe Type) (mbas :: [Maybe Type]) (bmbas :: [(Maybe Type, Type, Type, Symbol, O)]) (imbas :: [(Maybe Type, Type, Type, Symbol, Format)])
+ Gpu.Vulkan: newtype AccessFlagBits2
+ Gpu.Vulkan: pattern Access2AccelerationStructureReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2AccelerationStructureReadBitNv :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2AccelerationStructureWriteBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2AccelerationStructureWriteBitNv :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ColorAttachmentReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ColorAttachmentReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ColorAttachmentReadNoncoherentBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ColorAttachmentWriteBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ColorAttachmentWriteBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2CommandPreprocessReadBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2CommandPreprocessReadBitNv :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2CommandPreprocessWriteBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2CommandPreprocessWriteBitNv :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ConditionalRenderingReadBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2DepthStencilAttachmentReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2DepthStencilAttachmentReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2DepthStencilAttachmentWriteBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2DepthStencilAttachmentWriteBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2DescriptorBufferReadBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2FragmentDensityMapReadBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2FragmentShadingRateAttachmentReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2HostReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2HostReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2HostWriteBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2HostWriteBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2IndexReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2IndexReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2IndirectCommandReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2IndirectCommandReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2InputAttachmentReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2InputAttachmentReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2InvocationMaskReadBitHuawei :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2MemoryReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2MemoryReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2MemoryWriteBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2MemoryWriteBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2MicromapReadBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2MicromapWriteBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2None :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2NoneKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2OpticalFlowReadBitNv :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2OpticalFlowWriteBitNv :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderBindingTableReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderSampledReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderSampledReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderStorageReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderStorageReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderStorageWriteBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderStorageWriteBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderWriteBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShaderWriteBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2ShadingRateImageReadBitNv :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2TransferReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2TransferReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2TransferWriteBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2TransferWriteBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2TransformFeedbackCounterReadBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2TransformFeedbackCounterWriteBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2TransformFeedbackWriteBitExt :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2UniformReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2UniformReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2VertexAttributeReadBit :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2VertexAttributeReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2VideoDecodeReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2VideoDecodeWriteBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2VideoEncodeReadBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern Access2VideoEncodeWriteBitKhr :: AccessFlagBits2
+ Gpu.Vulkan: pattern AccessFlags2Zero :: AccessFlagBits2
+ Gpu.Vulkan: type AccessFlags2 = AccessFlagBits2
+ Gpu.Vulkan: unAccessFlagBits2 :: AccessFlagBits2 -> Word64
+ Gpu.Vulkan.Buffer: MemoryBarrier2 :: M mn -> StageFlags2 -> AccessFlags2 -> StageFlags2 -> AccessFlags2 -> Index -> Index -> Binded sm sb nm objs -> MemoryBarrier2 (mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: O)
+ Gpu.Vulkan.Buffer: [memoryBarrier2Buffer] :: MemoryBarrier2 (mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: O) -> Binded sm sb nm objs
+ Gpu.Vulkan.Buffer: [memoryBarrier2DstAccessMask] :: MemoryBarrier2 (mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: O) -> AccessFlags2
+ Gpu.Vulkan.Buffer: [memoryBarrier2DstQueueFamilyIndex] :: MemoryBarrier2 (mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: O) -> Index
+ Gpu.Vulkan.Buffer: [memoryBarrier2DstStageMask] :: MemoryBarrier2 (mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: O) -> StageFlags2
+ Gpu.Vulkan.Buffer: [memoryBarrier2Next] :: MemoryBarrier2 (mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: O) -> M mn
+ Gpu.Vulkan.Buffer: [memoryBarrier2SrcAccessMask] :: MemoryBarrier2 (mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: O) -> AccessFlags2
+ Gpu.Vulkan.Buffer: [memoryBarrier2SrcQueueFamilyIndex] :: MemoryBarrier2 (mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: O) -> Index
+ Gpu.Vulkan.Buffer: [memoryBarrier2SrcStageMask] :: MemoryBarrier2 (mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: O) -> StageFlags2
+ Gpu.Vulkan.Buffer: class MemoryBarrier2ListToMiddle (nsmsbnmobjs :: [(Maybe Type, Type, Type, Symbol, O)])
+ Gpu.Vulkan.Buffer: data MemoryBarrier2 (mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: O)
+ Gpu.Vulkan.Cmd: pipelineBarrier2 :: forall (mn :: Maybe Type) (mbas :: [Maybe Type]) (bmbas :: [(Maybe Type, Type, Type, Symbol, O)]) (imbas :: [(Maybe Type, Type, Type, Symbol, Format)]) scb. (WithPoked (M mn), ToListWithCCpsM' WithPoked M mbas, Length mbas, ToListWithCCpsM' WithPoked M (M0_5 bmbas), Length (M0_5 bmbas), ToListWithCCpsM' WithPoked M (M0_5 imbas), Length (M0_5 imbas), MemoryBarrier2ListToMiddle bmbas, MemoryBarrier2ListToMiddle imbas) => C scb -> DependencyInfo mn mbas bmbas imbas -> IO ()
+ Gpu.Vulkan.Image: MemoryBarrier2 :: M mn -> StageFlags2 -> AccessFlags2 -> StageFlags2 -> AccessFlags2 -> Layout -> Layout -> Index -> Index -> Binded sm si nm fmt -> SubresourceRange -> MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format)
+ Gpu.Vulkan.Image: [memoryBarrier2DstAccessMask] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> AccessFlags2
+ Gpu.Vulkan.Image: [memoryBarrier2DstQueueFamilyIndex] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> Index
+ Gpu.Vulkan.Image: [memoryBarrier2DstStageMask] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> StageFlags2
+ Gpu.Vulkan.Image: [memoryBarrier2Image] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> Binded sm si nm fmt
+ Gpu.Vulkan.Image: [memoryBarrier2NewLayout] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> Layout
+ Gpu.Vulkan.Image: [memoryBarrier2Next] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> M mn
+ Gpu.Vulkan.Image: [memoryBarrier2OldLayout] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> Layout
+ Gpu.Vulkan.Image: [memoryBarrier2SrcAccessMask] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> AccessFlags2
+ Gpu.Vulkan.Image: [memoryBarrier2SrcQueueFamilyIndex] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> Index
+ Gpu.Vulkan.Image: [memoryBarrier2SrcStageMask] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> StageFlags2
+ Gpu.Vulkan.Image: [memoryBarrier2SubresourceRange] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> SubresourceRange
+ Gpu.Vulkan.Image: class MemoryBarrier2ListToMiddle (mbargs :: [(Maybe Type, Type, Type, Symbol, Format)])
+ Gpu.Vulkan.Image: data MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format)
+ Gpu.Vulkan.Image.Internal: MemoryBarrier2 :: M mn -> StageFlags2 -> AccessFlags2 -> StageFlags2 -> AccessFlags2 -> Layout -> Layout -> Index -> Index -> Binded sm si nm fmt -> SubresourceRange -> MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format)
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2DstAccessMask] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> AccessFlags2
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2DstQueueFamilyIndex] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> Index
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2DstStageMask] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> StageFlags2
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2Image] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> Binded sm si nm fmt
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2NewLayout] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> Layout
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2Next] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> M mn
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2OldLayout] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> Layout
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2SrcAccessMask] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> AccessFlags2
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2SrcQueueFamilyIndex] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> Index
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2SrcStageMask] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> StageFlags2
+ Gpu.Vulkan.Image.Internal: [memoryBarrier2SubresourceRange] :: MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format) -> SubresourceRange
+ Gpu.Vulkan.Image.Internal: class MemoryBarrier2ListToMiddle (mbargs :: [(Maybe Type, Type, Type, Symbol, Format)])
+ Gpu.Vulkan.Image.Internal: data MemoryBarrier2 (mn :: Maybe Type) sm si (nm :: Symbol) (fmt :: Format)
+ Gpu.Vulkan.Image.Internal: instance Gpu.Vulkan.Image.Internal.MemoryBarrier2ListToMiddle '[]
+ Gpu.Vulkan.Image.Internal: instance Gpu.Vulkan.Image.Internal.MemoryBarrier2ListToMiddle mbargs => Gpu.Vulkan.Image.Internal.MemoryBarrier2ListToMiddle ('(mn, si, sm, nm, fmt) : mbargs)
+ Gpu.Vulkan.Image.Internal: memoryBarrier2ListToMiddle :: MemoryBarrier2ListToMiddle mbargs => PL (U5 MemoryBarrier2) mbargs -> PL MemoryBarrier2 (M0_5 mbargs)
+ Gpu.Vulkan.Memory: Barrier2 :: M mn -> StageFlags2 -> AccessFlags2 -> StageFlags2 -> AccessFlags2 -> Barrier2 (mn :: Maybe Type)
+ Gpu.Vulkan.Memory: [barrier2DstAccessMask] :: Barrier2 (mn :: Maybe Type) -> AccessFlags2
+ Gpu.Vulkan.Memory: [barrier2DstStageMask] :: Barrier2 (mn :: Maybe Type) -> StageFlags2
+ Gpu.Vulkan.Memory: [barrier2Next] :: Barrier2 (mn :: Maybe Type) -> M mn
+ Gpu.Vulkan.Memory: [barrier2SrcAccessMask] :: Barrier2 (mn :: Maybe Type) -> AccessFlags2
+ Gpu.Vulkan.Memory: [barrier2SrcStageMask] :: Barrier2 (mn :: Maybe Type) -> StageFlags2
+ Gpu.Vulkan.Memory: data Barrier2 (mn :: Maybe Type)
+ Gpu.Vulkan.Pipeline: StageFlagBits2 :: Word64 -> StageFlagBits2
+ Gpu.Vulkan.Pipeline: newtype StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2AccelerationStructureBuildBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2AccelerationStructureBuildBitNv :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2AccelerationStructureCopyBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2AllCommandsBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2AllCommandsBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2AllGraphicsBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2AllGraphicsBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2AllTransferBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2AllTransferBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2BlitBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2BlitBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2BottomOfPipeBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2BottomOfPipeBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ClearBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ClearBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ClusterCullingShaderBitHuawei :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ColorAttachmentOutputBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ColorAttachmentOutputBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2CommandPreprocessBitExt :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2CommandPreprocessBitNv :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ComputeShaderBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ComputeShaderBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ConditionalRenderingBitExt :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2CopyBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2CopyBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2DrawIndirectBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2DrawIndirectBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2EarlyFragmentTestsBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2EarlyFragmentTestsBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2FragmentDensityProcessBitExt :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2FragmentShaderBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2FragmentShaderBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2FragmentShadingRateAttachmentBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2GeometryShaderBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2GeometryShaderBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2HostBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2HostBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2IndexInputBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2IndexInputBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2InvocationMaskBitHuawei :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2LateFragmentTestsBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2LateFragmentTestsBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2MeshShaderBitExt :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2MeshShaderBitNv :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2MicromapBuildBitExt :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2None :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2NoneKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2OpticalFlowBitNv :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2PreRasterizationShadersBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2PreRasterizationShadersBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2RayTracingShaderBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2RayTracingShaderBitNv :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ResolveBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ResolveBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2ShadingRateImageBitNv :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2SubpassShaderBitHuawei :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2SubpassShadingBitHuawei :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TaskShaderBitExt :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TaskShaderBitNv :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TessellationControlShaderBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TessellationControlShaderBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TessellationEvaluationShaderBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TessellationEvaluationShaderBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TopOfPipeBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TopOfPipeBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TransferBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TransferBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2TransformFeedbackBitExt :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2VertexAttributeInputBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2VertexAttributeInputBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2VertexInputBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2VertexInputBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2VertexShaderBit :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2VertexShaderBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2VideoDecodeBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern Stage2VideoEncodeBitKhr :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: pattern StageFlags2Zero :: StageFlagBits2
+ Gpu.Vulkan.Pipeline: type StageFlags2 = StageFlagBits2
+ Gpu.Vulkan.Pipeline: unStageFlagBits2 :: StageFlagBits2 -> Word64

Files

gpu-vulkan.cabal view
@@ -5,7 +5,7 @@ -- see: https://github.com/sol/hpack  name:           gpu-vulkan-version:        0.1.0.159+version:        0.1.0.160 synopsis:       Vulkan library description:    Please see the README on GitHub at <https://github.com/YoshikuniJujo/gpu-vulkan#readme> category:       GPU
src/Gpu/Vulkan.hs view
@@ -82,6 +82,8 @@  	Size(..), +	DependencyInfo(..),+ 	-- * ENUM  	module Gpu.Vulkan.Enum,
src/Gpu/Vulkan/Buffer.hs view
@@ -32,6 +32,7 @@ 	-- * MEMORY BARRIER  	MemoryBarrier(..), MemoryBarrierListToMiddle,+	MemoryBarrier2(..), MemoryBarrier2ListToMiddle,  	-- * UNSAFE 
src/Gpu/Vulkan/Buffer/Internal.hs view
@@ -37,6 +37,7 @@ 	-- * MEMORY BARRIER  	MemoryBarrier(..), MemoryBarrierListToMiddle(..),+	MemoryBarrier2(..), MemoryBarrier2ListToMiddle(..),  	-- * UNSAFE @@ -78,6 +79,8 @@ import Control.Concurrent.STM.TSem import Data.Map qualified as Map +import qualified Gpu.Vulkan.Pipeline as Pipeline+ data CreateInfo mn objs = CreateInfo { 	createInfoNext :: TMaybe.M mn, 	createInfoFlags :: CreateFlags,@@ -326,20 +329,18 @@ 	MemoryBarrier n sm sb nm obj -> M.MemoryBarrier n memoryBarrierToMiddle MemoryBarrier { 	memoryBarrierNext = mnxt,-	memoryBarrierSrcAccessMask = sam,-	memoryBarrierDstAccessMask = dam,+	memoryBarrierSrcAccessMask = sam, memoryBarrierDstAccessMask = dam, 	memoryBarrierSrcQueueFamilyIndex = sqfi, 	memoryBarrierDstQueueFamilyIndex = dqfi,-	memoryBarrierBuffer = Binded lns b :: Binded sm sb nm objs } =-	M.MemoryBarrier {-		M.memoryBarrierNext = mnxt,-		M.memoryBarrierSrcAccessMask = sam,-		M.memoryBarrierDstAccessMask = dam,-		M.memoryBarrierSrcQueueFamilyIndex = sqfi,-		M.memoryBarrierDstQueueFamilyIndex = dqfi,-		M.memoryBarrierBuffer = b,-		M.memoryBarrierOffset = ost,-		M.memoryBarrierSize = sz }+	memoryBarrierBuffer = Binded lns b } = M.MemoryBarrier {+	M.memoryBarrierNext = mnxt,+	M.memoryBarrierSrcAccessMask = sam,+	M.memoryBarrierDstAccessMask = dam,+	M.memoryBarrierSrcQueueFamilyIndex = sqfi,+	M.memoryBarrierDstQueueFamilyIndex = dqfi,+	M.memoryBarrierBuffer = b,+	M.memoryBarrierOffset = ost,+	M.memoryBarrierSize = sz } 	where (ost, sz) = VObj.offsetRange @obj @_ @0 0 lns  class MemoryBarrierListToMiddle nsmsbnmobjs where@@ -354,6 +355,49 @@ 	MemoryBarrierListToMiddle ('(mn, sm, sb, nm, obj) ': nsmsbnmobjs) where 	memoryBarrierListToMiddle (U5 mb :** mbs) = 		memoryBarrierToMiddle mb :** memoryBarrierListToMiddle mbs++data MemoryBarrier2 mn sm sb nm obj = forall objs . (+	VObj.OffsetRange obj objs 0, VObj.LengthOf obj objs ) =>+	MemoryBarrier2 {+		memoryBarrier2Next :: TMaybe.M mn,+		memoryBarrier2SrcStageMask :: Pipeline.StageFlags2,+		memoryBarrier2SrcAccessMask :: AccessFlags2,+		memoryBarrier2DstStageMask :: Pipeline.StageFlags2,+		memoryBarrier2DstAccessMask :: AccessFlags2,+		memoryBarrier2SrcQueueFamilyIndex :: QueueFamily.Index,+		memoryBarrier2DstQueueFamilyIndex :: QueueFamily.Index,+		memoryBarrier2Buffer :: Binded sm sb nm objs }++memoryBarrier2ToMiddle :: forall mn sm sb nm obj .+	MemoryBarrier2 mn sm sb nm obj -> M.MemoryBarrier2 mn+memoryBarrier2ToMiddle MemoryBarrier2 {+	memoryBarrier2Next = mnxt,+	memoryBarrier2SrcStageMask = ssm, memoryBarrier2SrcAccessMask = sam,+	memoryBarrier2DstStageMask = dsm, memoryBarrier2DstAccessMask = dam,+	memoryBarrier2SrcQueueFamilyIndex = sqfi,+	memoryBarrier2DstQueueFamilyIndex = dqfi,+	memoryBarrier2Buffer = Binded lns b } = M.MemoryBarrier2 {+	M.memoryBarrier2Next = mnxt,+	M.memoryBarrier2SrcStageMask = ssm, M.memoryBarrier2SrcAccessMask = sam,+	M.memoryBarrier2DstStageMask = dsm, M.memoryBarrier2DstAccessMask = dam,+	M.memoryBarrier2SrcQueueFamilyIndex = sqfi,+	M.memoryBarrier2DstQueueFamilyIndex = dqfi,+	M.memoryBarrier2Buffer = b,+	M.memoryBarrier2Offset = ost, M.memoryBarrier2Size = sz }+	where (ost, sz) = VObj.offsetRange @obj @_ @0 0 lns++class MemoryBarrier2ListToMiddle nsmsbnmobjs where+	memoryBarrier2ListToMiddle ::+		HeteroParList.PL (U5 MemoryBarrier2) nsmsbnmobjs ->+		HeteroParList.PL M.MemoryBarrier2 (TMapIndex.M0_5 nsmsbnmobjs)++instance MemoryBarrier2ListToMiddle '[] where+	memoryBarrier2ListToMiddle HeteroParList.Nil = HeteroParList.Nil++instance MemoryBarrier2ListToMiddle nsmsbnmobjs =>+	MemoryBarrier2ListToMiddle ('(mn, sm, sb, nm, obj) ': nsmsbnmobjs) where+	memoryBarrier2ListToMiddle (U5 mb :** mbs) =+		memoryBarrier2ToMiddle mb :** memoryBarrier2ListToMiddle mbs  data ImageCopy img inm = ImageCopy { 	imageCopyImageSubresource :: Image.M.SubresourceLayers,
+ src/Gpu/Vulkan/Buffer/Internal.hs-boot view
@@ -0,0 +1,25 @@+{-# LANGUAGE ImportQualifiedPost #-}+{-# LANGUAGE DataKinds #-}+{-# LANGUAGE KindSignatures #-}+{-# LANGUAGE RoleAnnotations #-}+{-# OPTIONS_GHC -Wall -fno-warn-tabs #-}++module Gpu.Vulkan.Buffer.Internal where++import GHC.TypeLits+import Data.Kind+import Data.TypeLevel.Tuple.Uncurry+import Data.TypeLevel.Tuple.MapIndex qualified as TMapIndex+import Data.HeteroParList qualified as HPList++import Gpu.Vulkan.Object qualified as VObj+import Gpu.Vulkan.Buffer.Middle qualified as M++type role MemoryBarrier2 nominal phantom phantom phantom nominal+data MemoryBarrier2+	(mn :: Maybe Type) sm sb (nm :: Symbol) (obj :: VObj.O)++class MemoryBarrier2ListToMiddle nsmsbnmobjs where+	memoryBarrier2ListToMiddle ::+		HPList.PL (U5 MemoryBarrier2) nsmsbnmobjs ->+		HPList.PL M.MemoryBarrier2 (TMapIndex.M0_5 nsmsbnmobjs)
src/Gpu/Vulkan/Cmd.hs view
@@ -43,7 +43,7 @@  -- * MEMORY DEPENDENCY -pipelineBarrier,+pipelineBarrier, pipelineBarrier2,  -- * QUERY @@ -66,12 +66,14 @@ import Data.TypeLevel.Tuple.Uncurry import Data.TypeLevel.Tuple.Index qualified as TIndex import Data.TypeLevel.Tuple.MapIndex qualified as TMapIndex+import qualified Data.HeteroParList as HPList import qualified Data.HeteroParList as HeteroParList import Data.HeteroParList (pattern (:**)) import Data.Word import Data.Int  import Gpu.Vulkan+import Gpu.Vulkan.Internal import Gpu.Vulkan.TypeEnum qualified as T  import qualified Gpu.Vulkan.CommandBuffer as CommandBuffer@@ -290,6 +292,19 @@ 	M.pipelineBarrier cb ssm dsm dfs mbs 		(Bffr.I.memoryBarrierListToMiddle bmbs) 		(Image.I.memoryBarrierListToMiddle imbs)++pipelineBarrier2 :: (+	WithPoked (TMaybe.M mn),+	HPList.ToListWithCCpsM' WithPoked TMaybe.M mbas, Length mbas,+	HPList.ToListWithCCpsM' WithPoked TMaybe.M (TMapIndex.M0_5 bmbas),+	Length (TMapIndex.M0_5 bmbas),+	HPList.ToListWithCCpsM' WithPoked TMaybe.M (TMapIndex.M0_5 imbas),+	Length (TMapIndex.M0_5 imbas),+	Bffr.I.MemoryBarrier2ListToMiddle bmbas,+	Image.I.MemoryBarrier2ListToMiddle imbas ) =>+	CommandBuffer.C scb -> DependencyInfo mn mbas bmbas imbas -> IO ()+pipelineBarrier2 (CommandBuffer.T.C cb) di =+	M.pipelineBarrier2 cb $ dependencyInfoToMiddle di  copyBufferToImage :: 	forall (algn :: Nat) img inms scb smb sbb bnm objs smi si inm .
src/Gpu/Vulkan/Image.hs view
@@ -25,7 +25,9 @@  	-- * MEMORY BARRIER -	MemoryBarrier(..), SubresourceRange(..), MemoryBarrierListToMiddle,+	MemoryBarrier(..), MemoryBarrierListToMiddle,+	MemoryBarrier2(..), MemoryBarrier2ListToMiddle,+	SubresourceRange(..),  	-- * BLIT 
src/Gpu/Vulkan/Image/Internal.hs view
@@ -26,8 +26,9 @@  	-- * MEMORY BARRIER -	MemoryBarrier(..), M.SubresourceRange(..),-	MemoryBarrierListToMiddle(..),+	MemoryBarrier(..), MemoryBarrierListToMiddle(..),+	MemoryBarrier2(..), MemoryBarrier2ListToMiddle(..),+	M.SubresourceRange(..),  	-- * BLIT @@ -48,6 +49,7 @@ import Data.TypeLevel.Tuple.MapIndex qualified as TMapIndex import Data.TypeLevel.Maybe qualified as TMaybe import Data.TypeLevel.ParMaybe qualified as TPMaybe+import qualified Data.HeteroParList as HPList import qualified Data.HeteroParList as HeteroParList import Data.HeteroParList (pattern (:**)) import Data.Word@@ -67,6 +69,8 @@ import qualified Gpu.Vulkan.Sample.Enum as Sample import qualified Gpu.Vulkan.Image.Enum as I +import qualified Gpu.Vulkan.Pipeline as Pipeline+ create :: ( 	WithPoked (TMaybe.M mn), T.FormatToValue fmt, 	AllocationCallbacks.ToMiddle mac ) =>@@ -176,6 +180,57 @@ 	MemoryBarrierListToMiddle ('(mn, si, sm, nm, fmt) ': mbargs) where 	memoryBarrierListToMiddle (U5 mb :** mbs) = 		memoryBarrierToMiddle mb :** memoryBarrierListToMiddle mbs++data MemoryBarrier2 mn sm si nm fmt = MemoryBarrier2 {+	memoryBarrier2Next :: TMaybe.M mn,+	memoryBarrier2SrcStageMask :: Pipeline.StageFlags2,+	memoryBarrier2SrcAccessMask :: AccessFlags2,+	memoryBarrier2DstStageMask :: Pipeline.StageFlags2,+	memoryBarrier2DstAccessMask :: AccessFlags2,+	memoryBarrier2OldLayout :: Layout, memoryBarrier2NewLayout :: Layout,+	memoryBarrier2SrcQueueFamilyIndex :: QueueFamily.Index,+	memoryBarrier2DstQueueFamilyIndex :: QueueFamily.Index,+	memoryBarrier2Image :: Binded sm si nm fmt,+	memoryBarrier2SubresourceRange :: M.SubresourceRange }++memoryBarrier2ToMiddle :: MemoryBarrier2 mn si sm nm fmt -> M.MemoryBarrier2 mn+memoryBarrier2ToMiddle MemoryBarrier2 {+	memoryBarrier2Next = mnxt,+	memoryBarrier2SrcStageMask = ssm,+	memoryBarrier2SrcAccessMask = sam,+	memoryBarrier2DstStageMask = dsm,+	memoryBarrier2DstAccessMask = dam,+	memoryBarrier2OldLayout = ol,+	memoryBarrier2NewLayout = nl,+	memoryBarrier2SrcQueueFamilyIndex = sqfi,+	memoryBarrier2DstQueueFamilyIndex = dqfi,+	memoryBarrier2Image = Binded img,+	memoryBarrier2SubresourceRange = srr } = M.MemoryBarrier2 {+	M.memoryBarrier2Next = mnxt,+	M.memoryBarrier2SrcStageMask = ssm,+	M.memoryBarrier2SrcAccessMask = sam,+	M.memoryBarrier2DstStageMask = dsm,+	M.memoryBarrier2DstAccessMask = dam,+	M.memoryBarrier2OldLayout = ol,+	M.memoryBarrier2NewLayout = nl,+	M.memoryBarrier2SrcQueueFamilyIndex = sqfi,+	M.memoryBarrier2DstQueueFamilyIndex = dqfi,+	M.memoryBarrier2Image = img,+	M.memoryBarrier2SubresourceRange = srr }++class MemoryBarrier2ListToMiddle+	(mbargs :: [(Maybe Type, Type, Type, Symbol, T.Format)])  where+	memoryBarrier2ListToMiddle ::+		HeteroParList.PL (U5 MemoryBarrier2) mbargs ->+		HeteroParList.PL M.MemoryBarrier2 (TMapIndex.M0_5 mbargs)++instance MemoryBarrier2ListToMiddle '[] where+	memoryBarrier2ListToMiddle HPList.Nil = HPList.Nil++instance  MemoryBarrier2ListToMiddle mbargs =>+	MemoryBarrier2ListToMiddle ('(mn, si, sm, nm, fmt) ': mbargs) where+	memoryBarrier2ListToMiddle (U5 mb :** mbs) =+		memoryBarrier2ToMiddle mb :** memoryBarrier2ListToMiddle mbs  data CreateInfo mn (fmt :: T.Format) = CreateInfo { 	createInfoNext :: TMaybe.M mn,
src/Gpu/Vulkan/Internal.hs view
@@ -80,24 +80,33 @@  	-- * OTHERS -	M.Size(..)+	M.Size(..), +	DependencyInfo(..), dependencyInfoToMiddle+ 	) where  import Foreign.Storable.PeekPoke import Data.Kind import Data.TypeLevel.Maybe qualified as TMaybe import Data.TypeLevel.Tuple.Uncurry+import Data.TypeLevel.Tuple.MapIndex qualified as TMapIndex import Data.HeteroParList qualified as HeteroParList+import Data.HeteroParList qualified as HPList import Data.HeteroParList (pattern (:**)) import Data.Text qualified as T  import qualified Gpu.Vulkan.Middle as M+import Gpu.Vulkan.Enum import qualified Gpu.Vulkan.Semaphore.Type as Semaphore import qualified Gpu.Vulkan.Semaphore.Middle as Semaphore.M import qualified Gpu.Vulkan.CommandBuffer.Type as CommandBuffer import qualified Gpu.Vulkan.Pipeline.Enum as Pipeline +import Gpu.Vulkan.Memory.Middle qualified as Memory.M+import {-# SOURCE #-} Gpu.Vulkan.Buffer.Internal qualified as Buffer+import Gpu.Vulkan.Image.Internal qualified as Image+ data SubmitInfo n sss ss ssss = SubmitInfo { 	submitInfoNext :: TMaybe.M n, 	submitInfoWaitSemaphoreDstStageMasks ::@@ -200,3 +209,32 @@  layerKhronosValidation :: LayerName layerKhronosValidation = LayerName "VK_LAYER_KHRONOS_validation"++data DependencyInfo mn mbas bmbas imbas = DependencyInfo {+	dependencyInfoNext :: TMaybe.M mn,+	dependencyInfoDependencyFlags :: DependencyFlags,+	dependencyInfoMemoryBarriers :: HPList.PL Memory.M.Barrier2 mbas,+	dependencyInfoBufferMemoryBarriers ::+		HPList.PL (U5 Buffer.MemoryBarrier2) bmbas,+	dependencyInfoImageMemoryBarriers ::+		HPList.PL (U5 Image.MemoryBarrier2) imbas }++dependencyInfoToMiddle :: (+	Buffer.MemoryBarrier2ListToMiddle bmbas,+	Image.MemoryBarrier2ListToMiddle imbas ) =>+	DependencyInfo mn mbas bmbas imbas ->+	M.DependencyInfo mn mbas (TMapIndex.M0_5 bmbas) (TMapIndex.M0_5 imbas)+dependencyInfoToMiddle DependencyInfo {+	dependencyInfoNext = mnxt,+	dependencyInfoDependencyFlags = fs,+	dependencyInfoMemoryBarriers = mbs,+	dependencyInfoBufferMemoryBarriers = bmbs,+	dependencyInfoImageMemoryBarriers = imbs+	} = M.DependencyInfo {+	M.dependencyInfoNext = mnxt,+	M.dependencyInfoDependencyFlags = fs,+	M.dependencyInfoMemoryBarriers = mbs,+	M.dependencyInfoBufferMemoryBarriers =+		Buffer.memoryBarrier2ListToMiddle bmbs,+	M.dependencyInfoImageMemoryBarriers =+		Image.memoryBarrier2ListToMiddle imbs }
src/Gpu/Vulkan/Memory.hs view
@@ -44,7 +44,7 @@  	-- * BARRIER -	M.Barrier(..),+	M.Barrier(..), M.Barrier2(..),  	-- * OTHERS