diff --git a/gpu-vulkan-middle.cabal b/gpu-vulkan-middle.cabal --- a/gpu-vulkan-middle.cabal +++ b/gpu-vulkan-middle.cabal @@ -5,7 +5,7 @@ -- see: https://github.com/sol/hpack name: gpu-vulkan-middle -version: 0.1.0.64 +version: 0.1.0.65 synopsis: Medium wrapper for Vulkan API description: Please see the README on GitHub at category: GPU diff --git a/src/Gpu/Vulkan/Buffer/Middle.hs b/src/Gpu/Vulkan/Buffer/Middle.hs --- a/src/Gpu/Vulkan/Buffer/Middle.hs +++ b/src/Gpu/Vulkan/Buffer/Middle.hs @@ -18,6 +18,6 @@ -- * MEMORY BARRIER - MemoryBarrier(..) ) where + MemoryBarrier(..), MemoryBarrier2(..) ) where import Gpu.Vulkan.Buffer.Middle.Internal diff --git a/src/Gpu/Vulkan/Buffer/Middle/Internal.hs-boot b/src/Gpu/Vulkan/Buffer/Middle/Internal.hs-boot new file mode 100644 --- /dev/null +++ b/src/Gpu/Vulkan/Buffer/Middle/Internal.hs-boot @@ -0,0 +1,17 @@ +{-# LANGUAGE ImportQualifiedPost #-} +{-# LANGUAGE KindSignatures #-} +{-# LANGUAGE FlexibleContexts #-} +{-# LANGUAGE RoleAnnotations #-} + +module Gpu.Vulkan.Buffer.Middle.Internal where + +import Foreign.Storable.PeekPoke +import Data.Kind +import Data.TypeLevel.Maybe qualified as TMaybe +import Gpu.Vulkan.Buffer.Core qualified as C + +type role MemoryBarrier2 nominal +data MemoryBarrier2 (mn :: Maybe Type) + +memoryBarrier2ToCore :: WithPoked (TMaybe.M mn) => + MemoryBarrier2 mn -> (C.MemoryBarrier2 -> IO a) -> IO () diff --git a/src/Gpu/Vulkan/Buffer/Middle/Internal.hsc b/src/Gpu/Vulkan/Buffer/Middle/Internal.hsc --- a/src/Gpu/Vulkan/Buffer/Middle/Internal.hsc +++ b/src/Gpu/Vulkan/Buffer/Middle/Internal.hsc @@ -1,6 +1,7 @@ {-# LANGUAGE ImportQualifiedPost #-} {-# LANGUAGE BlockArguments #-} {-# LANGUAGE MonoLocalBinds #-} +{-# LANGUAGE DataKinds #-} {-# LANGUAGE KindSignatures #-} {-# LANGUAGE FlexibleContexts, UndecidableInstances #-} {-# LANGUAGE PatternSynonyms, ViewPatterns #-} @@ -13,6 +14,7 @@ ImageCopy(..), imageCopyToCore, MemoryBarrier(..), memoryBarrierToCore', + MemoryBarrier2(..), memoryBarrier2ToCore, C.Copy, pattern C.Copy, C.copySrcOffset, C.copyDstOffset, C.copySize ) where @@ -45,6 +47,8 @@ import qualified Gpu.Vulkan.QueueFamily.EnumManual as QueueFamily import qualified Gpu.Vulkan.Image.Middle.Internal as Image +import qualified Gpu.Vulkan.Pipeline.Enum as Pipeline + #include data CreateInfo (mn :: Maybe Type) = CreateInfo { @@ -116,7 +120,7 @@ memoryBarrierOffset :: Device.Size, memoryBarrierSize :: Device.Size } -deriving instance Show (TMaybe.M mn) => Show (MemoryBarrier mn) +deriving instance Show (TMaybe.M mn) => Show (MemoryBarrier2 mn) memoryBarrierToCore' :: WithPoked (TMaybe.M mn) => MemoryBarrier mn -> (C.MemoryBarrier -> IO a) -> IO () @@ -140,6 +144,47 @@ C.memoryBarrierBuffer = b, C.memoryBarrierOffset = ofst, C.memoryBarrierSize = sz } + +data MemoryBarrier2 mn = MemoryBarrier2 { + memoryBarrier2Next :: TMaybe.M mn, + memoryBarrier2SrcStageMask :: Pipeline.StageFlags2, + memoryBarrier2SrcAccessMask :: AccessFlags2, + memoryBarrier2DstStageMask :: Pipeline.StageFlags2, + memoryBarrier2DstAccessMask :: AccessFlags2, + memoryBarrier2SrcQueueFamilyIndex :: QueueFamily.Index, + memoryBarrier2DstQueueFamilyIndex :: QueueFamily.Index, + memoryBarrier2Buffer :: B, + memoryBarrier2Offset :: Device.Size, + memoryBarrier2Size :: Device.Size } + +deriving instance Show (TMaybe.M mn) => Show (MemoryBarrier mn) + +memoryBarrier2ToCore :: WithPoked (TMaybe.M mn) => + MemoryBarrier2 mn -> (C.MemoryBarrier2 -> IO a) -> IO () +memoryBarrier2ToCore MemoryBarrier2 { + memoryBarrier2Next = mnxt, + memoryBarrier2SrcStageMask = Pipeline.StageFlagBits2 ssm, + memoryBarrier2SrcAccessMask = AccessFlagBits2 sam, + memoryBarrier2DstStageMask = Pipeline.StageFlagBits2 dsm, + memoryBarrier2DstAccessMask = AccessFlagBits2 dam, + memoryBarrier2SrcQueueFamilyIndex = QueueFamily.Index sqfi, + memoryBarrier2DstQueueFamilyIndex = QueueFamily.Index dqfi, + memoryBarrier2Buffer = B b, + memoryBarrier2Offset = Device.Size ofst, + memoryBarrier2Size = Device.Size sz } f = + withPoked' mnxt \pnxt -> withPtrS pnxt \(castPtr -> pnxt') -> + f C.MemoryBarrier2 { + C.memoryBarrier2SType = (), + C.memoryBarrier2PNext = pnxt', + C.memoryBarrier2SrcStageMask = ssm, + C.memoryBarrier2SrcAccessMask = sam, + C.memoryBarrier2DstStageMask = dsm, + C.memoryBarrier2DstAccessMask = dam, + C.memoryBarrier2SrcQueueFamilyIndex = sqfi, + C.memoryBarrier2DstQueueFamilyIndex = dqfi, + C.memoryBarrier2Buffer = b, + C.memoryBarrier2Offset = ofst, + C.memoryBarrier2Size = sz } data ImageCopy = ImageCopy { imageCopyBufferOffset :: Device.Size, diff --git a/src/Gpu/Vulkan/Cmd/Middle.hs b/src/Gpu/Vulkan/Cmd/Middle.hs --- a/src/Gpu/Vulkan/Cmd/Middle.hs +++ b/src/Gpu/Vulkan/Cmd/Middle.hs @@ -34,7 +34,7 @@ -- * MEMORY DEPENDENCY - pipelineBarrier, + pipelineBarrier, pipelineBarrier2, -- * QUERY @@ -44,6 +44,7 @@ import Foreign.Marshal.Alloc import Foreign.Marshal.Array +import Foreign.Storable import Foreign.Storable.PeekPoke (WithPoked) import Foreign.Storable.HeteroList import Control.Arrow @@ -51,6 +52,8 @@ import Control.Monad.Trans import Control.Monad.Cont import Data.TypeLevel.Maybe qualified as TMaybe +import Data.TypeLevel.List qualified as TList +import Data.HeteroParList qualified as HPList import Data.HeteroParList qualified as HeteroParList import Data.Word import Data.Int @@ -219,6 +222,18 @@ C.pipelineBarrier cb ssm dsm dfs (fromIntegral mbc) pmbs (fromIntegral bbc) pbbs (fromIntegral ibc) pibs + +pipelineBarrier2 :: ( + WithPoked (TMaybe.M mn), + HPList.ToListWithCCpsM' WithPoked TMaybe.M mbas, TList.Length mbas, + HPList.ToListWithCCpsM' WithPoked TMaybe.M bmbas, TList.Length bmbas, + HPList.ToListWithCCpsM' WithPoked TMaybe.M imbas, TList.Length imbas + ) => + CommandBuffer.M.C -> DependencyInfo mn mbas bmbas imbas -> IO () +pipelineBarrier2 (CommandBuffer.M.C _ cb) di = + dependencyInfoToCore di \cdi -> alloca \pdi -> do + poke pdi cdi + C.pipelineBarrier2 cb pdi blitImage :: CommandBuffer.M.C -> Image.I -> Image.Layout -> Image.I -> Image.Layout -> diff --git a/src/Gpu/Vulkan/Descriptor/Middle/Internal.hsc b/src/Gpu/Vulkan/Descriptor/Middle/Internal.hsc --- a/src/Gpu/Vulkan/Descriptor/Middle/Internal.hsc +++ b/src/Gpu/Vulkan/Descriptor/Middle/Internal.hsc @@ -9,8 +9,6 @@ indexingExtensionName, ImageInfo(..), imageInfoToCore, BufferInfo(..), bufferInfoToCore ) where -import Control.Monad.Trans - import qualified Gpu.Vulkan.Device.Middle.Internal as Device import qualified Gpu.Vulkan.Buffer.Middle.Internal as Buffer import qualified Gpu.Vulkan.Image.Enum as Image diff --git a/src/Gpu/Vulkan/Enum.hsc b/src/Gpu/Vulkan/Enum.hsc --- a/src/Gpu/Vulkan/Enum.hsc +++ b/src/Gpu/Vulkan/Enum.hsc @@ -17,6 +17,128 @@ #include +enum "AccessFlagBits2" ''#{type VkAccessFlagBits2} + [''Show, ''Eq, ''Storable, ''Bits] [ + ("AccessFlags2Zero", 0), + ("Access2None", #{const VK_ACCESS_2_NONE}), + ("Access2NoneKhr", #{const VK_ACCESS_2_NONE_KHR}), + ("Access2IndirectCommandReadBit", + #{const VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT}), + ("Access2IndirectCommandReadBitKhr", + #{const VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR}), + ("Access2IndexReadBit", #{const VK_ACCESS_2_INDEX_READ_BIT}), + ("Access2IndexReadBitKhr", #{const VK_ACCESS_2_INDEX_READ_BIT_KHR}), + ("Access2VertexAttributeReadBit", + #{const VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT}), + ("Access2VertexAttributeReadBitKhr", + #{const VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT_KHR}), + ("Access2UniformReadBit", #{const VK_ACCESS_2_UNIFORM_READ_BIT}), + ("Access2UniformReadBitKhr", #{const VK_ACCESS_2_UNIFORM_READ_BIT_KHR}), + ("Access2InputAttachmentReadBit", + #{const VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT}), + ("Access2InputAttachmentReadBitKhr", + #{const VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR}), + ("Access2ShaderReadBit", #{const VK_ACCESS_2_SHADER_READ_BIT}), + ("Access2ShaderReadBitKhr", #{const VK_ACCESS_2_SHADER_READ_BIT_KHR}), + ("Access2ShaderWriteBit", #{const VK_ACCESS_2_SHADER_WRITE_BIT}), + ("Access2ShaderWriteBitKhr", #{const VK_ACCESS_2_SHADER_WRITE_BIT_KHR}), + ("Access2ColorAttachmentReadBit", + #{const VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT}), + ("Access2ColorAttachmentReadBitKhr", + #{const VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR}), + ("Access2ColorAttachmentWriteBit", + #{const VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT}), + ("Access2ColorAttachmentWriteBitKhr", + #{const VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR}), + ("Access2DepthStencilAttachmentReadBit", + #{const VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT}), + ("Access2DepthStencilAttachmentReadBitKhr", + #{const VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT_KHR}), + ("Access2DepthStencilAttachmentWriteBit", + #{const VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT}), + ("Access2DepthStencilAttachmentWriteBitKhr", + #{const VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR}), + ("Access2TransferReadBit", #{const VK_ACCESS_2_TRANSFER_READ_BIT}), + ("Access2TransferReadBitKhr", + #{const VK_ACCESS_2_TRANSFER_READ_BIT_KHR}), + ("Access2TransferWriteBit", #{const VK_ACCESS_2_TRANSFER_WRITE_BIT}), + ("Access2TransferWriteBitKhr", + #{const VK_ACCESS_2_TRANSFER_WRITE_BIT_KHR}), + ("Access2HostReadBit", #{const VK_ACCESS_2_HOST_READ_BIT}), + ("Access2HostReadBitKhr", #{const VK_ACCESS_2_HOST_READ_BIT_KHR}), + ("Access2HostWriteBit", #{const VK_ACCESS_2_HOST_WRITE_BIT}), + ("Access2HostWriteBitKhr", #{const VK_ACCESS_2_HOST_WRITE_BIT_KHR}), + ("Access2MemoryReadBit", #{const VK_ACCESS_2_MEMORY_READ_BIT}), + ("Access2MemoryReadBitKhr", #{const VK_ACCESS_2_MEMORY_READ_BIT_KHR}), + ("Access2MemoryWriteBit", #{const VK_ACCESS_2_MEMORY_WRITE_BIT}), + ("Access2MemoryWriteBitKhr", #{const VK_ACCESS_2_MEMORY_WRITE_BIT_KHR}), + ("Access2ShaderSampledReadBit", + #{const VK_ACCESS_2_SHADER_SAMPLED_READ_BIT}), + ("Access2ShaderSampledReadBitKhr", + #{const VK_ACCESS_2_SHADER_SAMPLED_READ_BIT_KHR}), + ("Access2ShaderStorageReadBit", + #{const VK_ACCESS_2_SHADER_STORAGE_READ_BIT}), + ("Access2ShaderStorageReadBitKhr", + #{const VK_ACCESS_2_SHADER_STORAGE_READ_BIT_KHR}), + ("Access2ShaderStorageWriteBit", + #{const VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT}), + ("Access2ShaderStorageWriteBitKhr", + #{const VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR}), + ("Access2VideoDecodeReadBitKhr", + #{const VK_ACCESS_2_VIDEO_DECODE_READ_BIT_KHR}), + ("Access2VideoDecodeWriteBitKhr", + #{const VK_ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHR}), + ("Access2VideoEncodeReadBitKhr", + #{const VK_ACCESS_2_VIDEO_ENCODE_READ_BIT_KHR}), + ("Access2VideoEncodeWriteBitKhr", + #{const VK_ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHR}), + ("Access2TransformFeedbackWriteBitExt", + #{const VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT}), + ("Access2TransformFeedbackCounterReadBitExt", + #{const VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT}), + ("Access2TransformFeedbackCounterWriteBitExt", + #{const VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT}), + ("Access2ConditionalRenderingReadBitExt", + #{const VK_ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT}), + ("Access2CommandPreprocessReadBitNv", + #{const VK_ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV}), + ("Access2CommandPreprocessWriteBitNv", + #{const VK_ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV}), + ("Access2CommandPreprocessReadBitExt", + #{const VK_ACCESS_2_COMMAND_PREPROCESS_READ_BIT_EXT}), + ("Access2CommandPreprocessWriteBitExt", + #{const VK_ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_EXT}), + ("Access2FragmentShadingRateAttachmentReadBitKhr", + #{const VK_ACCESS_2_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR}), + ("Access2ShadingRateImageReadBitNv", + #{const VK_ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV}), + ("Access2AccelerationStructureReadBitKhr", + #{const VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR}), + ("Access2AccelerationStructureWriteBitKhr", + #{const VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR}), + ("Access2AccelerationStructureReadBitNv", + #{const VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_NV}), + ("Access2AccelerationStructureWriteBitNv", + #{const VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_NV}), + ("Access2FragmentDensityMapReadBitExt", + #{const VK_ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT}), + ("Access2ColorAttachmentReadNoncoherentBitExt", + #{const VK_ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT}), + ("Access2DescriptorBufferReadBitExt", + #{const VK_ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT}), + ("Access2InvocationMaskReadBitHuawei", + #{const VK_ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI}), + ("Access2ShaderBindingTableReadBitKhr", + #{const VK_ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR}), + ("Access2MicromapReadBitExt", + #{const VK_ACCESS_2_MICROMAP_READ_BIT_EXT}), + ("Access2MicromapWriteBitExt", + #{const VK_ACCESS_2_MICROMAP_WRITE_BIT_EXT}), + ("Access2OpticalFlowReadBitNv", + #{const VK_ACCESS_2_OPTICAL_FLOW_READ_BIT_NV}), + ("Access2OpticalFlowWriteBitNv", + #{const VK_ACCESS_2_OPTICAL_FLOW_WRITE_BIT_NV}) ] + enum "StructureType" ''#{type VkStructureType} [''Show, ''Eq, ''Storable] [ ("StructureTypeApplicationInfo", @@ -3426,6 +3548,7 @@ type PtrDynamicState = Ptr DynamicState type AccessFlags = AccessFlagBits +type AccessFlags2 = AccessFlagBits2 type DependencyFlags = DependencyFlagBits type QueryControlFlags = QueryControlFlagBits type QueryPipelineStatisticFlags = QueryPipelineStatisticFlagBits diff --git a/src/Gpu/Vulkan/Image/Middle.hs b/src/Gpu/Vulkan/Image/Middle.hs --- a/src/Gpu/Vulkan/Image/Middle.hs +++ b/src/Gpu/Vulkan/Image/Middle.hs @@ -16,7 +16,7 @@ -- * MEMORY BARRIER - MemoryBarrier(..), SubresourceRange(..), + MemoryBarrier(..), MemoryBarrier2(..), SubresourceRange(..), -- * BLIT diff --git a/src/Gpu/Vulkan/Image/Middle/Internal.hs b/src/Gpu/Vulkan/Image/Middle/Internal.hs --- a/src/Gpu/Vulkan/Image/Middle/Internal.hs +++ b/src/Gpu/Vulkan/Image/Middle/Internal.hs @@ -26,6 +26,7 @@ -- * MEMORY BARRIER MemoryBarrier(..), memoryBarrierToCore, + MemoryBarrier2(..), memoryBarrier2ToCore, SubresourceRange(..), subresourceRangeToCore, -- * BLIT @@ -70,6 +71,8 @@ import qualified Gpu.Vulkan.Sample.Enum as Sample import qualified Gpu.Vulkan.QueueFamily.EnumManual as QueueFamily +import qualified Gpu.Vulkan.Pipeline.Enum as Pipeline + data SubresourceRange = SubresourceRange { subresourceRangeAspectMask :: AspectFlags, subresourceRangeBaseMipLevel :: Word32, @@ -291,6 +294,48 @@ C.memoryBarrierDstQueueFamilyIndex = dqfi, C.memoryBarrierImage = img, C.memoryBarrierSubresourceRange = subresourceRangeToCore srr } + +data MemoryBarrier2 mn = MemoryBarrier2 { + memoryBarrier2Next :: TMaybe.M mn, + memoryBarrier2SrcStageMask :: Pipeline.StageFlags2, + memoryBarrier2SrcAccessMask :: AccessFlags2, + memoryBarrier2DstStageMask :: Pipeline.StageFlags2, + memoryBarrier2DstAccessMask :: AccessFlags2, + memoryBarrier2OldLayout :: Layout, memoryBarrier2NewLayout :: Layout, + memoryBarrier2SrcQueueFamilyIndex :: QueueFamily.Index, + memoryBarrier2DstQueueFamilyIndex :: QueueFamily.Index, + memoryBarrier2Image :: I, + memoryBarrier2SubresourceRange :: SubresourceRange } + +memoryBarrier2ToCore :: WithPoked (TMaybe.M mn) => + MemoryBarrier2 mn -> (C.MemoryBarrier2 -> IO a) -> IO () +memoryBarrier2ToCore MemoryBarrier2 { + memoryBarrier2Next = mnxt, + memoryBarrier2SrcStageMask = Pipeline.StageFlagBits2 ssm, + memoryBarrier2SrcAccessMask = AccessFlagBits2 sam, + memoryBarrier2DstStageMask = Pipeline.StageFlagBits2 dsm, + memoryBarrier2DstAccessMask = AccessFlagBits2 dam, + memoryBarrier2OldLayout = Layout ol, + memoryBarrier2NewLayout = Layout nl, + memoryBarrier2SrcQueueFamilyIndex = QueueFamily.Index sqfi, + memoryBarrier2DstQueueFamilyIndex = QueueFamily.Index dqfi, + memoryBarrier2Image = I rimg, + memoryBarrier2SubresourceRange = srr } f = + withPoked' mnxt \pnxt -> withPtrS pnxt \(castPtr -> pnxt') -> + readIORef rimg >>= \(_, img) -> + f C.MemoryBarrier2 { + C.memoryBarrier2SType = (), + C.memoryBarrier2PNext = pnxt', + C.memoryBarrier2SrcStageMask = ssm, + C.memoryBarrier2SrcAccessMask = sam, + C.memoryBarrier2DstStageMask = dsm, + C.memoryBarrier2DstAccessMask = dam, + C.memoryBarrier2OldLayout = ol, + C.memoryBarrier2NewLayout = nl, + C.memoryBarrier2SrcQueueFamilyIndex = sqfi, + C.memoryBarrier2DstQueueFamilyIndex = dqfi, + C.memoryBarrier2Image = img, + C.memoryBarrier2SubresourceRange = subresourceRangeToCore srr } data SubresourceLayers = SubresourceLayers { subresourceLayersAspectMask :: AspectFlags, diff --git a/src/Gpu/Vulkan/Memory/Middle.hs b/src/Gpu/Vulkan/Memory/Middle.hs --- a/src/Gpu/Vulkan/Memory/Middle.hs +++ b/src/Gpu/Vulkan/Memory/Middle.hs @@ -16,7 +16,7 @@ -- * REQUIREMENTS AND BARRIER - Requirements(..), Barrier(..), + Requirements(..), Barrier(..), Barrier2(..), -- * MEMORY TYPE diff --git a/src/Gpu/Vulkan/Memory/Middle/Internal.hsc b/src/Gpu/Vulkan/Memory/Middle/Internal.hsc --- a/src/Gpu/Vulkan/Memory/Middle/Internal.hsc +++ b/src/Gpu/Vulkan/Memory/Middle/Internal.hsc @@ -17,6 +17,7 @@ Requirements(..), requirementsFromCore, Barrier(..), barrierToCore, + Barrier2(..), barrier2ToCore, Heap(..), heapFromCore, @@ -51,6 +52,8 @@ import qualified Gpu.Vulkan.AllocationCallbacks.Middle.Internal as AllocationCallbacks import qualified Gpu.Vulkan.Memory.Core as C +import qualified Gpu.Vulkan.Pipeline.Enum as Pipeline + #include newtype M = M (IORef C.M) @@ -245,7 +248,8 @@ deriving instance Show (TMaybe.M mn) => Show (Barrier mn) -barrierToCore :: WithPoked (TMaybe.M mn) => Barrier mn -> (C.Barrier -> IO a) -> IO () +barrierToCore :: WithPoked (TMaybe.M mn) => + Barrier mn -> (C.Barrier -> IO a) -> IO () barrierToCore Barrier { barrierNext = mnxt, barrierSrcAccessMask = AccessFlagBits sam, @@ -255,3 +259,28 @@ C.barrierPNext = pnxt', C.barrierSrcAccessMask = sam, C.barrierDstAccessMask = dam } + +data Barrier2 mn = Barrier2 { + barrier2Next :: TMaybe.M mn, + barrier2SrcStageMask :: Pipeline.StageFlags2, + barrier2SrcAccessMask :: AccessFlags2, + barrier2DstStageMask :: Pipeline.StageFlags2, + barrier2DstAccessMask :: AccessFlags2 } + +deriving instance Show (TMaybe.M mn) => Show (Barrier2 mn) + +barrier2ToCore :: WithPoked (TMaybe.M mn) => + Barrier2 mn -> (C.Barrier2 -> IO a) -> IO () +barrier2ToCore Barrier2 { + barrier2Next = mnxt, + barrier2SrcStageMask = Pipeline.StageFlagBits2 ssm, + barrier2SrcAccessMask = AccessFlagBits2 sam, + barrier2DstStageMask = Pipeline.StageFlagBits2 dsm, + barrier2DstAccessMask = AccessFlagBits2 dam } f = + withPoked' mnxt \pnxt -> withPtrS pnxt \(castPtr -> pnxt') -> f C.Barrier2 { + C.barrier2SType = (), + C.barrier2PNext = pnxt', + C.barrier2SrcStageMask = ssm, + C.barrier2SrcAccessMask = sam, + C.barrier2DstStageMask = dsm, + C.barrier2DstAccessMask = dam } diff --git a/src/Gpu/Vulkan/Middle.hs b/src/Gpu/Vulkan/Middle.hs --- a/src/Gpu/Vulkan/Middle.hs +++ b/src/Gpu/Vulkan/Middle.hs @@ -67,7 +67,9 @@ -- * OTHERS - Size(..) + Size(..), + + DependencyInfo(..) ) where diff --git a/src/Gpu/Vulkan/Middle/Internal.hsc b/src/Gpu/Vulkan/Middle/Internal.hsc --- a/src/Gpu/Vulkan/Middle/Internal.hsc +++ b/src/Gpu/Vulkan/Middle/Internal.hsc @@ -42,8 +42,10 @@ C.viewportX, C.viewportY, C.viewportWidth, C.viewportHeight, C.viewportMinDepth, C.viewportMaxDepth, - Size(..) + Size(..), + DependencyInfo(..), dependencyInfoToCore + ) where import Foreign.Ptr @@ -54,9 +56,11 @@ import Foreign.Storable.PeekPoke import Control.Arrow import Control.Monad +import Data.Kind import Data.Default import Data.TypeLevel.Maybe qualified as TMaybe import Data.TypeLevel.List qualified as TL +import Data.HeteroParList qualified as HPList import Data.HeteroParList qualified as HeteroParList import Data.HeteroParList (pattern (:**)) import Data.Word @@ -76,6 +80,10 @@ import Gpu.Vulkan.Middle.Types +import qualified Gpu.Vulkan.Memory.Middle.Internal as Memory +import {-# SOURCE #-} qualified Gpu.Vulkan.Buffer.Middle.Internal as Buffer +import qualified Gpu.Vulkan.Image.Middle.Internal as Image + #include data ApplicationInfo mn = ApplicationInfo { @@ -349,3 +357,49 @@ formatPropertiesOptimalTilingFeatures = FormatFeatureFlagBits otfs, formatPropertiesBufferFeatures = FormatFeatureFlagBits bfs } + +data DependencyInfo mn mbs bmbs imbs = DependencyInfo { + dependencyInfoNext :: TMaybe.M mn, + dependencyInfoDependencyFlags :: DependencyFlags, + dependencyInfoMemoryBarriers :: HPList.PL Memory.Barrier2 mbs, + dependencyInfoBufferMemoryBarriers :: + HPList.PL Buffer.MemoryBarrier2 bmbs, + dependencyInfoImageMemoryBarriers :: + HPList.PL Image.MemoryBarrier2 imbs } + +dependencyInfoToCore :: forall mn (mbs :: [Maybe Type]) bmbs imbs a . ( + WithPoked (TMaybe.M mn), + HPList.ToListWithCCpsM' WithPoked TMaybe.M mbs, TL.Length mbs, + HPList.ToListWithCCpsM' WithPoked TMaybe.M bmbs, TL.Length bmbs, + HPList.ToListWithCCpsM' WithPoked TMaybe.M imbs, TL.Length imbs ) => + DependencyInfo mn mbs bmbs imbs -> (C.DependencyInfo -> IO a) -> IO () +dependencyInfoToCore DependencyInfo { + dependencyInfoNext = mnxt, + dependencyInfoDependencyFlags = DependencyFlagBits fs, + dependencyInfoMemoryBarriers = mbs, + dependencyInfoBufferMemoryBarriers = bmbs, + dependencyInfoImageMemoryBarriers = imbs } f = + withPoked' mnxt \pnxt -> withPtrS pnxt \(castPtr -> pnxt') -> + allocaArray mbc \pmbs -> + allocaArray bmbc \pbmbs -> allocaArray imbc \pimbs -> do + HPList.withListWithCCpsM' @_ @WithPoked @TMaybe.M + mbs Memory.barrier2ToCore \cmbs -> pokeArray pmbs cmbs + HPList.withListWithCCpsM' @_ @WithPoked @TMaybe.M + bmbs Buffer.memoryBarrier2ToCore \cbmbs -> pokeArray pbmbs cbmbs + HPList.withListWithCCpsM' @_ @WithPoked @TMaybe.M + imbs Image.memoryBarrier2ToCore \cimbs -> pokeArray pimbs cimbs + f C.DependencyInfo { + C.dependencyInfoSType = (), + C.dependencyInfoPNext = pnxt', + C.dependencyInfoDependencyFlags = fs, + C.dependencyInfoMemoryBarrierCount = mbc, + C.dependencyInfoPMemoryBarriers = pmbs, + C.dependencyInfoBufferMemoryBarrierCount = bmbc, + C.dependencyInfoPBufferMemoryBarriers = pbmbs, + C.dependencyInfoImageMemoryBarrierCount = imbc, + C.dependencyInfoPImageMemoryBarriers = pimbs } + where + mbc, bmbc, imbc :: Integral n => n + mbc = TL.length @_ @mbs + bmbc = TL.length @_ @bmbs + imbc = TL.length @_ @imbs diff --git a/src/Gpu/Vulkan/Pipeline/Enum.hsc b/src/Gpu/Vulkan/Pipeline/Enum.hsc --- a/src/Gpu/Vulkan/Pipeline/Enum.hsc +++ b/src/Gpu/Vulkan/Pipeline/Enum.hsc @@ -102,6 +102,155 @@ instance Default StageFlagBits where def = StageFlagsZero +enum "StageFlagBits2" ''#{type VkPipelineStageFlagBits2} + [''Show, ''Eq, ''Storable, ''Bits] [ + ("StageFlags2Zero", 0), + ("Stage2None", #{const VK_PIPELINE_STAGE_2_NONE}), + ("Stage2NoneKhr", #{const VK_PIPELINE_STAGE_2_NONE_KHR}), + ("Stage2TopOfPipeBit", + #{const VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT}), + ("Stage2TopOfPipeBitKhr", + #{const VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR}), + ("Stage2DrawIndirectBit", + #{const VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT}), + ("Stage2DrawIndirectBitKhr", + #{const VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR}), + ("Stage2VertexInputBit", + #{const VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT}), + ("Stage2VertexInputBitKhr", + #{const VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR}), + ("Stage2VertexShaderBit", + #{const VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT}), + ("Stage2VertexShaderBitKhr", + #{const VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR}), + ("Stage2TessellationControlShaderBit", + #{const VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT}), + ("Stage2TessellationControlShaderBitKhr", + #{const VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR}), + ("Stage2TessellationEvaluationShaderBit", + #{const VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT}), + ("Stage2TessellationEvaluationShaderBitKhr", + #{const VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR}), + ("Stage2GeometryShaderBit", + #{const VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT}), + ("Stage2GeometryShaderBitKhr", + #{const VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR}), + ("Stage2FragmentShaderBit", + #{const VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT}), + ("Stage2FragmentShaderBitKhr", + #{const VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR}), + ("Stage2EarlyFragmentTestsBit", + #{const VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT}), + ("Stage2EarlyFragmentTestsBitKhr", + #{const VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR}), + ("Stage2LateFragmentTestsBit", + #{const VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT}), + ("Stage2LateFragmentTestsBitKhr", + #{const VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR}), + ("Stage2ColorAttachmentOutputBit", + #{const VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT}), + ("Stage2ColorAttachmentOutputBitKhr", + #{const VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR}), + ("Stage2ComputeShaderBit", + #{const VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT}), + ("Stage2ComputeShaderBitKhr", + #{const VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT_KHR}), + ("Stage2AllTransferBit", + #{const VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT}), + ("Stage2AllTransferBitKhr", + #{const VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR}), + ("Stage2TransferBit", + #{const VK_PIPELINE_STAGE_2_TRANSFER_BIT}), + ("Stage2TransferBitKhr", + #{const VK_PIPELINE_STAGE_2_TRANSFER_BIT_KHR}), + ("Stage2BottomOfPipeBit", + #{const VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT}), + ("Stage2BottomOfPipeBitKhr", + #{const VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR}), + ("Stage2HostBit", #{const VK_PIPELINE_STAGE_2_HOST_BIT}), + ("Stage2HostBitKhr", #{const VK_PIPELINE_STAGE_2_HOST_BIT_KHR}), + ("Stage2AllGraphicsBit", + #{const VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT}), + ("Stage2AllGraphicsBitKhr", + #{const VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR}), + ("Stage2AllCommandsBit", + #{const VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT}), + ("Stage2AllCommandsBitKhr", + #{const VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR}), + ("Stage2CopyBit", #{const VK_PIPELINE_STAGE_2_COPY_BIT}), + ("Stage2CopyBitKhr", #{const VK_PIPELINE_STAGE_2_COPY_BIT_KHR}), + ("Stage2ResolveBit", #{const VK_PIPELINE_STAGE_2_RESOLVE_BIT}), + ("Stage2ResolveBitKhr", + #{const VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR}), + ("Stage2BlitBit", #{const VK_PIPELINE_STAGE_2_BLIT_BIT}), + ("Stage2BlitBitKhr", #{const VK_PIPELINE_STAGE_2_BLIT_BIT_KHR}), + ("Stage2ClearBit", #{const VK_PIPELINE_STAGE_2_CLEAR_BIT}), + ("Stage2ClearBitKhr", + #{const VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR}), + ("Stage2IndexInputBit", + #{const VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT}), + ("Stage2IndexInputBitKhr", + #{const VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR}), + ("Stage2VertexAttributeInputBit", + #{const VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT}), + ("Stage2VertexAttributeInputBitKhr", + #{const VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR}), + ("Stage2PreRasterizationShadersBit", + #{const VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT}), + ("Stage2PreRasterizationShadersBitKhr", + #{const VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT_KHR}), + ("Stage2VideoDecodeBitKhr", + #{const VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR}), + ("Stage2VideoEncodeBitKhr", + #{const VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR}), + ("Stage2TransformFeedbackBitExt", + #{const VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT}), + ("Stage2ConditionalRenderingBitExt", + #{const VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT}), + ("Stage2CommandPreprocessBitNv", + #{const VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV}), + ("Stage2CommandPreprocessBitExt", + #{const VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_EXT}), + ("Stage2FragmentShadingRateAttachmentBitKhr", + #{const VK_PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR}), + ("Stage2ShadingRateImageBitNv", + #{const VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV}), + ("Stage2AccelerationStructureBuildBitKhr", + #{const VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR}), + ("Stage2RayTracingShaderBitKhr", + #{const VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR}), + ("Stage2RayTracingShaderBitNv", + #{const VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_NV}), + ("Stage2AccelerationStructureBuildBitNv", + #{const VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_NV}), + ("Stage2FragmentDensityProcessBitExt", + #{const VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT}), + ("Stage2TaskShaderBitNv", + #{const VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV}), + ("Stage2MeshShaderBitNv", + #{const VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV}), + ("Stage2TaskShaderBitExt", + #{const VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT}), + ("Stage2MeshShaderBitExt", + #{const VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT}), + ("Stage2SubpassShaderBitHuawei", + #{const VK_PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI}), + ("Stage2SubpassShadingBitHuawei", + #{const VK_PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI}), + ("Stage2InvocationMaskBitHuawei", + #{const VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI}), + ("Stage2AccelerationStructureCopyBitKhr", + #{const VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR}), + ("Stage2MicromapBuildBitExt", + #{const VK_PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT}), + ("Stage2ClusterCullingShaderBitHuawei", + #{const VK_PIPELINE_STAGE_2_CLUSTER_CULLING_SHADER_BIT_HUAWEI}), + ("Stage2OpticalFlowBitNv", + #{const VK_PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV}) ] + +instance Default StageFlagBits2 where + def = StageFlags2Zero + enum "CreateFlagBits" ''#{type VkPipelineCreateFlagBits} [''Show, ''Eq, ''Storable, ''Bits] [ ("CreateFlagsZero", 0), @@ -186,4 +335,5 @@ def = CreateFlagsZero type StageFlags = StageFlagBits +type StageFlags2 = StageFlagBits2 type CreateFlags = CreateFlagBits diff --git a/src/Gpu/Vulkan/Sparse/Buffer/Middle/Internal.hs b/src/Gpu/Vulkan/Sparse/Buffer/Middle/Internal.hs --- a/src/Gpu/Vulkan/Sparse/Buffer/Middle/Internal.hs +++ b/src/Gpu/Vulkan/Sparse/Buffer/Middle/Internal.hs @@ -5,9 +5,7 @@ module Gpu.Vulkan.Sparse.Buffer.Middle.Internal where -import Foreign.Ptr import Foreign.Marshal.Array -import Foreign.Storable.PeekPoke import Control.Arrow import Gpu.Vulkan.Buffer.Middle.Internal qualified as Buffer diff --git a/src/Gpu/Vulkan/Sparse/Image/Middle/Internal.hs b/src/Gpu/Vulkan/Sparse/Image/Middle/Internal.hs --- a/src/Gpu/Vulkan/Sparse/Image/Middle/Internal.hs +++ b/src/Gpu/Vulkan/Sparse/Image/Middle/Internal.hs @@ -5,9 +5,7 @@ module Gpu.Vulkan.Sparse.Image.Middle.Internal where -import Foreign.Ptr import Foreign.Marshal.Array -import Foreign.Storable.PeekPoke import Control.Arrow import Data.IORef