diff --git a/.golden/stm32f405-isrs/golden b/.golden/stm32f405-isrs/golden new file mode 100644 --- /dev/null +++ b/.golden/stm32f405-isrs/golden @@ -0,0 +1,90 @@ + | WWDG -- 0 Window Watchdog interrupt + | PVD -- 1 PVD through EXTI line detection interrupt + | TAMP_STAMP -- 2 Tamper and TimeStamp interrupts through the EXTI line + | RTC_WKUP -- 3 RTC Wakeup interrupt through the EXTI line + | Undefined4 -- 4 Undefined interrupt (padding only) + | RCC -- 5 RCC global interrupt + | EXTI0 -- 6 EXTI Line0 interrupt + | EXTI1 -- 7 EXTI Line1 interrupt + | EXTI2 -- 8 EXTI Line2 interrupt + | EXTI3 -- 9 EXTI Line3 interrupt + | EXTI4 -- 10 EXTI Line4 interrupt + | DMA1_STREAM0 -- 11 DMA1 Stream0 global interrupt + | DMA1_STREAM1 -- 12 DMA1 Stream1 global interrupt + | DMA1_STREAM2 -- 13 DMA1 Stream2 global interrupt + | DMA1_STREAM3 -- 14 DMA1 Stream3 global interrupt + | DMA1_STREAM4 -- 15 DMA1 Stream4 global interrupt + | DMA1_STREAM5 -- 16 DMA1 Stream5 global interrupt + | DMA1_STREAM6 -- 17 DMA1 Stream6 global interrupt + | ADC -- 18 ADC1 global interrupt + | CAN1_TX -- 19 CAN1 TX interrupts + | CAN1_RX0 -- 20 CAN1 RX0 interrupts + | CAN1_RX1 -- 21 CAN1 RX1 interrupts + | CAN1_SCE -- 22 CAN1 SCE interrupt + | EXTI9_5 -- 23 EXTI Line[9:5] interrupts + | TIM1_BRK_TIM9 -- 24 TIM1 Break interrupt and TIM9 global interrupt + | TIM1_UP_TIM10 -- 25 TIM1 Update interrupt and TIM10 global interrupt + | TIM1_TRG_COM_TIM11 -- 26 TIM1 Trigger and Commutation interrupts and TIM11 global interrupt + | TIM1_CC -- 27 TIM1 Capture Compare interrupt + | TIM2 -- 28 TIM2 global interrupt + | TIM3 -- 29 TIM3 global interrupt + | TIM4 -- 30 TIM4 global interrupt + | I2C1_EV -- 31 I2C1 event interrupt + | I2C1_ER -- 32 I2C1 error interrupt + | I2C2_EV -- 33 I2C2 event interrupt + | I2C2_ER -- 34 I2C2 error interrupt + | SPI1 -- 35 SPI1 global interrupt + | SPI2 -- 36 SPI2 global interrupt + | USART1 -- 37 USART1 global interrupt + | USART2 -- 38 USART2 global interrupt + | USART3 -- 39 USART3 global interrupt + | EXTI15_10 -- 40 EXTI Line[15:10] interrupts + | RTC_ALARM -- 41 RTC Alarms (A and B) through EXTI line interrupt + | OTG_FS_WKUP -- 42 USB On-The-Go FS Wakeup through EXTI line interrupt + | TIM8_BRK_TIM12 -- 43 TIM8 Break interrupt and TIM12 global interrupt + | TIM8_UP_TIM13 -- 44 TIM8 Update interrupt and TIM13 global interrupt + | TIM8_TRG_COM_TIM14 -- 45 TIM8 Trigger and Commutation interrupts and TIM14 global interrupt + | TIM8_CC -- 46 TIM8 Capture Compare interrupt + | DMA1_STREAM7 -- 47 DMA1 Stream7 global interrupt + | FSMC -- 48 FSMC global interrupt + | SDIO -- 49 SDIO global interrupt + | TIM5 -- 50 TIM5 global interrupt + | SPI3 -- 51 SPI3 global interrupt + | UART4 -- 52 UART4 global interrupt + | UART5 -- 53 UART5 global interrupt + | TIM6_DAC -- 54 TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt + | TIM7 -- 55 TIM7 global interrupt + | DMA2_STREAM0 -- 56 DMA2 Stream0 global interrupt + | DMA2_STREAM1 -- 57 DMA2 Stream1 global interrupt + | DMA2_STREAM2 -- 58 DMA2 Stream2 global interrupt + | DMA2_STREAM3 -- 59 DMA2 Stream3 global interrupt + | DMA2_STREAM4 -- 60 DMA2 Stream4 global interrupt + | Undefined61 -- 61 Undefined interrupt (padding only) + | Undefined62 -- 62 Undefined interrupt (padding only) + | CAN2_TX -- 63 CAN2 TX interrupts + | CAN2_RX0 -- 64 CAN2 RX0 interrupts + | CAN2_RX1 -- 65 CAN2 RX1 interrupts + | CAN2_SCE -- 66 CAN2 SCE interrupt + | OTG_FS -- 67 USB On The Go FS global interrupt + | DMA2_STREAM5 -- 68 DMA2 Stream5 global interrupt + | DMA2_STREAM6 -- 69 DMA2 Stream6 global interrupt + | DMA2_STREAM7 -- 70 DMA2 Stream7 global interrupt + | USART6 -- 71 USART6 global interrupt + | I2C3_EV -- 72 I2C3 event interrupt + | I2C3_ER -- 73 I2C3 error interrupt + | OTG_HS_EP1_OUT -- 74 USB On The Go HS End Point 1 Out global interrupt + | OTG_HS_EP1_IN -- 75 USB On The Go HS End Point 1 In global interrupt + | OTG_HS_WKUP -- 76 USB On The Go HS Wakeup through EXTI interrupt + | OTG_HS -- 77 USB On The Go HS global interrupt + | DCMI -- 78 DCMI global interrupt + | CRYP -- 79 CRYP crypto global interrupt + | HASH_RNG -- 80 Hash and Rng global interrupt + | FPU -- 81 FPU interrupt + | Undefined82 -- 82 Undefined interrupt (padding only) + | Undefined83 -- 83 Undefined interrupt (padding only) + | Undefined84 -- 84 Undefined interrupt (padding only) + | Undefined85 -- 85 Undefined interrupt (padding only) + | Undefined86 -- 86 Undefined interrupt (padding only) + | Undefined87 -- 87 Undefined interrupt (padding only) + | LTDC -- 88 LTDC global interrupt + | LTDC_ER -- 89 LTDC global error interrupt diff --git a/.golden/stm32f405-memmap/golden b/.golden/stm32f405-memmap/golden new file mode 100644 --- /dev/null +++ b/.golden/stm32f405-memmap/golden @@ -0,0 +1,170 @@ +tim2_periph_base :: Integer +tim2_periph_base = 0x40000000 +tim3_periph_base :: Integer +tim3_periph_base = 0x40000400 +tim4_periph_base :: Integer +tim4_periph_base = 0x40000800 +tim5_periph_base :: Integer +tim5_periph_base = 0x40000c00 +tim6_periph_base :: Integer +tim6_periph_base = 0x40001000 +tim7_periph_base :: Integer +tim7_periph_base = 0x40001400 +tim12_periph_base :: Integer +tim12_periph_base = 0x40001800 +tim13_periph_base :: Integer +tim13_periph_base = 0x40001c00 +tim14_periph_base :: Integer +tim14_periph_base = 0x40002000 +rtc_periph_base :: Integer +rtc_periph_base = 0x40002800 +wwdg_periph_base :: Integer +wwdg_periph_base = 0x40002c00 +iwdg_periph_base :: Integer +iwdg_periph_base = 0x40003000 +i2s2ext_periph_base :: Integer +i2s2ext_periph_base = 0x40003400 +spi2_periph_base :: Integer +spi2_periph_base = 0x40003800 +spi3_periph_base :: Integer +spi3_periph_base = 0x40003c00 +i2s3ext_periph_base :: Integer +i2s3ext_periph_base = 0x40004000 +usart2_periph_base :: Integer +usart2_periph_base = 0x40004400 +usart3_periph_base :: Integer +usart3_periph_base = 0x40004800 +uart4_periph_base :: Integer +uart4_periph_base = 0x40004c00 +uart5_periph_base :: Integer +uart5_periph_base = 0x40005000 +i2c1_periph_base :: Integer +i2c1_periph_base = 0x40005400 +i2c2_periph_base :: Integer +i2c2_periph_base = 0x40005800 +i2c3_periph_base :: Integer +i2c3_periph_base = 0x40005c00 +can1_periph_base :: Integer +can1_periph_base = 0x40006400 +can2_periph_base :: Integer +can2_periph_base = 0x40006800 +pwr_periph_base :: Integer +pwr_periph_base = 0x40007000 +dac_periph_base :: Integer +dac_periph_base = 0x40007400 +tim1_periph_base :: Integer +tim1_periph_base = 0x40010000 +tim8_periph_base :: Integer +tim8_periph_base = 0x40010400 +usart1_periph_base :: Integer +usart1_periph_base = 0x40011000 +usart6_periph_base :: Integer +usart6_periph_base = 0x40011400 +adc1_periph_base :: Integer +adc1_periph_base = 0x40012000 +adc2_periph_base :: Integer +adc2_periph_base = 0x40012100 +adc3_periph_base :: Integer +adc3_periph_base = 0x40012200 +adc_common_periph_base :: Integer +adc_common_periph_base = 0x40012300 +sdio_periph_base :: Integer +sdio_periph_base = 0x40012c00 +spi1_periph_base :: Integer +spi1_periph_base = 0x40013000 +spi4_periph_base :: Integer +spi4_periph_base = 0x40013400 +syscfg_periph_base :: Integer +syscfg_periph_base = 0x40013800 +exti_periph_base :: Integer +exti_periph_base = 0x40013c00 +tim9_periph_base :: Integer +tim9_periph_base = 0x40014000 +tim10_periph_base :: Integer +tim10_periph_base = 0x40014400 +tim11_periph_base :: Integer +tim11_periph_base = 0x40014800 +spi5_periph_base :: Integer +spi5_periph_base = 0x40015000 +spi6_periph_base :: Integer +spi6_periph_base = 0x40015400 +sai1_periph_base :: Integer +sai1_periph_base = 0x40015800 +ltdc_periph_base :: Integer +ltdc_periph_base = 0x40016800 +gpioa_periph_base :: Integer +gpioa_periph_base = 0x40020000 +gpiob_periph_base :: Integer +gpiob_periph_base = 0x40020400 +gpioc_periph_base :: Integer +gpioc_periph_base = 0x40020800 +gpiod_periph_base :: Integer +gpiod_periph_base = 0x40020c00 +gpioe_periph_base :: Integer +gpioe_periph_base = 0x40021000 +gpiof_periph_base :: Integer +gpiof_periph_base = 0x40021400 +gpiog_periph_base :: Integer +gpiog_periph_base = 0x40021800 +gpioh_periph_base :: Integer +gpioh_periph_base = 0x40021c00 +gpioi_periph_base :: Integer +gpioi_periph_base = 0x40022000 +gpioj_periph_base :: Integer +gpioj_periph_base = 0x40022400 +gpiok_periph_base :: Integer +gpiok_periph_base = 0x40022800 +crc_periph_base :: Integer +crc_periph_base = 0x40023000 +rcc_periph_base :: Integer +rcc_periph_base = 0x40023800 +flash_periph_base :: Integer +flash_periph_base = 0x40023c00 +dma1_periph_base :: Integer +dma1_periph_base = 0x40026000 +dma2_periph_base :: Integer +dma2_periph_base = 0x40026400 +otg_hs_global_periph_base :: Integer +otg_hs_global_periph_base = 0x40040000 +otg_hs_host_periph_base :: Integer +otg_hs_host_periph_base = 0x40040400 +otg_hs_device_periph_base :: Integer +otg_hs_device_periph_base = 0x40040800 +otg_hs_pwrclk_periph_base :: Integer +otg_hs_pwrclk_periph_base = 0x40040e00 +otg_fs_global_periph_base :: Integer +otg_fs_global_periph_base = 0x50000000 +otg_fs_host_periph_base :: Integer +otg_fs_host_periph_base = 0x50000400 +otg_fs_device_periph_base :: Integer +otg_fs_device_periph_base = 0x50000800 +otg_fs_pwrclk_periph_base :: Integer +otg_fs_pwrclk_periph_base = 0x50000e00 +dcmi_periph_base :: Integer +dcmi_periph_base = 0x50050000 +cryp_periph_base :: Integer +cryp_periph_base = 0x50060000 +hash_periph_base :: Integer +hash_periph_base = 0x50060400 +rng_periph_base :: Integer +rng_periph_base = 0x50060800 +fsmc_periph_base :: Integer +fsmc_periph_base = 0xa0000000 +scb_actrl_periph_base :: Integer +scb_actrl_periph_base = 0xe000e008 +stk_periph_base :: Integer +stk_periph_base = 0xe000e010 +nvic_periph_base :: Integer +nvic_periph_base = 0xe000e100 +scb_periph_base :: Integer +scb_periph_base = 0xe000ed00 +fpu_cpacr_periph_base :: Integer +fpu_cpacr_periph_base = 0xe000ed88 +mpu_periph_base :: Integer +mpu_periph_base = 0xe000ed90 +nvic_stir_periph_base :: Integer +nvic_stir_periph_base = 0xe000ef00 +fpu_periph_base :: Integer +fpu_periph_base = 0xe000ef34 +dbgmcu_periph_base :: Integer +dbgmcu_periph_base = 0xe0042000 diff --git a/.golden/stm32f405/golden b/.golden/stm32f405/golden new file mode 100644 --- /dev/null +++ b/.golden/stm32f405/golden @@ -0,0 +1,8896 @@ +STM32F405 + + TIM2 0x40000000 General purpose timers + + CR1 0x0 - control register 1 + _ :: Bits 22 -- (Reserved) + CKD :: Bits 2 -- Clock division + ARPE :: Bit -- Auto-reload preload enable + CMS :: Bits 2 -- Center-aligned mode selection + DIR :: Bit -- Direction + OPM :: Bit -- One-pulse mode + URS :: Bit -- Update request source + UDIS :: Bit -- Update disable + CEN :: Bit -- Counter enable + + CR2 0x4 - control register 2 + _ :: Bits 24 -- (Reserved) + TI1S :: Bit -- TI1 selection + MMS :: Bits 3 -- Master mode selection + CCDS :: Bit -- Capture/compare DMA selection + _ :: Bits 3 -- (Reserved) + + SMCR 0x8 - slave mode control register + _ :: Bits 16 -- (Reserved) + ETP :: Bit -- External trigger polarity + ECE :: Bit -- External clock enable + ETPS :: Bits 2 -- External trigger prescaler + ETF :: Bits 4 -- External trigger filter + MSM :: Bit -- Master/Slave mode + TS :: Bits 3 -- Trigger selection + _ :: Bit -- (Reserved) + SMS :: Bits 3 -- Slave mode selection + + DIER 0xc - DMA/Interrupt enable register + _ :: Bits 17 -- (Reserved) + TDE :: Bit -- Trigger DMA request enable + _ :: Bit -- (Reserved) + CC4DE :: Bit -- Capture/Compare 4 DMA request enable + CC3DE :: Bit -- Capture/Compare 3 DMA request enable + CC2DE :: Bit -- Capture/Compare 2 DMA request enable + CC1DE :: Bit -- Capture/Compare 1 DMA request enable + UDE :: Bit -- Update DMA request enable + _ :: Bit -- (Reserved) + TIE :: Bit -- Trigger interrupt enable + _ :: Bit -- (Reserved) + CC4IE :: Bit -- Capture/Compare 4 interrupt enable + CC3IE :: Bit -- Capture/Compare 3 interrupt enable + CC2IE :: Bit -- Capture/Compare 2 interrupt enable + CC1IE :: Bit -- Capture/Compare 1 interrupt enable + UIE :: Bit -- Update interrupt enable + + SR 0x10 - status register + _ :: Bits 19 -- (Reserved) + CC4OF :: Bit -- Capture/Compare 4 overcapture flag + CC3OF :: Bit -- Capture/Compare 3 overcapture flag + CC2OF :: Bit -- Capture/compare 2 overcapture flag + CC1OF :: Bit -- Capture/Compare 1 overcapture flag + _ :: Bits 2 -- (Reserved) + TIF :: Bit -- Trigger interrupt flag + _ :: Bit -- (Reserved) + CC4IF :: Bit -- Capture/Compare 4 interrupt flag + CC3IF :: Bit -- Capture/Compare 3 interrupt flag + CC2IF :: Bit -- Capture/Compare 2 interrupt flag + CC1IF :: Bit -- Capture/compare 1 interrupt flag + UIF :: Bit -- Update interrupt flag + + EGR 0x14 - event generation register + _ :: Bits 25 -- (Reserved) + TG :: Bit -- Trigger generation + _ :: Bit -- (Reserved) + CC4G :: Bit -- Capture/compare 4 generation + CC3G :: Bit -- Capture/compare 3 generation + CC2G :: Bit -- Capture/compare 2 generation + CC1G :: Bit -- Capture/compare 1 generation + UG :: Bit -- Update generation + + CCMR1_Output 0x18 - capture/compare mode register 1 (output mode) + _ :: Bits 16 -- (Reserved) + OC2CE :: Bit -- OC2CE + OC2M :: Bits 3 -- OC2M + OC2PE :: Bit -- OC2PE + OC2FE :: Bit -- OC2FE + CC2S :: Bits 2 -- CC2S + OC1CE :: Bit -- OC1CE + OC1M :: Bits 3 -- OC1M + OC1PE :: Bit -- OC1PE + OC1FE :: Bit -- OC1FE + CC1S :: Bits 2 -- CC1S + + CCMR1_Input 0x18 - capture/compare mode register 1 (input mode) + _ :: Bits 16 -- (Reserved) + IC2F :: Bits 4 -- Input capture 2 filter + IC2PSC :: Bits 2 -- Input capture 2 prescaler + CC2S :: Bits 2 -- Capture/Compare 2 selection + IC1F :: Bits 4 -- Input capture 1 filter + IC1PSC :: Bits 2 -- Input capture 1 prescaler + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCMR2_Output 0x1c - capture/compare mode register 2 (output mode) + _ :: Bits 16 -- (Reserved) + OC4CE :: Bit -- O24CE + OC4M :: Bits 3 -- OC4M + OC4PE :: Bit -- OC4PE + OC4FE :: Bit -- OC4FE + CC4S :: Bits 2 -- CC4S + OC3CE :: Bit -- OC3CE + OC3M :: Bits 3 -- OC3M + OC3PE :: Bit -- OC3PE + OC3FE :: Bit -- OC3FE + CC3S :: Bits 2 -- CC3S + + CCMR2_Input 0x1c - capture/compare mode register 2 (input mode) + _ :: Bits 16 -- (Reserved) + IC4F :: Bits 4 -- Input capture 4 filter + IC4PSC :: Bits 2 -- Input capture 4 prescaler + CC4S :: Bits 2 -- Capture/Compare 4 selection + IC3F :: Bits 4 -- Input capture 3 filter + IC3PSC :: Bits 2 -- Input capture 3 prescaler + CC3S :: Bits 2 -- Capture/compare 3 selection + + CCER 0x20 - capture/compare enable register + _ :: Bits 16 -- (Reserved) + CC4NP :: Bit -- Capture/Compare 4 output Polarity + _ :: Bit -- (Reserved) + CC4P :: Bit -- Capture/Compare 3 output Polarity + CC4E :: Bit -- Capture/Compare 4 output enable + CC3NP :: Bit -- Capture/Compare 3 output Polarity + _ :: Bit -- (Reserved) + CC3P :: Bit -- Capture/Compare 3 output Polarity + CC3E :: Bit -- Capture/Compare 3 output enable + CC2NP :: Bit -- Capture/Compare 2 output Polarity + _ :: Bit -- (Reserved) + CC2P :: Bit -- Capture/Compare 2 output Polarity + CC2E :: Bit -- Capture/Compare 2 output enable + CC1NP :: Bit -- Capture/Compare 1 output Polarity + _ :: Bit -- (Reserved) + CC1P :: Bit -- Capture/Compare 1 output Polarity + CC1E :: Bit -- Capture/Compare 1 output enable + + CNT 0x24 - counter + CNT :: Bits 32 -- Counter value + + PSC 0x28 - prescaler + _ :: Bits 16 -- (Reserved) + PSC :: Bits 16 -- Prescaler value + + ARR 0x2c - auto-reload register + ARR :: Bits 32 -- Auto-reload value + + CCR1 0x34 - capture/compare register + CCR :: Bits 32 -- Capture/Compare value + + CCR2 0x38 - capture/compare register + CCR :: Bits 32 -- Capture/Compare value + + CCR3 0x3c - capture/compare register + CCR :: Bits 32 -- Capture/Compare value + + CCR4 0x40 - capture/compare register + CCR :: Bits 32 -- Capture/Compare value + + DCR 0x48 - DMA control register + _ :: Bits 19 -- (Reserved) + DBL :: Bits 5 -- DMA burst length + _ :: Bits 3 -- (Reserved) + DBA :: Bits 5 -- DMA base address + + DMAR 0x4c - DMA address for full transfer + _ :: Bits 16 -- (Reserved) + DMAB :: Bits 16 -- DMA register for burst accesses + + OR 0x50 - TIM5 option register + _ :: Bits 20 -- (Reserved) + ITR1_RMP :: Bits 2 -- Timer Input 4 remap + _ :: Bits 10 -- (Reserved) + + TIM3 0x40000400 General purpose timers + + CR1 0x0 - control register 1 + _ :: Bits 22 -- (Reserved) + CKD :: Bits 2 -- Clock division + ARPE :: Bit -- Auto-reload preload enable + CMS :: Bits 2 -- Center-aligned mode selection + DIR :: Bit -- Direction + OPM :: Bit -- One-pulse mode + URS :: Bit -- Update request source + UDIS :: Bit -- Update disable + CEN :: Bit -- Counter enable + + CR2 0x4 - control register 2 + _ :: Bits 24 -- (Reserved) + TI1S :: Bit -- TI1 selection + MMS :: Bits 3 -- Master mode selection + CCDS :: Bit -- Capture/compare DMA selection + _ :: Bits 3 -- (Reserved) + + SMCR 0x8 - slave mode control register + _ :: Bits 16 -- (Reserved) + ETP :: Bit -- External trigger polarity + ECE :: Bit -- External clock enable + ETPS :: Bits 2 -- External trigger prescaler + ETF :: Bits 4 -- External trigger filter + MSM :: Bit -- Master/Slave mode + TS :: Bits 3 -- Trigger selection + _ :: Bit -- (Reserved) + SMS :: Bits 3 -- Slave mode selection + + DIER 0xc - DMA/Interrupt enable register + _ :: Bits 17 -- (Reserved) + TDE :: Bit -- Trigger DMA request enable + _ :: Bit -- (Reserved) + CC4DE :: Bit -- Capture/Compare 4 DMA request enable + CC3DE :: Bit -- Capture/Compare 3 DMA request enable + CC2DE :: Bit -- Capture/Compare 2 DMA request enable + CC1DE :: Bit -- Capture/Compare 1 DMA request enable + UDE :: Bit -- Update DMA request enable + _ :: Bit -- (Reserved) + TIE :: Bit -- Trigger interrupt enable + _ :: Bit -- (Reserved) + CC4IE :: Bit -- Capture/Compare 4 interrupt enable + CC3IE :: Bit -- Capture/Compare 3 interrupt enable + CC2IE :: Bit -- Capture/Compare 2 interrupt enable + CC1IE :: Bit -- Capture/Compare 1 interrupt enable + UIE :: Bit -- Update interrupt enable + + SR 0x10 - status register + _ :: Bits 19 -- (Reserved) + CC4OF :: Bit -- Capture/Compare 4 overcapture flag + CC3OF :: Bit -- Capture/Compare 3 overcapture flag + CC2OF :: Bit -- Capture/compare 2 overcapture flag + CC1OF :: Bit -- Capture/Compare 1 overcapture flag + _ :: Bits 2 -- (Reserved) + TIF :: Bit -- Trigger interrupt flag + _ :: Bit -- (Reserved) + CC4IF :: Bit -- Capture/Compare 4 interrupt flag + CC3IF :: Bit -- Capture/Compare 3 interrupt flag + CC2IF :: Bit -- Capture/Compare 2 interrupt flag + CC1IF :: Bit -- Capture/compare 1 interrupt flag + UIF :: Bit -- Update interrupt flag + + EGR 0x14 - event generation register + _ :: Bits 25 -- (Reserved) + TG :: Bit -- Trigger generation + _ :: Bit -- (Reserved) + CC4G :: Bit -- Capture/compare 4 generation + CC3G :: Bit -- Capture/compare 3 generation + CC2G :: Bit -- Capture/compare 2 generation + CC1G :: Bit -- Capture/compare 1 generation + UG :: Bit -- Update generation + + CCMR1_Output 0x18 - capture/compare mode register 1 (output mode) + _ :: Bits 16 -- (Reserved) + OC2CE :: Bit -- OC2CE + OC2M :: Bits 3 -- OC2M + OC2PE :: Bit -- OC2PE + OC2FE :: Bit -- OC2FE + CC2S :: Bits 2 -- CC2S + OC1CE :: Bit -- OC1CE + OC1M :: Bits 3 -- OC1M + OC1PE :: Bit -- OC1PE + OC1FE :: Bit -- OC1FE + CC1S :: Bits 2 -- CC1S + + CCMR1_Input 0x18 - capture/compare mode register 1 (input mode) + _ :: Bits 16 -- (Reserved) + IC2F :: Bits 4 -- Input capture 2 filter + IC2PSC :: Bits 2 -- Input capture 2 prescaler + CC2S :: Bits 2 -- Capture/Compare 2 selection + IC1F :: Bits 4 -- Input capture 1 filter + IC1PSC :: Bits 2 -- Input capture 1 prescaler + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCMR2_Output 0x1c - capture/compare mode register 2 (output mode) + _ :: Bits 16 -- (Reserved) + OC4CE :: Bit -- O24CE + OC4M :: Bits 3 -- OC4M + OC4PE :: Bit -- OC4PE + OC4FE :: Bit -- OC4FE + CC4S :: Bits 2 -- CC4S + OC3CE :: Bit -- OC3CE + OC3M :: Bits 3 -- OC3M + OC3PE :: Bit -- OC3PE + OC3FE :: Bit -- OC3FE + CC3S :: Bits 2 -- CC3S + + CCMR2_Input 0x1c - capture/compare mode register 2 (input mode) + _ :: Bits 16 -- (Reserved) + IC4F :: Bits 4 -- Input capture 4 filter + IC4PSC :: Bits 2 -- Input capture 4 prescaler + CC4S :: Bits 2 -- Capture/Compare 4 selection + IC3F :: Bits 4 -- Input capture 3 filter + IC3PSC :: Bits 2 -- Input capture 3 prescaler + CC3S :: Bits 2 -- Capture/compare 3 selection + + CCER 0x20 - capture/compare enable register + _ :: Bits 16 -- (Reserved) + CC4NP :: Bit -- Capture/Compare 4 output Polarity + _ :: Bit -- (Reserved) + CC4P :: Bit -- Capture/Compare 3 output Polarity + CC4E :: Bit -- Capture/Compare 4 output enable + CC3NP :: Bit -- Capture/Compare 3 output Polarity + _ :: Bit -- (Reserved) + CC3P :: Bit -- Capture/Compare 3 output Polarity + CC3E :: Bit -- Capture/Compare 3 output enable + CC2NP :: Bit -- Capture/Compare 2 output Polarity + _ :: Bit -- (Reserved) + CC2P :: Bit -- Capture/Compare 2 output Polarity + CC2E :: Bit -- Capture/Compare 2 output enable + CC1NP :: Bit -- Capture/Compare 1 output Polarity + _ :: Bit -- (Reserved) + CC1P :: Bit -- Capture/Compare 1 output Polarity + CC1E :: Bit -- Capture/Compare 1 output enable + + CNT 0x24 - counter + _ :: Bits 16 -- (Reserved) + CNT :: Bits 16 -- Counter value + + PSC 0x28 - prescaler + _ :: Bits 16 -- (Reserved) + PSC :: Bits 16 -- Prescaler value + + ARR 0x2c - auto-reload register + _ :: Bits 16 -- (Reserved) + ARR :: Bits 16 -- Auto-reload value + + CCR1 0x34 - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + CCR2 0x38 - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + CCR3 0x3c - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + CCR4 0x40 - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + DCR 0x48 - DMA control register + _ :: Bits 19 -- (Reserved) + DBL :: Bits 5 -- DMA burst length + _ :: Bits 3 -- (Reserved) + DBA :: Bits 5 -- DMA base address + + DMAR 0x4c - DMA address for full transfer + _ :: Bits 16 -- (Reserved) + DMAB :: Bits 16 -- DMA register for burst accesses + + TIM4 0x40000800 + + Derived from TIM3 + + TIM5 0x40000c00 General-purpose-timers + + CR1 0x0 - control register 1 + _ :: Bits 22 -- (Reserved) + CKD :: Bits 2 -- Clock division + ARPE :: Bit -- Auto-reload preload enable + CMS :: Bits 2 -- Center-aligned mode selection + DIR :: Bit -- Direction + OPM :: Bit -- One-pulse mode + URS :: Bit -- Update request source + UDIS :: Bit -- Update disable + CEN :: Bit -- Counter enable + + CR2 0x4 - control register 2 + _ :: Bits 24 -- (Reserved) + TI1S :: Bit -- TI1 selection + MMS :: Bits 3 -- Master mode selection + CCDS :: Bit -- Capture/compare DMA selection + _ :: Bits 3 -- (Reserved) + + SMCR 0x8 - slave mode control register + _ :: Bits 16 -- (Reserved) + ETP :: Bit -- External trigger polarity + ECE :: Bit -- External clock enable + ETPS :: Bits 2 -- External trigger prescaler + ETF :: Bits 4 -- External trigger filter + MSM :: Bit -- Master/Slave mode + TS :: Bits 3 -- Trigger selection + _ :: Bit -- (Reserved) + SMS :: Bits 3 -- Slave mode selection + + DIER 0xc - DMA/Interrupt enable register + _ :: Bits 17 -- (Reserved) + TDE :: Bit -- Trigger DMA request enable + _ :: Bit -- (Reserved) + CC4DE :: Bit -- Capture/Compare 4 DMA request enable + CC3DE :: Bit -- Capture/Compare 3 DMA request enable + CC2DE :: Bit -- Capture/Compare 2 DMA request enable + CC1DE :: Bit -- Capture/Compare 1 DMA request enable + UDE :: Bit -- Update DMA request enable + _ :: Bit -- (Reserved) + TIE :: Bit -- Trigger interrupt enable + _ :: Bit -- (Reserved) + CC4IE :: Bit -- Capture/Compare 4 interrupt enable + CC3IE :: Bit -- Capture/Compare 3 interrupt enable + CC2IE :: Bit -- Capture/Compare 2 interrupt enable + CC1IE :: Bit -- Capture/Compare 1 interrupt enable + UIE :: Bit -- Update interrupt enable + + SR 0x10 - status register + _ :: Bits 19 -- (Reserved) + CC4OF :: Bit -- Capture/Compare 4 overcapture flag + CC3OF :: Bit -- Capture/Compare 3 overcapture flag + CC2OF :: Bit -- Capture/compare 2 overcapture flag + CC1OF :: Bit -- Capture/Compare 1 overcapture flag + _ :: Bits 2 -- (Reserved) + TIF :: Bit -- Trigger interrupt flag + _ :: Bit -- (Reserved) + CC4IF :: Bit -- Capture/Compare 4 interrupt flag + CC3IF :: Bit -- Capture/Compare 3 interrupt flag + CC2IF :: Bit -- Capture/Compare 2 interrupt flag + CC1IF :: Bit -- Capture/compare 1 interrupt flag + UIF :: Bit -- Update interrupt flag + + EGR 0x14 - event generation register + _ :: Bits 25 -- (Reserved) + TG :: Bit -- Trigger generation + _ :: Bit -- (Reserved) + CC4G :: Bit -- Capture/compare 4 generation + CC3G :: Bit -- Capture/compare 3 generation + CC2G :: Bit -- Capture/compare 2 generation + CC1G :: Bit -- Capture/compare 1 generation + UG :: Bit -- Update generation + + CCMR1_Output 0x18 - capture/compare mode register 1 (output mode) + _ :: Bits 16 -- (Reserved) + OC2CE :: Bit -- OC2CE + OC2M :: Bits 3 -- OC2M + OC2PE :: Bit -- OC2PE + OC2FE :: Bit -- OC2FE + CC2S :: Bits 2 -- CC2S + OC1CE :: Bit -- OC1CE + OC1M :: Bits 3 -- OC1M + OC1PE :: Bit -- OC1PE + OC1FE :: Bit -- OC1FE + CC1S :: Bits 2 -- CC1S + + CCMR1_Input 0x18 - capture/compare mode register 1 (input mode) + _ :: Bits 16 -- (Reserved) + IC2F :: Bits 4 -- Input capture 2 filter + IC2PSC :: Bits 2 -- Input capture 2 prescaler + CC2S :: Bits 2 -- Capture/Compare 2 selection + IC1F :: Bits 4 -- Input capture 1 filter + IC1PSC :: Bits 2 -- Input capture 1 prescaler + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCMR2_Output 0x1c - capture/compare mode register 2 (output mode) + _ :: Bits 16 -- (Reserved) + OC4CE :: Bit -- O24CE + OC4M :: Bits 3 -- OC4M + OC4PE :: Bit -- OC4PE + OC4FE :: Bit -- OC4FE + CC4S :: Bits 2 -- CC4S + OC3CE :: Bit -- OC3CE + OC3M :: Bits 3 -- OC3M + OC3PE :: Bit -- OC3PE + OC3FE :: Bit -- OC3FE + CC3S :: Bits 2 -- CC3S + + CCMR2_Input 0x1c - capture/compare mode register 2 (input mode) + _ :: Bits 16 -- (Reserved) + IC4F :: Bits 4 -- Input capture 4 filter + IC4PSC :: Bits 2 -- Input capture 4 prescaler + CC4S :: Bits 2 -- Capture/Compare 4 selection + IC3F :: Bits 4 -- Input capture 3 filter + IC3PSC :: Bits 2 -- Input capture 3 prescaler + CC3S :: Bits 2 -- Capture/compare 3 selection + + CCER 0x20 - capture/compare enable register + _ :: Bits 16 -- (Reserved) + CC4NP :: Bit -- Capture/Compare 4 output Polarity + _ :: Bit -- (Reserved) + CC4P :: Bit -- Capture/Compare 3 output Polarity + CC4E :: Bit -- Capture/Compare 4 output enable + CC3NP :: Bit -- Capture/Compare 3 output Polarity + _ :: Bit -- (Reserved) + CC3P :: Bit -- Capture/Compare 3 output Polarity + CC3E :: Bit -- Capture/Compare 3 output enable + CC2NP :: Bit -- Capture/Compare 2 output Polarity + _ :: Bit -- (Reserved) + CC2P :: Bit -- Capture/Compare 2 output Polarity + CC2E :: Bit -- Capture/Compare 2 output enable + CC1NP :: Bit -- Capture/Compare 1 output Polarity + _ :: Bit -- (Reserved) + CC1P :: Bit -- Capture/Compare 1 output Polarity + CC1E :: Bit -- Capture/Compare 1 output enable + + CNT 0x24 - counter + CNT :: Bits 32 -- Counter value + + PSC 0x28 - prescaler + _ :: Bits 16 -- (Reserved) + PSC :: Bits 16 -- Prescaler value + + ARR 0x2c - auto-reload register + ARR :: Bits 32 -- Auto-reload value + + CCR1 0x34 - capture/compare register + CCR :: Bits 32 -- Capture/Compare value + + CCR2 0x38 - capture/compare register + CCR :: Bits 32 -- Capture/Compare value + + CCR3 0x3c - capture/compare register + CCR :: Bits 32 -- Capture/Compare value + + CCR4 0x40 - capture/compare register + CCR :: Bits 32 -- Capture/Compare value + + DCR 0x48 - DMA control register + _ :: Bits 19 -- (Reserved) + DBL :: Bits 5 -- DMA burst length + _ :: Bits 3 -- (Reserved) + DBA :: Bits 5 -- DMA base address + + DMAR 0x4c - DMA address for full transfer + _ :: Bits 16 -- (Reserved) + DMAB :: Bits 16 -- DMA register for burst accesses + + OR 0x50 - TIM5 option register + _ :: Bits 24 -- (Reserved) + IT4_RMP :: Bits 2 -- Timer Input 4 remap + _ :: Bits 6 -- (Reserved) + + TIM6 0x40001000 Basic timers + + CR1 0x0 - control register 1 + _ :: Bits 24 -- (Reserved) + ARPE :: Bit -- Auto-reload preload enable + _ :: Bits 3 -- (Reserved) + OPM :: Bit -- One-pulse mode + URS :: Bit -- Update request source + UDIS :: Bit -- Update disable + CEN :: Bit -- Counter enable + + CR2 0x4 - control register 2 + _ :: Bits 25 -- (Reserved) + MMS :: Bits 3 -- Master mode selection + _ :: Bits 4 -- (Reserved) + + DIER 0xc - DMA/Interrupt enable register + _ :: Bits 23 -- (Reserved) + UDE :: Bit -- Update DMA request enable + _ :: Bits 7 -- (Reserved) + UIE :: Bit -- Update interrupt enable + + SR 0x10 - status register + _ :: Bits 31 -- (Reserved) + UIF :: Bit -- Update interrupt flag + + EGR 0x14 - event generation register + _ :: Bits 31 -- (Reserved) + UG :: Bit -- Update generation + + CNT 0x24 - counter + _ :: Bits 16 -- (Reserved) + CNT :: Bits 16 -- Low counter value + + PSC 0x28 - prescaler + _ :: Bits 16 -- (Reserved) + PSC :: Bits 16 -- Prescaler value + + ARR 0x2c - auto-reload register + _ :: Bits 16 -- (Reserved) + ARR :: Bits 16 -- Low Auto-reload value + + TIM7 0x40001400 + + Derived from TIM6 + + TIM12 0x40001800 + + Derived from TIM9 + + TIM13 0x40001c00 + + Derived from TIM10 + + TIM14 0x40002000 + + Derived from TIM10 + + RTC 0x40002800 Real-time clock + + TR 0x0 - time register + _ :: Bits 9 -- (Reserved) + PM :: Bit -- AM/PM notation + HT :: Bits 2 -- Hour tens in BCD format + HU :: Bits 4 -- Hour units in BCD format + _ :: Bit -- (Reserved) + MNT :: Bits 3 -- Minute tens in BCD format + MNU :: Bits 4 -- Minute units in BCD format + _ :: Bit -- (Reserved) + ST :: Bits 3 -- Second tens in BCD format + SU :: Bits 4 -- Second units in BCD format + + DR 0x4 - date register + _ :: Bits 8 -- (Reserved) + YT :: Bits 4 -- Year tens in BCD format + YU :: Bits 4 -- Year units in BCD format + WDU :: Bits 3 -- Week day units + MT :: Bit -- Month tens in BCD format + MU :: Bits 4 -- Month units in BCD format + _ :: Bits 2 -- (Reserved) + DT :: Bits 2 -- Date tens in BCD format + DU :: Bits 4 -- Date units in BCD format + + CR 0x8 - control register + _ :: Bits 8 -- (Reserved) + COE :: Bit -- Calibration output enable + OSEL :: Bits 2 -- Output selection + POL :: Bit -- Output polarity + COSEL :: Bit -- Calibration output selection + BKP :: Bit -- Backup + SUB1H :: Bit -- Subtract 1 hour (winter time change) + ADD1H :: Bit -- Add 1 hour (summer time change) + TSIE :: Bit -- Time-stamp interrupt enable + WUTIE :: Bit -- Wakeup timer interrupt enable + ALRBIE :: Bit -- Alarm B interrupt enable + ALRAIE :: Bit -- Alarm A interrupt enable + TSE :: Bit -- Time stamp enable + WUTE :: Bit -- Wakeup timer enable + ALRBE :: Bit -- Alarm B enable + ALRAE :: Bit -- Alarm A enable + DCE :: Bit -- Coarse digital calibration enable + FMT :: Bit -- Hour format + BYPSHAD :: Bit -- Bypass the shadow registers + REFCKON :: Bit -- Reference clock detection enable (50 or 60 Hz) + TSEDGE :: Bit -- Time-stamp event active edge + WUCKSEL :: Bits 3 -- Wakeup clock selection + + ISR 0xc - initialization and status register + _ :: Bits 15 -- (Reserved) + RECALPF :: Bit -- Recalibration pending Flag + _ :: Bit -- (Reserved) + TAMP2F :: Bit -- TAMPER2 detection flag + TAMP1F :: Bit -- Tamper detection flag + TSOVF :: Bit -- Time-stamp overflow flag + TSF :: Bit -- Time-stamp flag + WUTF :: Bit -- Wakeup timer flag + ALRBF :: Bit -- Alarm B flag + ALRAF :: Bit -- Alarm A flag + INIT :: Bit -- Initialization mode + INITF :: Bit -- Initialization flag + RSF :: Bit -- Registers synchronization flag + INITS :: Bit -- Initialization status flag + SHPF :: Bit -- Shift operation pending + WUTWF :: Bit -- Wakeup timer write flag + ALRBWF :: Bit -- Alarm B write flag + ALRAWF :: Bit -- Alarm A write flag + + PRER 0x10 - prescaler register + _ :: Bits 9 -- (Reserved) + PREDIV_A :: Bits 7 -- Asynchronous prescaler factor + _ :: Bit -- (Reserved) + PREDIV_S :: Bits 15 -- Synchronous prescaler factor + + WUTR 0x14 - wakeup timer register + _ :: Bits 16 -- (Reserved) + WUT :: Bits 16 -- Wakeup auto-reload value bits + + CALIBR 0x18 - calibration register + _ :: Bits 24 -- (Reserved) + DCS :: Bit -- Digital calibration sign + _ :: Bits 2 -- (Reserved) + DC :: Bits 5 -- Digital calibration + + ALRMAR 0x1c - Alarm A register + MSK4 :: Bit -- Alarm date mask + WDSEL :: Bit -- Week day selection + DT :: Bits 2 -- Date tens in BCD format + DU :: Bits 4 -- Date units or day in BCD format + MSK3 :: Bit -- Alarm hours mask + PM :: Bit -- AM/PM notation + HT :: Bits 2 -- Hour tens in BCD format + HU :: Bits 4 -- Hour units in BCD format + MSK2 :: Bit -- Alarm minutes mask + MNT :: Bits 3 -- Minute tens in BCD format + MNU :: Bits 4 -- Minute units in BCD format + MSK1 :: Bit -- Alarm seconds mask + ST :: Bits 3 -- Second tens in BCD format + SU :: Bits 4 -- Second units in BCD format + + ALRMBR 0x20 - Alarm B register + MSK4 :: Bit -- Alarm date mask + WDSEL :: Bit -- Week day selection + DT :: Bits 2 -- Date tens in BCD format + DU :: Bits 4 -- Date units or day in BCD format + MSK3 :: Bit -- Alarm hours mask + PM :: Bit -- AM/PM notation + HT :: Bits 2 -- Hour tens in BCD format + HU :: Bits 4 -- Hour units in BCD format + MSK2 :: Bit -- Alarm minutes mask + MNT :: Bits 3 -- Minute tens in BCD format + MNU :: Bits 4 -- Minute units in BCD format + MSK1 :: Bit -- Alarm seconds mask + ST :: Bits 3 -- Second tens in BCD format + SU :: Bits 4 -- Second units in BCD format + + WPR 0x24 - write protection register + _ :: Bits 24 -- (Reserved) + KEY :: Bits 8 -- Write protection key + + SSR 0x28 - sub second register + _ :: Bits 16 -- (Reserved) + SS :: Bits 16 -- Sub second value + + SHIFTR 0x2c - shift control register + ADD1S :: Bit -- Add one second + _ :: Bits 16 -- (Reserved) + SUBFS :: Bits 15 -- Subtract a fraction of a second + + CALR 0x3c - calibration register + _ :: Bits 16 -- (Reserved) + CALP :: Bit -- Increase frequency of RTC by 488.5 ppm + CALW8 :: Bit -- Use an 8-second calibration cycle period + CALW16 :: Bit -- Use a 16-second calibration cycle period + _ :: Bits 4 -- (Reserved) + CALM :: Bits 9 -- Calibration minus + + TAFCR 0x40 - tamper and alternate function configuration register + _ :: Bits 13 -- (Reserved) + ALARMOUTTYPE :: Bit -- AFO_ALARM output type + TSINSEL :: Bit -- TIMESTAMP mapping + TAMP1INSEL :: Bit -- TAMPER1 mapping + TAMPPUDIS :: Bit -- TAMPER pull-up disable + TAMPPRCH :: Bits 2 -- Tamper precharge duration + TAMPFLT :: Bits 2 -- Tamper filter count + TAMPFREQ :: Bits 3 -- Tamper sampling frequency + TAMPTS :: Bit -- Activate timestamp on tamper detection event + _ :: Bits 2 -- (Reserved) + TAMP2TRG :: Bit -- Active level for tamper 2 + TAMP2E :: Bit -- Tamper 2 detection enable + TAMPIE :: Bit -- Tamper interrupt enable + TAMP1TRG :: Bit -- Active level for tamper 1 + TAMP1E :: Bit -- Tamper 1 detection enable + + ALRMASSR 0x44 - Alarm A sub-second register + _ :: Bits 4 -- (Reserved) + MASKSS :: Bits 4 -- Mask the most-significant bits starting at this bit + _ :: Bits 9 -- (Reserved) + SS :: Bits 15 -- Sub seconds value + + ALRMBSSR 0x48 - Alarm B sub-second register + _ :: Bits 4 -- (Reserved) + MASKSS :: Bits 4 -- Mask the most-significant bits starting at this bit + _ :: Bits 9 -- (Reserved) + SS :: Bits 15 -- Sub seconds value + + BKP0R 0x50 - backup register + BKP :: Bits 32 -- BKP + + BKP1R 0x54 - backup register + BKP :: Bits 32 -- BKP + + BKP2R 0x58 - backup register + BKP :: Bits 32 -- BKP + + BKP3R 0x5c - backup register + BKP :: Bits 32 -- BKP + + BKP4R 0x60 - backup register + BKP :: Bits 32 -- BKP + + BKP5R 0x64 - backup register + BKP :: Bits 32 -- BKP + + BKP6R 0x68 - backup register + BKP :: Bits 32 -- BKP + + BKP7R 0x6c - backup register + BKP :: Bits 32 -- BKP + + BKP8R 0x70 - backup register + BKP :: Bits 32 -- BKP + + BKP9R 0x74 - backup register + BKP :: Bits 32 -- BKP + + BKP10R 0x78 - backup register + BKP :: Bits 32 -- BKP + + BKP11R 0x7c - backup register + BKP :: Bits 32 -- BKP + + BKP12R 0x80 - backup register + BKP :: Bits 32 -- BKP + + BKP13R 0x84 - backup register + BKP :: Bits 32 -- BKP + + BKP14R 0x88 - backup register + BKP :: Bits 32 -- BKP + + BKP15R 0x8c - backup register + BKP :: Bits 32 -- BKP + + BKP16R 0x90 - backup register + BKP :: Bits 32 -- BKP + + BKP17R 0x94 - backup register + BKP :: Bits 32 -- BKP + + BKP18R 0x98 - backup register + BKP :: Bits 32 -- BKP + + BKP19R 0x9c - backup register + BKP :: Bits 32 -- BKP + + WWDG 0x40002c00 Window watchdog + + CR 0x0 - Control register + _ :: Bits 24 -- (Reserved) + WDGA :: Bit -- Activation bit + T :: Bits 7 -- 7-bit counter (MSB to LSB) + + CFR 0x4 - Configuration register + _ :: Bits 22 -- (Reserved) + EWI :: Bit -- Early wakeup interrupt + WDGTB :: Bits 2 -- Timer base + W :: Bits 7 -- 7-bit window value + + SR 0x8 - Status register + _ :: Bits 31 -- (Reserved) + EWIF :: Bit -- Early wakeup interrupt flag + + IWDG 0x40003000 Independent watchdog + + KR 0x0 - Key register + _ :: Bits 16 -- (Reserved) + KEY :: Bits 16 -- Key value (write only, read 0000h) + + PR 0x4 - Prescaler register + _ :: Bits 29 -- (Reserved) + PR :: Bits 3 -- Prescaler divider + + RLR 0x8 - Reload register + _ :: Bits 20 -- (Reserved) + RL :: Bits 12 -- Watchdog counter reload value + + SR 0xc - Status register + _ :: Bits 30 -- (Reserved) + RVU :: Bit -- Watchdog counter reload value update + PVU :: Bit -- Watchdog prescaler value update + + I2S2ext 0x40003400 + + Derived from SPI1 + + SPI2 0x40003800 + + Derived from SPI1 + + SPI3 0x40003c00 + + Derived from SPI1 + + I2S3ext 0x40004000 + + Derived from SPI1 + + USART2 0x40004400 + + Derived from USART1 + + USART3 0x40004800 + + Derived from USART1 + + UART4 0x40004c00 Universal synchronous asynchronous receiver transmitter + + SR 0x0 - Status register + _ :: Bits 23 -- (Reserved) + LBD :: Bit -- LIN break detection flag + TXE :: Bit -- Transmit data register empty + TC :: Bit -- Transmission complete + RXNE :: Bit -- Read data register not empty + IDLE :: Bit -- IDLE line detected + ORE :: Bit -- Overrun error + NF :: Bit -- Noise detected flag + FE :: Bit -- Framing error + PE :: Bit -- Parity error + + DR 0x4 - Data register + _ :: Bits 23 -- (Reserved) + DR :: Bits 9 -- Data value + + BRR 0x8 - Baud rate register + _ :: Bits 16 -- (Reserved) + DIV_Mantissa :: Bits 12 -- mantissa of USARTDIV + DIV_Fraction :: Bits 4 -- fraction of USARTDIV + + CR1 0xc - Control register 1 + _ :: Bits 16 -- (Reserved) + OVER8 :: Bit -- Oversampling mode + _ :: Bit -- (Reserved) + UE :: Bit -- USART enable + M :: Bit -- Word length + WAKE :: Bit -- Wakeup method + PCE :: Bit -- Parity control enable + PS :: Bit -- Parity selection + PEIE :: Bit -- PE interrupt enable + TXEIE :: Bit -- TXE interrupt enable + TCIE :: Bit -- Transmission complete interrupt enable + RXNEIE :: Bit -- RXNE interrupt enable + IDLEIE :: Bit -- IDLE interrupt enable + TE :: Bit -- Transmitter enable + RE :: Bit -- Receiver enable + RWU :: Bit -- Receiver wakeup + SBK :: Bit -- Send break + + CR2 0x10 - Control register 2 + _ :: Bits 17 -- (Reserved) + LINEN :: Bit -- LIN mode enable + STOP :: Bits 2 -- STOP bits + _ :: Bits 5 -- (Reserved) + LBDIE :: Bit -- LIN break detection interrupt enable + LBDL :: Bit -- lin break detection length + _ :: Bit -- (Reserved) + ADD :: Bits 4 -- Address of the USART node + + CR3 0x14 - Control register 3 + _ :: Bits 20 -- (Reserved) + ONEBIT :: Bit -- One sample bit method enable + _ :: Bits 3 -- (Reserved) + DMAT :: Bit -- DMA enable transmitter + DMAR :: Bit -- DMA enable receiver + _ :: Bits 2 -- (Reserved) + HDSEL :: Bit -- Half-duplex selection + IRLP :: Bit -- IrDA low-power + IREN :: Bit -- IrDA mode enable + EIE :: Bit -- Error interrupt enable + + UART5 0x40005000 + + Derived from UART4 + + I2C1 0x40005400 Inter-integrated circuit + + CR1 0x0 - Control register 1 + _ :: Bits 16 -- (Reserved) + SWRST :: Bit -- Software reset + _ :: Bit -- (Reserved) + ALERT :: Bit -- SMBus alert + PEC :: Bit -- Packet error checking + POS :: Bit -- Acknowledge/PEC Position (for data reception) + ACK :: Bit -- Acknowledge enable + STOP :: Bit -- Stop generation + START :: Bit -- Start generation + NOSTRETCH :: Bit -- Clock stretching disable (Slave mode) + ENGC :: Bit -- General call enable + ENPEC :: Bit -- PEC enable + ENARP :: Bit -- ARP enable + SMBTYPE :: Bit -- SMBus type + _ :: Bit -- (Reserved) + SMBUS :: Bit -- SMBus mode + PE :: Bit -- Peripheral enable + + CR2 0x4 - Control register 2 + _ :: Bits 19 -- (Reserved) + LAST :: Bit -- DMA last transfer + DMAEN :: Bit -- DMA requests enable + ITBUFEN :: Bit -- Buffer interrupt enable + ITEVTEN :: Bit -- Event interrupt enable + ITERREN :: Bit -- Error interrupt enable + _ :: Bits 2 -- (Reserved) + FREQ :: Bits 6 -- Peripheral clock frequency + + OAR1 0x8 - Own address register 1 + _ :: Bits 16 -- (Reserved) + ADDMODE :: Bit -- Addressing mode (slave mode) + _ :: Bits 5 -- (Reserved) + ADD :: Bits 10 -- Interface address + + OAR2 0xc - Own address register 2 + _ :: Bits 24 -- (Reserved) + ADD2 :: Bits 7 -- Interface address + ENDUAL :: Bit -- Dual addressing mode enable + + DR 0x10 - Data register + _ :: Bits 24 -- (Reserved) + DR :: Bits 8 -- 8-bit data register + + SR1 0x14 - Status register 1 + _ :: Bits 16 -- (Reserved) + SMBALERT :: Bit -- SMBus alert + TIMEOUT :: Bit -- Timeout or Tlow error + _ :: Bit -- (Reserved) + PECERR :: Bit -- PEC Error in reception + OVR :: Bit -- Overrun/Underrun + AF :: Bit -- Acknowledge failure + ARLO :: Bit -- Arbitration lost (master mode) + BERR :: Bit -- Bus error + TxE :: Bit -- Data register empty (transmitters) + RxNE :: Bit -- Data register not empty (receivers) + _ :: Bit -- (Reserved) + STOPF :: Bit -- Stop detection (slave mode) + ADD10 :: Bit -- 10-bit header sent (Master mode) + BTF :: Bit -- Byte transfer finished + ADDR :: Bit -- Address sent (master mode)/matched (slave mode) + SB :: Bit -- Start bit (Master mode) + + SR2 0x18 - Status register 2 + _ :: Bits 16 -- (Reserved) + PEC :: Bits 8 -- acket error checking register + DUALF :: Bit -- Dual flag (Slave mode) + SMBHOST :: Bit -- SMBus host header (Slave mode) + SMBDEFAULT :: Bit -- SMBus device default address (Slave mode) + GENCALL :: Bit -- General call address (Slave mode) + _ :: Bit -- (Reserved) + TRA :: Bit -- Transmitter/receiver + BUSY :: Bit -- Bus busy + MSL :: Bit -- Master/slave + + CCR 0x1c - Clock control register + _ :: Bits 16 -- (Reserved) + F_S :: Bit -- I2C master mode selection + DUTY :: Bit -- Fast mode duty cycle + _ :: Bits 2 -- (Reserved) + CCR :: Bits 12 -- Clock control register in Fast/Standard mode (Master mode) + + TRISE 0x20 - TRISE register + _ :: Bits 26 -- (Reserved) + TRISE :: Bits 6 -- Maximum rise time in Fast/Standard mode (Master mode) + + I2C2 0x40005800 + + Derived from I2C1 + + I2C3 0x40005c00 + + Derived from I2C1 + + CAN1 0x40006400 Controller area network + + MCR 0x0 - master control register + _ :: Bits 15 -- (Reserved) + DBF :: Bit -- DBF + RESET :: Bit -- RESET + _ :: Bits 7 -- (Reserved) + TTCM :: Bit -- TTCM + ABOM :: Bit -- ABOM + AWUM :: Bit -- AWUM + NART :: Bit -- NART + RFLM :: Bit -- RFLM + TXFP :: Bit -- TXFP + SLEEP :: Bit -- SLEEP + INRQ :: Bit -- INRQ + + MSR 0x4 - master status register + _ :: Bits 20 -- (Reserved) + RX :: Bit -- RX + SAMP :: Bit -- SAMP + RXM :: Bit -- RXM + TXM :: Bit -- TXM + _ :: Bits 3 -- (Reserved) + SLAKI :: Bit -- SLAKI + WKUI :: Bit -- WKUI + ERRI :: Bit -- ERRI + SLAK :: Bit -- SLAK + INAK :: Bit -- INAK + + TSR 0x8 - transmit status register + LOW2 :: Bit -- Lowest priority flag for mailbox 2 + LOW1 :: Bit -- Lowest priority flag for mailbox 1 + LOW0 :: Bit -- Lowest priority flag for mailbox 0 + TME2 :: Bit -- Lowest priority flag for mailbox 2 + TME1 :: Bit -- Lowest priority flag for mailbox 1 + TME0 :: Bit -- Lowest priority flag for mailbox 0 + CODE :: Bits 2 -- CODE + ABRQ2 :: Bit -- ABRQ2 + _ :: Bits 3 -- (Reserved) + TERR2 :: Bit -- TERR2 + ALST2 :: Bit -- ALST2 + TXOK2 :: Bit -- TXOK2 + RQCP2 :: Bit -- RQCP2 + ABRQ1 :: Bit -- ABRQ1 + _ :: Bits 3 -- (Reserved) + TERR1 :: Bit -- TERR1 + ALST1 :: Bit -- ALST1 + TXOK1 :: Bit -- TXOK1 + RQCP1 :: Bit -- RQCP1 + ABRQ0 :: Bit -- ABRQ0 + _ :: Bits 3 -- (Reserved) + TERR0 :: Bit -- TERR0 + ALST0 :: Bit -- ALST0 + TXOK0 :: Bit -- TXOK0 + RQCP0 :: Bit -- RQCP0 + + RF0R 0xc - receive FIFO 0 register + _ :: Bits 26 -- (Reserved) + RFOM :: Bit -- RFOM0 + FOVR :: Bit -- FOVR0 + FULL :: Bit -- FULL0 + _ :: Bit -- (Reserved) + FMP :: Bits 2 -- FMP0 + + RF1R 0x10 - receive FIFO 1 register + _ :: Bits 26 -- (Reserved) + RFOM :: Bit -- RFOM0 + FOVR :: Bit -- FOVR0 + FULL :: Bit -- FULL0 + _ :: Bit -- (Reserved) + FMP :: Bits 2 -- FMP0 + + IER 0x14 - interrupt enable register + _ :: Bits 14 -- (Reserved) + SLKIE :: Bit -- SLKIE + WKUIE :: Bit -- WKUIE + ERRIE :: Bit -- ERRIE + _ :: Bits 3 -- (Reserved) + LECIE :: Bit -- LECIE + BOFIE :: Bit -- BOFIE + EPVIE :: Bit -- EPVIE + EWGIE :: Bit -- EWGIE + _ :: Bit -- (Reserved) + FOVIE1 :: Bit -- FOVIE1 + FFIE1 :: Bit -- FFIE1 + FMPIE1 :: Bit -- FMPIE1 + FOVIE0 :: Bit -- FOVIE0 + FFIE0 :: Bit -- FFIE0 + FMPIE0 :: Bit -- FMPIE0 + TMEIE :: Bit -- TMEIE + + ESR 0x18 - interrupt enable register + REC :: Bits 8 -- REC + TEC :: Bits 8 -- TEC + _ :: Bits 9 -- (Reserved) + LEC :: Bits 3 -- LEC + _ :: Bit -- (Reserved) + BOFF :: Bit -- BOFF + EPVF :: Bit -- EPVF + EWGF :: Bit -- EWGF + + BTR 0x1c - bit timing register + SILM :: Bit -- SILM + LBKM :: Bit -- LBKM + _ :: Bits 4 -- (Reserved) + SJW :: Bits 2 -- SJW + _ :: Bit -- (Reserved) + TS2 :: Bits 3 -- TS2 + TS1 :: Bits 4 -- TS1 + _ :: Bits 6 -- (Reserved) + BRP :: Bits 10 -- BRP + + TIR 0x180 - TX mailbox identifier register + STID :: Bits 11 -- STID + EXID :: Bits 18 -- EXID + IDE :: Bit -- IDE + RTR :: Bit -- RTR + TXRQ :: Bit -- TXRQ + + TDTR 0x184 - mailbox data length control and time stamp register + TIME :: Bits 16 -- TIME + _ :: Bits 7 -- (Reserved) + TGT :: Bit -- TGT + _ :: Bits 4 -- (Reserved) + DLC :: Bits 4 -- DLC + + TDLR 0x188 - mailbox data low register + DATA3 :: Bits 8 -- DATA3 + DATA2 :: Bits 8 -- DATA2 + DATA1 :: Bits 8 -- DATA1 + DATA0 :: Bits 8 -- DATA0 + + TDHR 0x18c - mailbox data high register + DATA7 :: Bits 8 -- DATA7 + DATA6 :: Bits 8 -- DATA6 + DATA5 :: Bits 8 -- DATA5 + DATA4 :: Bits 8 -- DATA4 + + TIR 0x190 - TX mailbox identifier register + STID :: Bits 11 -- STID + EXID :: Bits 18 -- EXID + IDE :: Bit -- IDE + RTR :: Bit -- RTR + TXRQ :: Bit -- TXRQ + + TDTR 0x194 - mailbox data length control and time stamp register + TIME :: Bits 16 -- TIME + _ :: Bits 7 -- (Reserved) + TGT :: Bit -- TGT + _ :: Bits 4 -- (Reserved) + DLC :: Bits 4 -- DLC + + TDLR 0x198 - mailbox data low register + DATA3 :: Bits 8 -- DATA3 + DATA2 :: Bits 8 -- DATA2 + DATA1 :: Bits 8 -- DATA1 + DATA0 :: Bits 8 -- DATA0 + + TDHR 0x19c - mailbox data high register + DATA7 :: Bits 8 -- DATA7 + DATA6 :: Bits 8 -- DATA6 + DATA5 :: Bits 8 -- DATA5 + DATA4 :: Bits 8 -- DATA4 + + TIR 0x1a0 - TX mailbox identifier register + STID :: Bits 11 -- STID + EXID :: Bits 18 -- EXID + IDE :: Bit -- IDE + RTR :: Bit -- RTR + TXRQ :: Bit -- TXRQ + + TDTR 0x1a4 - mailbox data length control and time stamp register + TIME :: Bits 16 -- TIME + _ :: Bits 7 -- (Reserved) + TGT :: Bit -- TGT + _ :: Bits 4 -- (Reserved) + DLC :: Bits 4 -- DLC + + TDLR 0x1a8 - mailbox data low register + DATA3 :: Bits 8 -- DATA3 + DATA2 :: Bits 8 -- DATA2 + DATA1 :: Bits 8 -- DATA1 + DATA0 :: Bits 8 -- DATA0 + + TDHR 0x1ac - mailbox data high register + DATA7 :: Bits 8 -- DATA7 + DATA6 :: Bits 8 -- DATA6 + DATA5 :: Bits 8 -- DATA5 + DATA4 :: Bits 8 -- DATA4 + + RIR 0x1b0 - receive FIFO mailbox identifier register + STID :: Bits 11 -- STID + EXID :: Bits 18 -- EXID + IDE :: Bit -- IDE + RTR :: Bit -- RTR + _ :: Bit -- (Reserved) + + RDTR 0x1b4 - mailbox data high register + TIME :: Bits 16 -- TIME + FMI :: Bits 8 -- FMI + _ :: Bits 4 -- (Reserved) + DLC :: Bits 4 -- DLC + + RDLR 0x1b8 - mailbox data high register + DATA3 :: Bits 8 -- DATA3 + DATA2 :: Bits 8 -- DATA2 + DATA1 :: Bits 8 -- DATA1 + DATA0 :: Bits 8 -- DATA0 + + RDHR 0x1bc - receive FIFO mailbox data high register + DATA7 :: Bits 8 -- DATA7 + DATA6 :: Bits 8 -- DATA6 + DATA5 :: Bits 8 -- DATA5 + DATA4 :: Bits 8 -- DATA4 + + RIR 0x1c0 - receive FIFO mailbox identifier register + STID :: Bits 11 -- STID + EXID :: Bits 18 -- EXID + IDE :: Bit -- IDE + RTR :: Bit -- RTR + _ :: Bit -- (Reserved) + + RDTR 0x1c4 - mailbox data high register + TIME :: Bits 16 -- TIME + FMI :: Bits 8 -- FMI + _ :: Bits 4 -- (Reserved) + DLC :: Bits 4 -- DLC + + RDLR 0x1c8 - mailbox data high register + DATA3 :: Bits 8 -- DATA3 + DATA2 :: Bits 8 -- DATA2 + DATA1 :: Bits 8 -- DATA1 + DATA0 :: Bits 8 -- DATA0 + + RDHR 0x1cc - receive FIFO mailbox data high register + DATA7 :: Bits 8 -- DATA7 + DATA6 :: Bits 8 -- DATA6 + DATA5 :: Bits 8 -- DATA5 + DATA4 :: Bits 8 -- DATA4 + + FMR 0x200 - filter master register + _ :: Bits 18 -- (Reserved) + CAN2SB :: Bits 6 -- CAN2SB + _ :: Bits 7 -- (Reserved) + FINIT :: Bit -- FINIT + + FM1R 0x204 - filter mode register + _ :: Bits 4 -- (Reserved) + FBM27 :: Bit -- Filter mode + FBM26 :: Bit -- Filter mode + FBM25 :: Bit -- Filter mode + FBM24 :: Bit -- Filter mode + FBM23 :: Bit -- Filter mode + FBM22 :: Bit -- Filter mode + FBM21 :: Bit -- Filter mode + FBM20 :: Bit -- Filter mode + FBM19 :: Bit -- Filter mode + FBM18 :: Bit -- Filter mode + FBM17 :: Bit -- Filter mode + FBM16 :: Bit -- Filter mode + FBM15 :: Bit -- Filter mode + FBM14 :: Bit -- Filter mode + FBM13 :: Bit -- Filter mode + FBM12 :: Bit -- Filter mode + FBM11 :: Bit -- Filter mode + FBM10 :: Bit -- Filter mode + FBM9 :: Bit -- Filter mode + FBM8 :: Bit -- Filter mode + FBM7 :: Bit -- Filter mode + FBM6 :: Bit -- Filter mode + FBM5 :: Bit -- Filter mode + FBM4 :: Bit -- Filter mode + FBM3 :: Bit -- Filter mode + FBM2 :: Bit -- Filter mode + FBM1 :: Bit -- Filter mode + FBM0 :: Bit -- Filter mode + + FS1R 0x20c - filter scale register + _ :: Bits 4 -- (Reserved) + FSC27 :: Bit -- Filter scale configuration + FSC26 :: Bit -- Filter scale configuration + FSC25 :: Bit -- Filter scale configuration + FSC24 :: Bit -- Filter scale configuration + FSC23 :: Bit -- Filter scale configuration + FSC22 :: Bit -- Filter scale configuration + FSC21 :: Bit -- Filter scale configuration + FSC20 :: Bit -- Filter scale configuration + FSC19 :: Bit -- Filter scale configuration + FSC18 :: Bit -- Filter scale configuration + FSC17 :: Bit -- Filter scale configuration + FSC16 :: Bit -- Filter scale configuration + FSC15 :: Bit -- Filter scale configuration + FSC14 :: Bit -- Filter scale configuration + FSC13 :: Bit -- Filter scale configuration + FSC12 :: Bit -- Filter scale configuration + FSC11 :: Bit -- Filter scale configuration + FSC10 :: Bit -- Filter scale configuration + FSC9 :: Bit -- Filter scale configuration + FSC8 :: Bit -- Filter scale configuration + FSC7 :: Bit -- Filter scale configuration + FSC6 :: Bit -- Filter scale configuration + FSC5 :: Bit -- Filter scale configuration + FSC4 :: Bit -- Filter scale configuration + FSC3 :: Bit -- Filter scale configuration + FSC2 :: Bit -- Filter scale configuration + FSC1 :: Bit -- Filter scale configuration + FSC0 :: Bit -- Filter scale configuration + + FFA1R 0x214 - filter FIFO assignment register + _ :: Bits 4 -- (Reserved) + FFA27 :: Bit -- Filter FIFO assignment for filter 27 + FFA26 :: Bit -- Filter FIFO assignment for filter 26 + FFA25 :: Bit -- Filter FIFO assignment for filter 25 + FFA24 :: Bit -- Filter FIFO assignment for filter 24 + FFA23 :: Bit -- Filter FIFO assignment for filter 23 + FFA22 :: Bit -- Filter FIFO assignment for filter 22 + FFA21 :: Bit -- Filter FIFO assignment for filter 21 + FFA20 :: Bit -- Filter FIFO assignment for filter 20 + FFA19 :: Bit -- Filter FIFO assignment for filter 19 + FFA18 :: Bit -- Filter FIFO assignment for filter 18 + FFA17 :: Bit -- Filter FIFO assignment for filter 17 + FFA16 :: Bit -- Filter FIFO assignment for filter 16 + FFA15 :: Bit -- Filter FIFO assignment for filter 15 + FFA14 :: Bit -- Filter FIFO assignment for filter 14 + FFA13 :: Bit -- Filter FIFO assignment for filter 13 + FFA12 :: Bit -- Filter FIFO assignment for filter 12 + FFA11 :: Bit -- Filter FIFO assignment for filter 11 + FFA10 :: Bit -- Filter FIFO assignment for filter 10 + FFA9 :: Bit -- Filter FIFO assignment for filter 9 + FFA8 :: Bit -- Filter FIFO assignment for filter 8 + FFA7 :: Bit -- Filter FIFO assignment for filter 7 + FFA6 :: Bit -- Filter FIFO assignment for filter 6 + FFA5 :: Bit -- Filter FIFO assignment for filter 5 + FFA4 :: Bit -- Filter FIFO assignment for filter 4 + FFA3 :: Bit -- Filter FIFO assignment for filter 3 + FFA2 :: Bit -- Filter FIFO assignment for filter 2 + FFA1 :: Bit -- Filter FIFO assignment for filter 1 + FFA0 :: Bit -- Filter FIFO assignment for filter 0 + + FA1R 0x21c - filter activation register + _ :: Bits 4 -- (Reserved) + FACT27 :: Bit -- Filter active + FACT26 :: Bit -- Filter active + FACT25 :: Bit -- Filter active + FACT24 :: Bit -- Filter active + FACT23 :: Bit -- Filter active + FACT22 :: Bit -- Filter active + FACT21 :: Bit -- Filter active + FACT20 :: Bit -- Filter active + FACT19 :: Bit -- Filter active + FACT18 :: Bit -- Filter active + FACT17 :: Bit -- Filter active + FACT16 :: Bit -- Filter active + FACT15 :: Bit -- Filter active + FACT14 :: Bit -- Filter active + FACT13 :: Bit -- Filter active + FACT12 :: Bit -- Filter active + FACT11 :: Bit -- Filter active + FACT10 :: Bit -- Filter active + FACT9 :: Bit -- Filter active + FACT8 :: Bit -- Filter active + FACT7 :: Bit -- Filter active + FACT6 :: Bit -- Filter active + FACT5 :: Bit -- Filter active + FACT4 :: Bit -- Filter active + FACT3 :: Bit -- Filter active + FACT2 :: Bit -- Filter active + FACT1 :: Bit -- Filter active + FACT0 :: Bit -- Filter active + + FR1 0x240 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x244 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x248 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x24c - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x250 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x254 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x258 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x25c - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x260 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x264 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x268 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x26c - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x270 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x274 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x278 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x27c - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x280 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x284 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x288 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x28c - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x290 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x294 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x298 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x29c - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2a0 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2a4 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2a8 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2ac - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2b0 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2b4 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2b8 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2bc - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2c0 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2c4 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2c8 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2cc - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2d0 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2d4 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2d8 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2dc - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2e0 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2e4 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2e8 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2ec - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2f0 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2f4 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x2f8 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x2fc - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x300 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x304 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x308 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x30c - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x310 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x314 - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + FR1 0x318 - Filter bank x register 1 + FB :: Bits 32 -- Filter bits + + FR2 0x31c - Filter bank x register 2 + FB :: Bits 32 -- Filter bits + + CAN2 0x40006800 + + Derived from CAN1 + + PWR 0x40007000 Power control + + CR 0x0 - power control register + _ :: Bits 22 -- (Reserved) + FPDS :: Bit -- Flash power down in Stop mode + DBP :: Bit -- Disable backup domain write protection + PLS :: Bits 3 -- PVD level selection + PVDE :: Bit -- Power voltage detector enable + CSBF :: Bit -- Clear standby flag + CWUF :: Bit -- Clear wakeup flag + PDDS :: Bit -- Power down deepsleep + LPDS :: Bit -- Low-power deep sleep + + CSR 0x4 - power control/status register + _ :: Bits 17 -- (Reserved) + VOSRDY :: Bit -- Regulator voltage scaling output selection ready bit + _ :: Bits 4 -- (Reserved) + BRE :: Bit -- Backup regulator enable + EWUP :: Bit -- Enable WKUP pin + _ :: Bits 4 -- (Reserved) + BRR :: Bit -- Backup regulator ready + PVDO :: Bit -- PVD output + SBF :: Bit -- Standby flag + WUF :: Bit -- Wakeup flag + + DAC 0x40007400 Digital-to-analog converter + + CR 0x0 - control register + _ :: Bits 2 -- (Reserved) + DMAUDRIE2 :: Bit -- DAC channel2 DMA underrun interrupt enable + DMAEN2 :: Bit -- DAC channel2 DMA enable + MAMP2 :: Bits 4 -- DAC channel2 mask/amplitude selector + WAVE2 :: Bits 2 -- DAC channel2 noise/triangle wave generation enable + TSEL2 :: Bits 3 -- DAC channel2 trigger selection + TEN2 :: Bit -- DAC channel2 trigger enable + BOFF2 :: Bit -- DAC channel2 output buffer disable + EN2 :: Bit -- DAC channel2 enable + _ :: Bits 2 -- (Reserved) + DMAUDRIE1 :: Bit -- DAC channel1 DMA Underrun Interrupt enable + DMAEN1 :: Bit -- DAC channel1 DMA enable + MAMP1 :: Bits 4 -- DAC channel1 mask/amplitude selector + WAVE1 :: Bits 2 -- DAC channel1 noise/triangle wave generation enable + TSEL1 :: Bits 3 -- DAC channel1 trigger selection + TEN1 :: Bit -- DAC channel1 trigger enable + BOFF1 :: Bit -- DAC channel1 output buffer disable + EN1 :: Bit -- DAC channel1 enable + + SWTRIGR 0x4 - software trigger register + _ :: Bits 30 -- (Reserved) + SWTRIG2 :: Bit -- DAC channel2 software trigger + SWTRIG1 :: Bit -- DAC channel1 software trigger + + DHR12R1 0x8 - channel1 12-bit right-aligned data holding register + _ :: Bits 20 -- (Reserved) + DACC1DHR :: Bits 12 -- DAC channel1 12-bit right-aligned data + + DHR12L1 0xc - channel1 12-bit left aligned data holding register + _ :: Bits 16 -- (Reserved) + DACC1DHR :: Bits 12 -- DAC channel1 12-bit left-aligned data + _ :: Bits 4 -- (Reserved) + + DHR8R1 0x10 - channel1 8-bit right aligned data holding register + _ :: Bits 24 -- (Reserved) + DACC1DHR :: Bits 8 -- DAC channel1 8-bit right-aligned data + + DHR12R2 0x14 - channel2 12-bit right aligned data holding register + _ :: Bits 20 -- (Reserved) + DACC2DHR :: Bits 12 -- DAC channel2 12-bit right-aligned data + + DHR12L2 0x18 - channel2 12-bit left aligned data holding register + _ :: Bits 16 -- (Reserved) + DACC2DHR :: Bits 12 -- DAC channel2 12-bit left-aligned data + _ :: Bits 4 -- (Reserved) + + DHR8R2 0x1c - channel2 8-bit right-aligned data holding register + _ :: Bits 24 -- (Reserved) + DACC2DHR :: Bits 8 -- DAC channel2 8-bit right-aligned data + + DHR12RD 0x20 - Dual DAC 12-bit right-aligned data holding register + _ :: Bits 4 -- (Reserved) + DACC2DHR :: Bits 12 -- DAC channel2 12-bit right-aligned data + _ :: Bits 4 -- (Reserved) + DACC1DHR :: Bits 12 -- DAC channel1 12-bit right-aligned data + + DHR12LD 0x24 - DUAL DAC 12-bit left aligned data holding register + DACC2DHR :: Bits 12 -- DAC channel2 12-bit left-aligned data + _ :: Bits 4 -- (Reserved) + DACC1DHR :: Bits 12 -- DAC channel1 12-bit left-aligned data + _ :: Bits 4 -- (Reserved) + + DHR8RD 0x28 - DUAL DAC 8-bit right aligned data holding register + _ :: Bits 16 -- (Reserved) + DACC2DHR :: Bits 8 -- DAC channel2 8-bit right-aligned data + DACC1DHR :: Bits 8 -- DAC channel1 8-bit right-aligned data + + DOR1 0x2c - channel1 data output register + _ :: Bits 20 -- (Reserved) + DACC1DOR :: Bits 12 -- DAC channel1 data output + + DOR2 0x30 - channel2 data output register + _ :: Bits 20 -- (Reserved) + DACC2DOR :: Bits 12 -- DAC channel2 data output + + SR 0x34 - status register + _ :: Bits 2 -- (Reserved) + DMAUDR2 :: Bit -- DAC channel2 DMA underrun flag + _ :: Bits 15 -- (Reserved) + DMAUDR1 :: Bit -- DAC channel1 DMA underrun flag + _ :: Bits 13 -- (Reserved) + + TIM1 0x40010000 Advanced-timers + + CR1 0x0 - control register 1 + _ :: Bits 22 -- (Reserved) + CKD :: Bits 2 -- Clock division + ARPE :: Bit -- Auto-reload preload enable + CMS :: Bits 2 -- Center-aligned mode selection + DIR :: Bit -- Direction + OPM :: Bit -- One-pulse mode + URS :: Bit -- Update request source + UDIS :: Bit -- Update disable + CEN :: Bit -- Counter enable + + CR2 0x4 - control register 2 + _ :: Bits 17 -- (Reserved) + OIS4 :: Bit -- Output Idle state 4 + OIS3N :: Bit -- Output Idle state 3 + OIS3 :: Bit -- Output Idle state 3 + OIS2N :: Bit -- Output Idle state 2 + OIS2 :: Bit -- Output Idle state 2 + OIS1N :: Bit -- Output Idle state 1 + OIS1 :: Bit -- Output Idle state 1 + TI1S :: Bit -- TI1 selection + MMS :: Bits 3 -- Master mode selection + CCDS :: Bit -- Capture/compare DMA selection + CCUS :: Bit -- Capture/compare control update selection + _ :: Bit -- (Reserved) + CCPC :: Bit -- Capture/compare preloaded control + + SMCR 0x8 - slave mode control register + _ :: Bits 16 -- (Reserved) + ETP :: Bit -- External trigger polarity + ECE :: Bit -- External clock enable + ETPS :: Bits 2 -- External trigger prescaler + ETF :: Bits 4 -- External trigger filter + MSM :: Bit -- Master/Slave mode + TS :: Bits 3 -- Trigger selection + _ :: Bit -- (Reserved) + SMS :: Bits 3 -- Slave mode selection + + DIER 0xc - DMA/Interrupt enable register + _ :: Bits 17 -- (Reserved) + TDE :: Bit -- Trigger DMA request enable + COMDE :: Bit -- COM DMA request enable + CC4DE :: Bit -- Capture/Compare 4 DMA request enable + CC3DE :: Bit -- Capture/Compare 3 DMA request enable + CC2DE :: Bit -- Capture/Compare 2 DMA request enable + CC1DE :: Bit -- Capture/Compare 1 DMA request enable + UDE :: Bit -- Update DMA request enable + BIE :: Bit -- Break interrupt enable + TIE :: Bit -- Trigger interrupt enable + COMIE :: Bit -- COM interrupt enable + CC4IE :: Bit -- Capture/Compare 4 interrupt enable + CC3IE :: Bit -- Capture/Compare 3 interrupt enable + CC2IE :: Bit -- Capture/Compare 2 interrupt enable + CC1IE :: Bit -- Capture/Compare 1 interrupt enable + UIE :: Bit -- Update interrupt enable + + SR 0x10 - status register + _ :: Bits 19 -- (Reserved) + CC4OF :: Bit -- Capture/Compare 4 overcapture flag + CC3OF :: Bit -- Capture/Compare 3 overcapture flag + CC2OF :: Bit -- Capture/compare 2 overcapture flag + CC1OF :: Bit -- Capture/Compare 1 overcapture flag + _ :: Bit -- (Reserved) + BIF :: Bit -- Break interrupt flag + TIF :: Bit -- Trigger interrupt flag + COMIF :: Bit -- COM interrupt flag + CC4IF :: Bit -- Capture/Compare 4 interrupt flag + CC3IF :: Bit -- Capture/Compare 3 interrupt flag + CC2IF :: Bit -- Capture/Compare 2 interrupt flag + CC1IF :: Bit -- Capture/compare 1 interrupt flag + UIF :: Bit -- Update interrupt flag + + EGR 0x14 - event generation register + _ :: Bits 24 -- (Reserved) + BG :: Bit -- Break generation + TG :: Bit -- Trigger generation + COMG :: Bit -- Capture/Compare control update generation + CC4G :: Bit -- Capture/compare 4 generation + CC3G :: Bit -- Capture/compare 3 generation + CC2G :: Bit -- Capture/compare 2 generation + CC1G :: Bit -- Capture/compare 1 generation + UG :: Bit -- Update generation + + CCMR1_Output 0x18 - capture/compare mode register 1 (output mode) + _ :: Bits 16 -- (Reserved) + OC2CE :: Bit -- Output Compare 2 clear enable + OC2M :: Bits 3 -- Output Compare 2 mode + OC2PE :: Bit -- Output Compare 2 preload enable + OC2FE :: Bit -- Output Compare 2 fast enable + CC2S :: Bits 2 -- Capture/Compare 2 selection + OC1CE :: Bit -- Output Compare 1 clear enable + OC1M :: Bits 3 -- Output Compare 1 mode + OC1PE :: Bit -- Output Compare 1 preload enable + OC1FE :: Bit -- Output Compare 1 fast enable + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCMR1_Input 0x18 - capture/compare mode register 1 (input mode) + _ :: Bits 16 -- (Reserved) + IC2F :: Bits 4 -- Input capture 2 filter + IC2PSC :: Bits 2 -- Input capture 2 prescaler + CC2S :: Bits 2 -- Capture/Compare 2 selection + IC1F :: Bits 4 -- Input capture 1 filter + IC1PSC :: Bits 2 -- Input capture 1 prescaler + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCMR2_Output 0x1c - capture/compare mode register 2 (output mode) + _ :: Bits 16 -- (Reserved) + OC4CE :: Bit -- Output compare 4 clear enable + OC4M :: Bits 3 -- Output compare 4 mode + OC4PE :: Bit -- Output compare 4 preload enable + OC4FE :: Bit -- Output compare 4 fast enable + CC4S :: Bits 2 -- Capture/Compare 4 selection + OC3CE :: Bit -- Output compare 3 clear enable + OC3M :: Bits 3 -- Output compare 3 mode + OC3PE :: Bit -- Output compare 3 preload enable + OC3FE :: Bit -- Output compare 3 fast enable + CC3S :: Bits 2 -- Capture/Compare 3 selection + + CCMR2_Input 0x1c - capture/compare mode register 2 (input mode) + _ :: Bits 16 -- (Reserved) + IC4F :: Bits 4 -- Input capture 4 filter + IC4PSC :: Bits 2 -- Input capture 4 prescaler + CC4S :: Bits 2 -- Capture/Compare 4 selection + IC3F :: Bits 4 -- Input capture 3 filter + IC3PSC :: Bits 2 -- Input capture 3 prescaler + CC3S :: Bits 2 -- Capture/compare 3 selection + + CCER 0x20 - capture/compare enable register + _ :: Bits 18 -- (Reserved) + CC4P :: Bit -- Capture/Compare 3 output Polarity + CC4E :: Bit -- Capture/Compare 4 output enable + CC3NP :: Bit -- Capture/Compare 3 output Polarity + CC3NE :: Bit -- Capture/Compare 3 complementary output enable + CC3P :: Bit -- Capture/Compare 3 output Polarity + CC3E :: Bit -- Capture/Compare 3 output enable + CC2NP :: Bit -- Capture/Compare 2 output Polarity + CC2NE :: Bit -- Capture/Compare 2 complementary output enable + CC2P :: Bit -- Capture/Compare 2 output Polarity + CC2E :: Bit -- Capture/Compare 2 output enable + CC1NP :: Bit -- Capture/Compare 1 output Polarity + CC1NE :: Bit -- Capture/Compare 1 complementary output enable + CC1P :: Bit -- Capture/Compare 1 output Polarity + CC1E :: Bit -- Capture/Compare 1 output enable + + CNT 0x24 - counter + _ :: Bits 16 -- (Reserved) + CNT :: Bits 16 -- counter value + + PSC 0x28 - prescaler + _ :: Bits 16 -- (Reserved) + PSC :: Bits 16 -- Prescaler value + + ARR 0x2c - auto-reload register + _ :: Bits 16 -- (Reserved) + ARR :: Bits 16 -- Auto-reload value + + RCR 0x30 - repetition counter register + _ :: Bits 24 -- (Reserved) + REP :: Bits 8 -- Repetition counter value + + CCR1 0x34 - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + CCR2 0x38 - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + CCR3 0x3c - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + CCR4 0x40 - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + BDTR 0x44 - break and dead-time register + _ :: Bits 16 -- (Reserved) + MOE :: Bit -- Main output enable + AOE :: Bit -- Automatic output enable + BKP :: Bit -- Break polarity + BKE :: Bit -- Break enable + OSSR :: Bit -- Off-state selection for Run mode + OSSI :: Bit -- Off-state selection for Idle mode + LOCK :: Bits 2 -- Lock configuration + DTG :: Bits 8 -- Dead-time generator setup + + DCR 0x48 - DMA control register + _ :: Bits 19 -- (Reserved) + DBL :: Bits 5 -- DMA burst length + _ :: Bits 3 -- (Reserved) + DBA :: Bits 5 -- DMA base address + + DMAR 0x4c - DMA address for full transfer + _ :: Bits 16 -- (Reserved) + DMAB :: Bits 16 -- DMA register for burst accesses + + TIM8 0x40010400 + + Derived from TIM1 + + USART1 0x40011000 Universal synchronous asynchronous receiver transmitter + + SR 0x0 - Status register + _ :: Bits 22 -- (Reserved) + CTS :: Bit -- CTS flag + LBD :: Bit -- LIN break detection flag + TXE :: Bit -- Transmit data register empty + TC :: Bit -- Transmission complete + RXNE :: Bit -- Read data register not empty + IDLE :: Bit -- IDLE line detected + ORE :: Bit -- Overrun error + NF :: Bit -- Noise detected flag + FE :: Bit -- Framing error + PE :: Bit -- Parity error + + DR 0x4 - Data register + _ :: Bits 23 -- (Reserved) + DR :: Bits 9 -- Data value + + BRR 0x8 - Baud rate register + _ :: Bits 16 -- (Reserved) + DIV_Mantissa :: Bits 12 -- mantissa of USARTDIV + DIV_Fraction :: Bits 4 -- fraction of USARTDIV + + CR1 0xc - Control register 1 + _ :: Bits 16 -- (Reserved) + OVER8 :: Bit -- Oversampling mode + _ :: Bit -- (Reserved) + UE :: Bit -- USART enable + M :: Bit -- Word length + WAKE :: Bit -- Wakeup method + PCE :: Bit -- Parity control enable + PS :: Bit -- Parity selection + PEIE :: Bit -- PE interrupt enable + TXEIE :: Bit -- TXE interrupt enable + TCIE :: Bit -- Transmission complete interrupt enable + RXNEIE :: Bit -- RXNE interrupt enable + IDLEIE :: Bit -- IDLE interrupt enable + TE :: Bit -- Transmitter enable + RE :: Bit -- Receiver enable + RWU :: Bit -- Receiver wakeup + SBK :: Bit -- Send break + + CR2 0x10 - Control register 2 + _ :: Bits 17 -- (Reserved) + LINEN :: Bit -- LIN mode enable + STOP :: Bits 2 -- STOP bits + CLKEN :: Bit -- Clock enable + CPOL :: Bit -- Clock polarity + CPHA :: Bit -- Clock phase + LBCL :: Bit -- Last bit clock pulse + _ :: Bit -- (Reserved) + LBDIE :: Bit -- LIN break detection interrupt enable + LBDL :: Bit -- lin break detection length + _ :: Bit -- (Reserved) + ADD :: Bits 4 -- Address of the USART node + + CR3 0x14 - Control register 3 + _ :: Bits 20 -- (Reserved) + ONEBIT :: Bit -- One sample bit method enable + CTSIE :: Bit -- CTS interrupt enable + CTSE :: Bit -- CTS enable + RTSE :: Bit -- RTS enable + DMAT :: Bit -- DMA enable transmitter + DMAR :: Bit -- DMA enable receiver + SCEN :: Bit -- Smartcard mode enable + NACK :: Bit -- Smartcard NACK enable + HDSEL :: Bit -- Half-duplex selection + IRLP :: Bit -- IrDA low-power + IREN :: Bit -- IrDA mode enable + EIE :: Bit -- Error interrupt enable + + GTPR 0x18 - Guard time and prescaler register + _ :: Bits 16 -- (Reserved) + GT :: Bits 8 -- Guard time value + PSC :: Bits 8 -- Prescaler value + + USART6 0x40011400 + + Derived from USART1 + + ADC1 0x40012000 Analog-to-digital converter + + SR 0x0 - status register + _ :: Bits 26 -- (Reserved) + OVR :: Bit -- Overrun + STRT :: Bit -- Regular channel start flag + JSTRT :: Bit -- Injected channel start flag + JEOC :: Bit -- Injected channel end of conversion + EOC :: Bit -- Regular channel end of conversion + AWD :: Bit -- Analog watchdog flag + + CR1 0x4 - control register 1 + _ :: Bits 5 -- (Reserved) + OVRIE :: Bit -- Overrun interrupt enable + RES :: Bits 2 -- Resolution + AWDEN :: Bit -- Analog watchdog enable on regular channels + JAWDEN :: Bit -- Analog watchdog enable on injected channels + _ :: Bits 6 -- (Reserved) + DISCNUM :: Bits 3 -- Discontinuous mode channel count + JDISCEN :: Bit -- Discontinuous mode on injected channels + DISCEN :: Bit -- Discontinuous mode on regular channels + JAUTO :: Bit -- Automatic injected group conversion + AWDSGL :: Bit -- Enable the watchdog on a single channel in scan mode + SCAN :: Bit -- Scan mode + JEOCIE :: Bit -- Interrupt enable for injected channels + AWDIE :: Bit -- Analog watchdog interrupt enable + EOCIE :: Bit -- Interrupt enable for EOC + AWDCH :: Bits 5 -- Analog watchdog channel select bits + + CR2 0x8 - control register 2 + _ :: Bit -- (Reserved) + SWSTART :: Bit -- Start conversion of regular channels + EXTEN :: Bits 2 -- External trigger enable for regular channels + EXTSEL :: Bits 4 -- External event select for regular group + _ :: Bit -- (Reserved) + JSWSTART :: Bit -- Start conversion of injected channels + JEXTEN :: Bits 2 -- External trigger enable for injected channels + JEXTSEL :: Bits 4 -- External event select for injected group + _ :: Bits 4 -- (Reserved) + ALIGN :: Bit -- Data alignment + EOCS :: Bit -- End of conversion selection + DDS :: Bit -- DMA disable selection (for single ADC mode) + DMA :: Bit -- Direct memory access mode (for single ADC mode) + _ :: Bits 6 -- (Reserved) + CONT :: Bit -- Continuous conversion + ADON :: Bit -- A/D Converter ON / OFF + + SMPR1 0xc - sample time register 1 + _ :: Bits 5 -- (Reserved) + SMP18 :: Bits 3 -- Channel 18 sampling time selection + SMP17 :: Bits 3 -- Channel 17 sampling time selection + SMP16 :: Bits 3 -- Channel 16 sampling time selection + SMP15 :: Bits 3 -- Channel 15 sampling time selection + SMP14 :: Bits 3 -- Channel 14 sampling time selection + SMP13 :: Bits 3 -- Channel 13 sampling time selection + SMP12 :: Bits 3 -- Channel 12 sampling time selection + SMP11 :: Bits 3 -- Channel 11 sampling time selection + SMP10 :: Bits 3 -- Channel 10 sampling time selection + + SMPR2 0x10 - sample time register 2 + _ :: Bits 2 -- (Reserved) + SMP9 :: Bits 3 -- Channel 9 sampling time selection + SMP8 :: Bits 3 -- Channel 8 sampling time selection + SMP7 :: Bits 3 -- Channel 7 sampling time selection + SMP6 :: Bits 3 -- Channel 6 sampling time selection + SMP5 :: Bits 3 -- Channel 5 sampling time selection + SMP4 :: Bits 3 -- Channel 4 sampling time selection + SMP3 :: Bits 3 -- Channel 3 sampling time selection + SMP2 :: Bits 3 -- Channel 2 sampling time selection + SMP1 :: Bits 3 -- Channel 1 sampling time selection + SMP0 :: Bits 3 -- Channel 0 sampling time selection + + JOFR1 0x14 - injected channel data offset register x + _ :: Bits 20 -- (Reserved) + JOFFSET :: Bits 12 -- Data offset for injected channel x + + JOFR2 0x18 - injected channel data offset register x + _ :: Bits 20 -- (Reserved) + JOFFSET :: Bits 12 -- Data offset for injected channel x + + JOFR3 0x1c - injected channel data offset register x + _ :: Bits 20 -- (Reserved) + JOFFSET :: Bits 12 -- Data offset for injected channel x + + JOFR4 0x20 - injected channel data offset register x + _ :: Bits 20 -- (Reserved) + JOFFSET :: Bits 12 -- Data offset for injected channel x + + HTR 0x24 - watchdog higher threshold register + _ :: Bits 20 -- (Reserved) + HT :: Bits 12 -- Analog watchdog higher threshold + + LTR 0x28 - watchdog lower threshold register + _ :: Bits 20 -- (Reserved) + LT :: Bits 12 -- Analog watchdog lower threshold + + SQR1 0x2c - regular sequence register 1 + _ :: Bits 8 -- (Reserved) + L :: Bits 4 -- Regular channel sequence length + SQ16 :: Bits 5 -- 16th conversion in regular sequence + SQ15 :: Bits 5 -- 15th conversion in regular sequence + SQ14 :: Bits 5 -- 14th conversion in regular sequence + SQ13 :: Bits 5 -- 13th conversion in regular sequence + + SQR2 0x30 - regular sequence register 2 + _ :: Bits 2 -- (Reserved) + SQ12 :: Bits 5 -- 12th conversion in regular sequence + SQ11 :: Bits 5 -- 11th conversion in regular sequence + SQ10 :: Bits 5 -- 10th conversion in regular sequence + SQ9 :: Bits 5 -- 9th conversion in regular sequence + SQ8 :: Bits 5 -- 8th conversion in regular sequence + SQ7 :: Bits 5 -- 7th conversion in regular sequence + + SQR3 0x34 - regular sequence register 3 + _ :: Bits 2 -- (Reserved) + SQ6 :: Bits 5 -- 6th conversion in regular sequence + SQ5 :: Bits 5 -- 5th conversion in regular sequence + SQ4 :: Bits 5 -- 4th conversion in regular sequence + SQ3 :: Bits 5 -- 3rd conversion in regular sequence + SQ2 :: Bits 5 -- 2nd conversion in regular sequence + SQ1 :: Bits 5 -- 1st conversion in regular sequence + + JSQR 0x38 - injected sequence register + _ :: Bits 10 -- (Reserved) + JL :: Bits 2 -- Injected sequence length + JSQ4 :: Bits 5 -- 4th conversion in injected sequence + JSQ3 :: Bits 5 -- 3rd conversion in injected sequence + JSQ2 :: Bits 5 -- 2nd conversion in injected sequence + JSQ1 :: Bits 5 -- 1st conversion in injected sequence + + JDR1 0x3c - injected data register x + _ :: Bits 16 -- (Reserved) + JDATA :: Bits 16 -- Injected data + + JDR2 0x40 - injected data register x + _ :: Bits 16 -- (Reserved) + JDATA :: Bits 16 -- Injected data + + JDR3 0x44 - injected data register x + _ :: Bits 16 -- (Reserved) + JDATA :: Bits 16 -- Injected data + + JDR4 0x48 - injected data register x + _ :: Bits 16 -- (Reserved) + JDATA :: Bits 16 -- Injected data + + DR 0x4c - regular data register + _ :: Bits 16 -- (Reserved) + DATA :: Bits 16 -- Regular data + + ADC2 0x40012100 + + Derived from ADC1 + + ADC3 0x40012200 + + Derived from ADC1 + + ADC_Common 0x40012300 Common ADC registers + + CSR 0x0 - ADC Common status register + _ :: Bits 10 -- (Reserved) + OVR3 :: Bit -- Overrun flag of ADC3 + STRT3 :: Bit -- Regular channel Start flag of ADC 3 + JSTRT3 :: Bit -- Injected channel Start flag of ADC 3 + JEOC3 :: Bit -- Injected channel end of conversion of ADC 3 + EOC3 :: Bit -- End of conversion of ADC 3 + AWD3 :: Bit -- Analog watchdog flag of ADC 3 + _ :: Bits 2 -- (Reserved) + OVR2 :: Bit -- Overrun flag of ADC 2 + STRT2 :: Bit -- Regular channel Start flag of ADC 2 + JSTRT2 :: Bit -- Injected channel Start flag of ADC 2 + JEOC2 :: Bit -- Injected channel end of conversion of ADC 2 + EOC2 :: Bit -- End of conversion of ADC 2 + AWD2 :: Bit -- Analog watchdog flag of ADC 2 + _ :: Bits 2 -- (Reserved) + OVR1 :: Bit -- Overrun flag of ADC 1 + STRT1 :: Bit -- Regular channel Start flag of ADC 1 + JSTRT1 :: Bit -- Injected channel Start flag of ADC 1 + JEOC1 :: Bit -- Injected channel end of conversion of ADC 1 + EOC1 :: Bit -- End of conversion of ADC 1 + AWD1 :: Bit -- Analog watchdog flag of ADC 1 + + CCR 0x4 - ADC common control register + _ :: Bits 8 -- (Reserved) + TSVREFE :: Bit -- Temperature sensor and VREFINT enable + VBATE :: Bit -- VBAT enable + _ :: Bits 4 -- (Reserved) + ADCPRE :: Bits 2 -- ADC prescaler + DMA :: Bits 2 -- Direct memory access mode for multi ADC mode + DDS :: Bit -- DMA disable selection for multi-ADC mode + _ :: Bit -- (Reserved) + DELAY :: Bits 4 -- Delay between 2 sampling phases + _ :: Bits 3 -- (Reserved) + MULTI :: Bits 5 -- Multi ADC mode selection + + CDR 0x8 - ADC common regular data register for dual and triple modes + DATA2 :: Bits 16 -- 2nd data item of a pair of regular conversions + DATA1 :: Bits 16 -- 1st data item of a pair of regular conversions + + SDIO 0x40012c00 Secure digital input/output interface + + POWER 0x0 - power control register + _ :: Bits 30 -- (Reserved) + PWRCTRL :: Bits 2 -- PWRCTRL + + CLKCR 0x4 - SDI clock control register + _ :: Bits 17 -- (Reserved) + HWFC_EN :: Bit -- HW Flow Control enable + NEGEDGE :: Bit -- SDIO_CK dephasing selection bit + WIDBUS :: Bits 2 -- Wide bus mode enable bit + BYPASS :: Bit -- Clock divider bypass enable bit + PWRSAV :: Bit -- Power saving configuration bit + CLKEN :: Bit -- Clock enable bit + CLKDIV :: Bits 8 -- Clock divide factor + + ARG 0x8 - argument register + CMDARG :: Bits 32 -- Command argument + + CMD 0xc - command register + _ :: Bits 17 -- (Reserved) + CE_ATACMD :: Bit -- CE-ATA command + nIEN :: Bit -- not Interrupt Enable + ENCMDcompl :: Bit -- Enable CMD completion + SDIOSuspend :: Bit -- SD I/O suspend command + CPSMEN :: Bit -- Command path state machine (CPSM) Enable bit + WAITPEND :: Bit -- CPSM Waits for ends of data transfer (CmdPend internal signal). + WAITINT :: Bit -- CPSM waits for interrupt request + WAITRESP :: Bits 2 -- Wait for response bits + CMDINDEX :: Bits 6 -- Command index + + RESPCMD 0x10 - command response register + _ :: Bits 26 -- (Reserved) + RESPCMD :: Bits 6 -- Response command index + + RESP1 0x14 - SDIO response 1 register + CARDSTATUS :: Bits 32 -- Status of a card, which is part of the received response + + RESP2 0x18 - SDIO response 2 register + CARDSTATUS :: Bits 32 -- Status of a card, which is part of the received response + + RESP3 0x1c - SDIO response 3 register + CARDSTATUS :: Bits 32 -- Status of a card, which is part of the received response + + RESP4 0x20 - SDIO response 4 register + CARDSTATUS :: Bits 32 -- Status of a card, which is part of the received response + + DTIMER 0x24 - data timer register + DATATIME :: Bits 32 -- Data timeout period + + DLEN 0x28 - data length register + _ :: Bits 7 -- (Reserved) + DATALENGTH :: Bits 25 -- Data length value + + DCTRL 0x2c - data control register + _ :: Bits 20 -- (Reserved) + SDIOEN :: Bit -- SD I/O enable functions + RWMOD :: Bit -- Read wait mode + RWSTOP :: Bit -- Read wait stop + RWSTART :: Bit -- Read wait start + DBLOCKSIZE :: Bits 4 -- Data block size + DMAEN :: Bit -- DMA enable bit + DTMODE :: Bit -- Data transfer mode selection 1: Stream or SDIO multibyte data transfer. + DTDIR :: Bit -- Data transfer direction selection + DTEN :: Bit -- DTEN + + DCOUNT 0x30 - data counter register + _ :: Bits 7 -- (Reserved) + DATACOUNT :: Bits 25 -- Data count value + + STA 0x34 - status register + _ :: Bits 8 -- (Reserved) + CEATAEND :: Bit -- CE-ATA command completion signal received for CMD61 + SDIOIT :: Bit -- SDIO interrupt received + RXDAVL :: Bit -- Data available in receive FIFO + TXDAVL :: Bit -- Data available in transmit FIFO + RXFIFOE :: Bit -- Receive FIFO empty + TXFIFOE :: Bit -- Transmit FIFO empty + RXFIFOF :: Bit -- Receive FIFO full + TXFIFOF :: Bit -- Transmit FIFO full + RXFIFOHF :: Bit -- Receive FIFO half full: there are at least 8 words in the FIFO + TXFIFOHE :: Bit -- Transmit FIFO half empty: at least 8 words can be written into the FIFO + RXACT :: Bit -- Data receive in progress + TXACT :: Bit -- Data transmit in progress + CMDACT :: Bit -- Command transfer in progress + DBCKEND :: Bit -- Data block sent/received (CRC check passed) + STBITERR :: Bit -- Start bit not detected on all data signals in wide bus mode + DATAEND :: Bit -- Data end (data counter, SDIDCOUNT, is zero) + CMDSENT :: Bit -- Command sent (no response required) + CMDREND :: Bit -- Command response received (CRC check passed) + RXOVERR :: Bit -- Received FIFO overrun error + TXUNDERR :: Bit -- Transmit FIFO underrun error + DTIMEOUT :: Bit -- Data timeout + CTIMEOUT :: Bit -- Command response timeout + DCRCFAIL :: Bit -- Data block sent/received (CRC check failed) + CCRCFAIL :: Bit -- Command response received (CRC check failed) + + ICR 0x38 - interrupt clear register + _ :: Bits 8 -- (Reserved) + CEATAENDC :: Bit -- CEATAEND flag clear bit + SDIOITC :: Bit -- SDIOIT flag clear bit + _ :: Bits 11 -- (Reserved) + DBCKENDC :: Bit -- DBCKEND flag clear bit + STBITERRC :: Bit -- STBITERR flag clear bit + DATAENDC :: Bit -- DATAEND flag clear bit + CMDSENTC :: Bit -- CMDSENT flag clear bit + CMDRENDC :: Bit -- CMDREND flag clear bit + RXOVERRC :: Bit -- RXOVERR flag clear bit + TXUNDERRC :: Bit -- TXUNDERR flag clear bit + DTIMEOUTC :: Bit -- DTIMEOUT flag clear bit + CTIMEOUTC :: Bit -- CTIMEOUT flag clear bit + DCRCFAILC :: Bit -- DCRCFAIL flag clear bit + CCRCFAILC :: Bit -- CCRCFAIL flag clear bit + + MASK 0x3c - mask register + _ :: Bits 8 -- (Reserved) + CEATAENDIE :: Bit -- CE-ATA command completion signal received interrupt enable + SDIOITIE :: Bit -- SDIO mode interrupt received interrupt enable + RXDAVLIE :: Bit -- Data available in Rx FIFO interrupt enable + TXDAVLIE :: Bit -- Data available in Tx FIFO interrupt enable + RXFIFOEIE :: Bit -- Rx FIFO empty interrupt enable + TXFIFOEIE :: Bit -- Tx FIFO empty interrupt enable + RXFIFOFIE :: Bit -- Rx FIFO full interrupt enable + TXFIFOFIE :: Bit -- Tx FIFO full interrupt enable + RXFIFOHFIE :: Bit -- Rx FIFO half full interrupt enable + TXFIFOHEIE :: Bit -- Tx FIFO half empty interrupt enable + RXACTIE :: Bit -- Data receive acting interrupt enable + TXACTIE :: Bit -- Data transmit acting interrupt enable + CMDACTIE :: Bit -- Command acting interrupt enable + DBCKENDIE :: Bit -- Data block end interrupt enable + STBITERRIE :: Bit -- Start bit error interrupt enable + DATAENDIE :: Bit -- Data end interrupt enable + CMDSENTIE :: Bit -- Command sent interrupt enable + CMDRENDIE :: Bit -- Command response received interrupt enable + RXOVERRIE :: Bit -- Rx FIFO overrun error interrupt enable + TXUNDERRIE :: Bit -- Tx FIFO underrun error interrupt enable + DTIMEOUTIE :: Bit -- Data timeout interrupt enable + CTIMEOUTIE :: Bit -- Command timeout interrupt enable + DCRCFAILIE :: Bit -- Data CRC fail interrupt enable + CCRCFAILIE :: Bit -- Command CRC fail interrupt enable + + FIFOCNT 0x48 - FIFO counter register + _ :: Bits 8 -- (Reserved) + FIFOCOUNT :: Bits 24 -- Remaining number of words to be written to or read from the FIFO. + + FIFO 0x80 - data FIFO register + FIFOData :: Bits 32 -- Receive and transmit FIFO data + + SPI1 0x40013000 Serial peripheral interface + + CR1 0x0 - control register 1 + _ :: Bits 16 -- (Reserved) + BIDIMODE :: Bit -- Bidirectional data mode enable + BIDIOE :: Bit -- Output enable in bidirectional mode + CRCEN :: Bit -- Hardware CRC calculation enable + CRCNEXT :: Bit -- CRC transfer next + DFF :: Bit -- Data frame format + RXONLY :: Bit -- Receive only + SSM :: Bit -- Software slave management + SSI :: Bit -- Internal slave select + LSBFIRST :: Bit -- Frame format + SPE :: Bit -- SPI enable + BR :: Bits 3 -- Baud rate control + MSTR :: Bit -- Master selection + CPOL :: Bit -- Clock polarity + CPHA :: Bit -- Clock phase + + CR2 0x4 - control register 2 + _ :: Bits 24 -- (Reserved) + TXEIE :: Bit -- Tx buffer empty interrupt enable + RXNEIE :: Bit -- RX buffer not empty interrupt enable + ERRIE :: Bit -- Error interrupt enable + FRF :: Bit -- Frame format + _ :: Bit -- (Reserved) + SSOE :: Bit -- SS output enable + TXDMAEN :: Bit -- Tx buffer DMA enable + RXDMAEN :: Bit -- Rx buffer DMA enable + + SR 0x8 - status register + _ :: Bits 23 -- (Reserved) + FRE :: Bit -- TI frame format error + BSY :: Bit -- Busy flag + OVR :: Bit -- Overrun flag + MODF :: Bit -- Mode fault + CRCERR :: Bit -- CRC error flag + UDR :: Bit -- Underrun flag + CHSIDE :: Bit -- Channel side + TXE :: Bit -- Transmit buffer empty + RXNE :: Bit -- Receive buffer not empty + + DR 0xc - data register + _ :: Bits 16 -- (Reserved) + DR :: Bits 16 -- Data register + + CRCPR 0x10 - CRC polynomial register + _ :: Bits 16 -- (Reserved) + CRCPOLY :: Bits 16 -- CRC polynomial register + + RXCRCR 0x14 - RX CRC register + _ :: Bits 16 -- (Reserved) + RxCRC :: Bits 16 -- Rx CRC register + + TXCRCR 0x18 - TX CRC register + _ :: Bits 16 -- (Reserved) + TxCRC :: Bits 16 -- Tx CRC register + + I2SCFGR 0x1c - I2S configuration register + _ :: Bits 20 -- (Reserved) + I2SMOD :: Bit -- I2S mode selection + I2SE :: Bit -- I2S Enable + I2SCFG :: Bits 2 -- I2S configuration mode + PCMSYNC :: Bit -- PCM frame synchronization + _ :: Bit -- (Reserved) + I2SSTD :: Bits 2 -- I2S standard selection + CKPOL :: Bit -- Steady state clock polarity + DATLEN :: Bits 2 -- Data length to be transferred + CHLEN :: Bit -- Channel length (number of bits per audio channel) + + I2SPR 0x20 - I2S prescaler register + _ :: Bits 22 -- (Reserved) + MCKOE :: Bit -- Master clock output enable + ODD :: Bit -- Odd factor for the prescaler + I2SDIV :: Bits 8 -- I2S Linear prescaler + + SPI4 0x40013400 + + Derived from SPI1 + + SYSCFG 0x40013800 System configuration controller + + MEMRM 0x0 - memory remap register + _ :: Bits 30 -- (Reserved) + MEM_MODE :: Bits 2 -- MEM_MODE + + EXTICR1 0x8 - external interrupt configuration register 1 + _ :: Bits 16 -- (Reserved) + EXTI3 :: Bits 4 -- EXTI x configuration (x = 0 to 3) + EXTI2 :: Bits 4 -- EXTI x configuration (x = 0 to 3) + EXTI1 :: Bits 4 -- EXTI x configuration (x = 0 to 3) + EXTI0 :: Bits 4 -- EXTI x configuration (x = 0 to 3) + + EXTICR2 0xc - external interrupt configuration register 2 + _ :: Bits 16 -- (Reserved) + EXTI7 :: Bits 4 -- EXTI x configuration (x = 4 to 7) + EXTI6 :: Bits 4 -- EXTI x configuration (x = 4 to 7) + EXTI5 :: Bits 4 -- EXTI x configuration (x = 4 to 7) + EXTI4 :: Bits 4 -- EXTI x configuration (x = 4 to 7) + + EXTICR3 0x10 - external interrupt configuration register 3 + _ :: Bits 16 -- (Reserved) + EXTI11 :: Bits 4 -- EXTI x configuration (x = 8 to 11) + EXTI10 :: Bits 4 -- EXTI10 + EXTI9 :: Bits 4 -- EXTI x configuration (x = 8 to 11) + EXTI8 :: Bits 4 -- EXTI x configuration (x = 8 to 11) + + EXTICR4 0x14 - external interrupt configuration register 4 + _ :: Bits 16 -- (Reserved) + EXTI15 :: Bits 4 -- EXTI x configuration (x = 12 to 15) + EXTI14 :: Bits 4 -- EXTI x configuration (x = 12 to 15) + EXTI13 :: Bits 4 -- EXTI x configuration (x = 12 to 15) + EXTI12 :: Bits 4 -- EXTI x configuration (x = 12 to 15) + + CMPCR 0x20 - Compensation cell control register + _ :: Bits 23 -- (Reserved) + READY :: Bit -- READY + _ :: Bits 7 -- (Reserved) + CMP_PD :: Bit -- Compensation cell power-down + + EXTI 0x40013c00 External interrupt/event controller + + IMR 0x0 - Interrupt mask register (EXTI_IMR) + _ :: Bits 9 -- (Reserved) + MR22 :: Bit -- Interrupt Mask on line 22 + MR21 :: Bit -- Interrupt Mask on line 21 + MR20 :: Bit -- Interrupt Mask on line 20 + MR19 :: Bit -- Interrupt Mask on line 19 + MR18 :: Bit -- Interrupt Mask on line 18 + MR17 :: Bit -- Interrupt Mask on line 17 + MR16 :: Bit -- Interrupt Mask on line 16 + MR15 :: Bit -- Interrupt Mask on line 15 + MR14 :: Bit -- Interrupt Mask on line 14 + MR13 :: Bit -- Interrupt Mask on line 13 + MR12 :: Bit -- Interrupt Mask on line 12 + MR11 :: Bit -- Interrupt Mask on line 11 + MR10 :: Bit -- Interrupt Mask on line 10 + MR9 :: Bit -- Interrupt Mask on line 9 + MR8 :: Bit -- Interrupt Mask on line 8 + MR7 :: Bit -- Interrupt Mask on line 7 + MR6 :: Bit -- Interrupt Mask on line 6 + MR5 :: Bit -- Interrupt Mask on line 5 + MR4 :: Bit -- Interrupt Mask on line 4 + MR3 :: Bit -- Interrupt Mask on line 3 + MR2 :: Bit -- Interrupt Mask on line 2 + MR1 :: Bit -- Interrupt Mask on line 1 + MR0 :: Bit -- Interrupt Mask on line 0 + + EMR 0x4 - Event mask register (EXTI_EMR) + _ :: Bits 9 -- (Reserved) + MR22 :: Bit -- Event Mask on line 22 + MR21 :: Bit -- Event Mask on line 21 + MR20 :: Bit -- Event Mask on line 20 + MR19 :: Bit -- Event Mask on line 19 + MR18 :: Bit -- Event Mask on line 18 + MR17 :: Bit -- Event Mask on line 17 + MR16 :: Bit -- Event Mask on line 16 + MR15 :: Bit -- Event Mask on line 15 + MR14 :: Bit -- Event Mask on line 14 + MR13 :: Bit -- Event Mask on line 13 + MR12 :: Bit -- Event Mask on line 12 + MR11 :: Bit -- Event Mask on line 11 + MR10 :: Bit -- Event Mask on line 10 + MR9 :: Bit -- Event Mask on line 9 + MR8 :: Bit -- Event Mask on line 8 + MR7 :: Bit -- Event Mask on line 7 + MR6 :: Bit -- Event Mask on line 6 + MR5 :: Bit -- Event Mask on line 5 + MR4 :: Bit -- Event Mask on line 4 + MR3 :: Bit -- Event Mask on line 3 + MR2 :: Bit -- Event Mask on line 2 + MR1 :: Bit -- Event Mask on line 1 + MR0 :: Bit -- Event Mask on line 0 + + RTSR 0x8 - Rising Trigger selection register (EXTI_RTSR) + _ :: Bits 9 -- (Reserved) + TR22 :: Bit -- Rising trigger event configuration of line 22 + TR21 :: Bit -- Rising trigger event configuration of line 21 + TR20 :: Bit -- Rising trigger event configuration of line 20 + TR19 :: Bit -- Rising trigger event configuration of line 19 + TR18 :: Bit -- Rising trigger event configuration of line 18 + TR17 :: Bit -- Rising trigger event configuration of line 17 + TR16 :: Bit -- Rising trigger event configuration of line 16 + TR15 :: Bit -- Rising trigger event configuration of line 15 + TR14 :: Bit -- Rising trigger event configuration of line 14 + TR13 :: Bit -- Rising trigger event configuration of line 13 + TR12 :: Bit -- Rising trigger event configuration of line 12 + TR11 :: Bit -- Rising trigger event configuration of line 11 + TR10 :: Bit -- Rising trigger event configuration of line 10 + TR9 :: Bit -- Rising trigger event configuration of line 9 + TR8 :: Bit -- Rising trigger event configuration of line 8 + TR7 :: Bit -- Rising trigger event configuration of line 7 + TR6 :: Bit -- Rising trigger event configuration of line 6 + TR5 :: Bit -- Rising trigger event configuration of line 5 + TR4 :: Bit -- Rising trigger event configuration of line 4 + TR3 :: Bit -- Rising trigger event configuration of line 3 + TR2 :: Bit -- Rising trigger event configuration of line 2 + TR1 :: Bit -- Rising trigger event configuration of line 1 + TR0 :: Bit -- Rising trigger event configuration of line 0 + + FTSR 0xc - Falling Trigger selection register (EXTI_FTSR) + _ :: Bits 9 -- (Reserved) + TR22 :: Bit -- Falling trigger event configuration of line 22 + TR21 :: Bit -- Falling trigger event configuration of line 21 + TR20 :: Bit -- Falling trigger event configuration of line 20 + TR19 :: Bit -- Falling trigger event configuration of line 19 + TR18 :: Bit -- Falling trigger event configuration of line 18 + TR17 :: Bit -- Falling trigger event configuration of line 17 + TR16 :: Bit -- Falling trigger event configuration of line 16 + TR15 :: Bit -- Falling trigger event configuration of line 15 + TR14 :: Bit -- Falling trigger event configuration of line 14 + TR13 :: Bit -- Falling trigger event configuration of line 13 + TR12 :: Bit -- Falling trigger event configuration of line 12 + TR11 :: Bit -- Falling trigger event configuration of line 11 + TR10 :: Bit -- Falling trigger event configuration of line 10 + TR9 :: Bit -- Falling trigger event configuration of line 9 + TR8 :: Bit -- Falling trigger event configuration of line 8 + TR7 :: Bit -- Falling trigger event configuration of line 7 + TR6 :: Bit -- Falling trigger event configuration of line 6 + TR5 :: Bit -- Falling trigger event configuration of line 5 + TR4 :: Bit -- Falling trigger event configuration of line 4 + TR3 :: Bit -- Falling trigger event configuration of line 3 + TR2 :: Bit -- Falling trigger event configuration of line 2 + TR1 :: Bit -- Falling trigger event configuration of line 1 + TR0 :: Bit -- Falling trigger event configuration of line 0 + + SWIER 0x10 - Software interrupt event register (EXTI_SWIER) + _ :: Bits 9 -- (Reserved) + SWIER22 :: Bit -- Software Interrupt on line 22 + SWIER21 :: Bit -- Software Interrupt on line 21 + SWIER20 :: Bit -- Software Interrupt on line 20 + SWIER19 :: Bit -- Software Interrupt on line 19 + SWIER18 :: Bit -- Software Interrupt on line 18 + SWIER17 :: Bit -- Software Interrupt on line 17 + SWIER16 :: Bit -- Software Interrupt on line 16 + SWIER15 :: Bit -- Software Interrupt on line 15 + SWIER14 :: Bit -- Software Interrupt on line 14 + SWIER13 :: Bit -- Software Interrupt on line 13 + SWIER12 :: Bit -- Software Interrupt on line 12 + SWIER11 :: Bit -- Software Interrupt on line 11 + SWIER10 :: Bit -- Software Interrupt on line 10 + SWIER9 :: Bit -- Software Interrupt on line 9 + SWIER8 :: Bit -- Software Interrupt on line 8 + SWIER7 :: Bit -- Software Interrupt on line 7 + SWIER6 :: Bit -- Software Interrupt on line 6 + SWIER5 :: Bit -- Software Interrupt on line 5 + SWIER4 :: Bit -- Software Interrupt on line 4 + SWIER3 :: Bit -- Software Interrupt on line 3 + SWIER2 :: Bit -- Software Interrupt on line 2 + SWIER1 :: Bit -- Software Interrupt on line 1 + SWIER0 :: Bit -- Software Interrupt on line 0 + + PR 0x14 - Pending register (EXTI_PR) + _ :: Bits 9 -- (Reserved) + PR22 :: Bit -- Pending bit 22 + PR21 :: Bit -- Pending bit 21 + PR20 :: Bit -- Pending bit 20 + PR19 :: Bit -- Pending bit 19 + PR18 :: Bit -- Pending bit 18 + PR17 :: Bit -- Pending bit 17 + PR16 :: Bit -- Pending bit 16 + PR15 :: Bit -- Pending bit 15 + PR14 :: Bit -- Pending bit 14 + PR13 :: Bit -- Pending bit 13 + PR12 :: Bit -- Pending bit 12 + PR11 :: Bit -- Pending bit 11 + PR10 :: Bit -- Pending bit 10 + PR9 :: Bit -- Pending bit 9 + PR8 :: Bit -- Pending bit 8 + PR7 :: Bit -- Pending bit 7 + PR6 :: Bit -- Pending bit 6 + PR5 :: Bit -- Pending bit 5 + PR4 :: Bit -- Pending bit 4 + PR3 :: Bit -- Pending bit 3 + PR2 :: Bit -- Pending bit 2 + PR1 :: Bit -- Pending bit 1 + PR0 :: Bit -- Pending bit 0 + + TIM9 0x40014000 General purpose timers + + CR1 0x0 - control register 1 + _ :: Bits 22 -- (Reserved) + CKD :: Bits 2 -- Clock division + ARPE :: Bit -- Auto-reload preload enable + _ :: Bits 3 -- (Reserved) + OPM :: Bit -- One-pulse mode + URS :: Bit -- Update request source + UDIS :: Bit -- Update disable + CEN :: Bit -- Counter enable + + CR2 0x4 - control register 2 + _ :: Bits 25 -- (Reserved) + MMS :: Bits 3 -- Master mode selection + _ :: Bits 4 -- (Reserved) + + SMCR 0x8 - slave mode control register + _ :: Bits 24 -- (Reserved) + MSM :: Bit -- Master/Slave mode + TS :: Bits 3 -- Trigger selection + _ :: Bit -- (Reserved) + SMS :: Bits 3 -- Slave mode selection + + DIER 0xc - DMA/Interrupt enable register + _ :: Bits 25 -- (Reserved) + TIE :: Bit -- Trigger interrupt enable + _ :: Bits 3 -- (Reserved) + CC2IE :: Bit -- Capture/Compare 2 interrupt enable + CC1IE :: Bit -- Capture/Compare 1 interrupt enable + UIE :: Bit -- Update interrupt enable + + SR 0x10 - status register + _ :: Bits 21 -- (Reserved) + CC2OF :: Bit -- Capture/compare 2 overcapture flag + CC1OF :: Bit -- Capture/Compare 1 overcapture flag + _ :: Bits 2 -- (Reserved) + TIF :: Bit -- Trigger interrupt flag + _ :: Bits 3 -- (Reserved) + CC2IF :: Bit -- Capture/Compare 2 interrupt flag + CC1IF :: Bit -- Capture/compare 1 interrupt flag + UIF :: Bit -- Update interrupt flag + + EGR 0x14 - event generation register + _ :: Bits 25 -- (Reserved) + TG :: Bit -- Trigger generation + _ :: Bits 3 -- (Reserved) + CC2G :: Bit -- Capture/compare 2 generation + CC1G :: Bit -- Capture/compare 1 generation + UG :: Bit -- Update generation + + CCMR1_Output 0x18 - capture/compare mode register 1 (output mode) + _ :: Bits 17 -- (Reserved) + OC2M :: Bits 3 -- Output Compare 2 mode + OC2PE :: Bit -- Output Compare 2 preload enable + OC2FE :: Bit -- Output Compare 2 fast enable + CC2S :: Bits 2 -- Capture/Compare 2 selection + _ :: Bit -- (Reserved) + OC1M :: Bits 3 -- Output Compare 1 mode + OC1PE :: Bit -- Output Compare 1 preload enable + OC1FE :: Bit -- Output Compare 1 fast enable + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCMR1_Input 0x18 - capture/compare mode register 1 (input mode) + _ :: Bits 17 -- (Reserved) + IC2F :: Bits 3 -- Input capture 2 filter + IC2PSC :: Bits 2 -- Input capture 2 prescaler + CC2S :: Bits 2 -- Capture/Compare 2 selection + _ :: Bit -- (Reserved) + IC1F :: Bits 3 -- Input capture 1 filter + IC1PSC :: Bits 2 -- Input capture 1 prescaler + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCER 0x20 - capture/compare enable register + _ :: Bits 24 -- (Reserved) + CC2NP :: Bit -- Capture/Compare 2 output Polarity + _ :: Bit -- (Reserved) + CC2P :: Bit -- Capture/Compare 2 output Polarity + CC2E :: Bit -- Capture/Compare 2 output enable + CC1NP :: Bit -- Capture/Compare 1 output Polarity + _ :: Bit -- (Reserved) + CC1P :: Bit -- Capture/Compare 1 output Polarity + CC1E :: Bit -- Capture/Compare 1 output enable + + CNT 0x24 - counter + _ :: Bits 16 -- (Reserved) + CNT :: Bits 16 -- counter value + + PSC 0x28 - prescaler + _ :: Bits 16 -- (Reserved) + PSC :: Bits 16 -- Prescaler value + + ARR 0x2c - auto-reload register + _ :: Bits 16 -- (Reserved) + ARR :: Bits 16 -- Auto-reload value + + CCR1 0x34 - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + CCR2 0x38 - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + TIM10 0x40014400 General-purpose-timers + + CR1 0x0 - control register 1 + _ :: Bits 22 -- (Reserved) + CKD :: Bits 2 -- Clock division + ARPE :: Bit -- Auto-reload preload enable + _ :: Bits 3 -- (Reserved) + OPM :: Bit -- One-pulse mode + URS :: Bit -- Update request source + UDIS :: Bit -- Update disable + CEN :: Bit -- Counter enable + + DIER 0xc - DMA/Interrupt enable register + _ :: Bits 30 -- (Reserved) + CC1IE :: Bit -- Capture/Compare 1 interrupt enable + UIE :: Bit -- Update interrupt enable + + SR 0x10 - status register + _ :: Bits 22 -- (Reserved) + CC1OF :: Bit -- Capture/Compare 1 overcapture flag + _ :: Bits 7 -- (Reserved) + CC1IF :: Bit -- Capture/compare 1 interrupt flag + UIF :: Bit -- Update interrupt flag + + EGR 0x14 - event generation register + _ :: Bits 30 -- (Reserved) + CC1G :: Bit -- Capture/compare 1 generation + UG :: Bit -- Update generation + + CCMR1_Output 0x18 - capture/compare mode register 1 (output mode) + _ :: Bits 25 -- (Reserved) + OC1M :: Bits 3 -- Output Compare 1 mode + OC1PE :: Bit -- Output Compare 1 preload enable + OC1FE :: Bit -- Output Compare 1 fast enable + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCMR1_Input 0x18 - capture/compare mode register 1 (input mode) + _ :: Bits 24 -- (Reserved) + IC1F :: Bits 4 -- Input capture 1 filter + IC1PSC :: Bits 2 -- Input capture 1 prescaler + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCER 0x20 - capture/compare enable register + _ :: Bits 28 -- (Reserved) + CC1NP :: Bit -- Capture/Compare 1 output Polarity + _ :: Bit -- (Reserved) + CC1P :: Bit -- Capture/Compare 1 output Polarity + CC1E :: Bit -- Capture/Compare 1 output enable + + CNT 0x24 - counter + _ :: Bits 16 -- (Reserved) + CNT :: Bits 16 -- counter value + + PSC 0x28 - prescaler + _ :: Bits 16 -- (Reserved) + PSC :: Bits 16 -- Prescaler value + + ARR 0x2c - auto-reload register + _ :: Bits 16 -- (Reserved) + ARR :: Bits 16 -- Auto-reload value + + CCR1 0x34 - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + TIM11 0x40014800 General-purpose-timers + + CR1 0x0 - control register 1 + _ :: Bits 22 -- (Reserved) + CKD :: Bits 2 -- Clock division + ARPE :: Bit -- Auto-reload preload enable + _ :: Bits 3 -- (Reserved) + OPM :: Bit -- One-pulse mode + URS :: Bit -- Update request source + UDIS :: Bit -- Update disable + CEN :: Bit -- Counter enable + + DIER 0xc - DMA/Interrupt enable register + _ :: Bits 30 -- (Reserved) + CC1IE :: Bit -- Capture/Compare 1 interrupt enable + UIE :: Bit -- Update interrupt enable + + SR 0x10 - status register + _ :: Bits 22 -- (Reserved) + CC1OF :: Bit -- Capture/Compare 1 overcapture flag + _ :: Bits 7 -- (Reserved) + CC1IF :: Bit -- Capture/compare 1 interrupt flag + UIF :: Bit -- Update interrupt flag + + EGR 0x14 - event generation register + _ :: Bits 30 -- (Reserved) + CC1G :: Bit -- Capture/compare 1 generation + UG :: Bit -- Update generation + + CCMR1_Output 0x18 - capture/compare mode register 1 (output mode) + _ :: Bits 25 -- (Reserved) + OC1M :: Bits 3 -- Output Compare 1 mode + OC1PE :: Bit -- Output Compare 1 preload enable + OC1FE :: Bit -- Output Compare 1 fast enable + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCMR1_Input 0x18 - capture/compare mode register 1 (input mode) + _ :: Bits 24 -- (Reserved) + IC1F :: Bits 4 -- Input capture 1 filter + IC1PSC :: Bits 2 -- Input capture 1 prescaler + CC1S :: Bits 2 -- Capture/Compare 1 selection + + CCER 0x20 - capture/compare enable register + _ :: Bits 28 -- (Reserved) + CC1NP :: Bit -- Capture/Compare 1 output Polarity + _ :: Bit -- (Reserved) + CC1P :: Bit -- Capture/Compare 1 output Polarity + CC1E :: Bit -- Capture/Compare 1 output enable + + CNT 0x24 - counter + _ :: Bits 16 -- (Reserved) + CNT :: Bits 16 -- counter value + + PSC 0x28 - prescaler + _ :: Bits 16 -- (Reserved) + PSC :: Bits 16 -- Prescaler value + + ARR 0x2c - auto-reload register + _ :: Bits 16 -- (Reserved) + ARR :: Bits 16 -- Auto-reload value + + CCR1 0x34 - capture/compare register + _ :: Bits 16 -- (Reserved) + CCR :: Bits 16 -- Capture/Compare value + + OR 0x50 - option register + _ :: Bits 30 -- (Reserved) + RMP :: Bits 2 -- Input 1 remapping capability + + SPI5 0x40015000 + + Derived from SPI1 + + SPI6 0x40015400 + + Derived from SPI1 + + SAI1 0x40015800 Serial audio interface + + CR1 0x4 - SAI AConfiguration register 1 + _ :: Bits 8 -- (Reserved) + MCKDIV :: Bits 4 -- Master clock divider + NODIV :: Bit -- No divider + _ :: Bit -- (Reserved) + DMAEN :: Bit -- DMA enable + SAIEN :: Bit -- Audio block enable + _ :: Bits 2 -- (Reserved) + OUTDRIV :: Bit -- Output drive + MONO :: Bit -- Mono mode + SYNCEN :: Bits 2 -- Synchronization enable + CKSTR :: Bit -- Clock strobing edge + LSBFIRST :: Bit -- Least significant bit first + DS :: Bits 3 -- Data size + _ :: Bit -- (Reserved) + PRTCFG :: Bits 2 -- Protocol configuration + MODE :: Bits 2 -- Audio block mode + + CR2 0x8 - SAI AConfiguration register 2 + _ :: Bits 16 -- (Reserved) + COMP :: Bits 2 -- Companding mode + CPL :: Bit -- Complement bit + MUTECNT :: Bits 6 -- Mute counter + MUTEVAL :: Bit -- Mute value + MUTE :: Bit -- Mute + TRIS :: Bit -- Tristate management on data line + FFLUSH :: Bit -- FIFO flush + FTH :: Bits 3 -- FIFO threshold + + FRCR 0xc - SAI AFrame configuration register + _ :: Bits 13 -- (Reserved) + FSOFF :: Bit -- Frame synchronization offset + FSPOL :: Bit -- Frame synchronization polarity + FSDEF :: Bit -- Frame synchronization definition + _ :: Bit -- (Reserved) + FSALL :: Bits 7 -- Frame synchronization active level length + FRL :: Bits 8 -- Frame length + + SLOTR 0x10 - SAI ASlot register + SLOTEN :: Bits 16 -- Slot enable + _ :: Bits 4 -- (Reserved) + NBSLOT :: Bits 4 -- Number of slots in an audio frame + SLOTSZ :: Bits 2 -- Slot size + _ :: Bit -- (Reserved) + FBOFF :: Bits 5 -- First bit offset + + IM 0x14 - SAI AInterrupt mask register2 + _ :: Bits 25 -- (Reserved) + LFSDETIE :: Bit -- Late frame synchronization detection interrupt enable + AFSDETIE :: Bit -- Anticipated frame synchronization detection interrupt enable + CNRDYIE :: Bit -- Codec not ready interrupt enable + FREQIE :: Bit -- FIFO request interrupt enable + WCKCFGIE :: Bit -- Wrong clock configuration interrupt enable + MUTEDETIE :: Bit -- Mute detection interrupt enable + OVRUDRIE :: Bit -- Overrun/underrun interrupt enable + + SR 0x18 - SAI AStatus register + _ :: Bits 13 -- (Reserved) + FLVL :: Bits 3 -- FIFO level threshold + _ :: Bits 9 -- (Reserved) + LFSDET :: Bit -- Late frame synchronization detection + AFSDET :: Bit -- Anticipated frame synchronization detection + CNRDY :: Bit -- Codec not ready + FREQ :: Bit -- FIFO request + WCKCFG :: Bit -- Wrong clock configuration flag + MUTEDET :: Bit -- Mute detection + OVRUDR :: Bit -- Overrun / underrun + + CLRFR 0x1c - SAI AClear flag register + _ :: Bits 25 -- (Reserved) + CLFSDET :: Bit -- Clear late frame synchronization detection flag + CAFSDET :: Bit -- Clear anticipated frame synchronization detection flag + CCNRDY :: Bit -- Clear codec not ready flag + _ :: Bit -- (Reserved) + CWCKCFG :: Bit -- Clear wrong clock configuration flag + CMUTEDET :: Bit -- Mute detection flag + COVRUDR :: Bit -- Clear overrun / underrun + + DR 0x20 - SAI AData register + DATA :: Bits 32 -- Data + + CR1 0x24 - SAI AConfiguration register 1 + _ :: Bits 8 -- (Reserved) + MCKDIV :: Bits 4 -- Master clock divider + NODIV :: Bit -- No divider + _ :: Bit -- (Reserved) + DMAEN :: Bit -- DMA enable + SAIEN :: Bit -- Audio block enable + _ :: Bits 2 -- (Reserved) + OUTDRIV :: Bit -- Output drive + MONO :: Bit -- Mono mode + SYNCEN :: Bits 2 -- Synchronization enable + CKSTR :: Bit -- Clock strobing edge + LSBFIRST :: Bit -- Least significant bit first + DS :: Bits 3 -- Data size + _ :: Bit -- (Reserved) + PRTCFG :: Bits 2 -- Protocol configuration + MODE :: Bits 2 -- Audio block mode + + CR2 0x28 - SAI AConfiguration register 2 + _ :: Bits 16 -- (Reserved) + COMP :: Bits 2 -- Companding mode + CPL :: Bit -- Complement bit + MUTECNT :: Bits 6 -- Mute counter + MUTEVAL :: Bit -- Mute value + MUTE :: Bit -- Mute + TRIS :: Bit -- Tristate management on data line + FFLUSH :: Bit -- FIFO flush + FTH :: Bits 3 -- FIFO threshold + + FRCR 0x2c - SAI AFrame configuration register + _ :: Bits 13 -- (Reserved) + FSOFF :: Bit -- Frame synchronization offset + FSPOL :: Bit -- Frame synchronization polarity + FSDEF :: Bit -- Frame synchronization definition + _ :: Bit -- (Reserved) + FSALL :: Bits 7 -- Frame synchronization active level length + FRL :: Bits 8 -- Frame length + + SLOTR 0x30 - SAI ASlot register + SLOTEN :: Bits 16 -- Slot enable + _ :: Bits 4 -- (Reserved) + NBSLOT :: Bits 4 -- Number of slots in an audio frame + SLOTSZ :: Bits 2 -- Slot size + _ :: Bit -- (Reserved) + FBOFF :: Bits 5 -- First bit offset + + IM 0x34 - SAI AInterrupt mask register2 + _ :: Bits 25 -- (Reserved) + LFSDETIE :: Bit -- Late frame synchronization detection interrupt enable + AFSDETIE :: Bit -- Anticipated frame synchronization detection interrupt enable + CNRDYIE :: Bit -- Codec not ready interrupt enable + FREQIE :: Bit -- FIFO request interrupt enable + WCKCFGIE :: Bit -- Wrong clock configuration interrupt enable + MUTEDETIE :: Bit -- Mute detection interrupt enable + OVRUDRIE :: Bit -- Overrun/underrun interrupt enable + + SR 0x38 - SAI AStatus register + _ :: Bits 13 -- (Reserved) + FLVL :: Bits 3 -- FIFO level threshold + _ :: Bits 9 -- (Reserved) + LFSDET :: Bit -- Late frame synchronization detection + AFSDET :: Bit -- Anticipated frame synchronization detection + CNRDY :: Bit -- Codec not ready + FREQ :: Bit -- FIFO request + WCKCFG :: Bit -- Wrong clock configuration flag + MUTEDET :: Bit -- Mute detection + OVRUDR :: Bit -- Overrun / underrun + + CLRFR 0x3c - SAI AClear flag register + _ :: Bits 25 -- (Reserved) + CLFSDET :: Bit -- Clear late frame synchronization detection flag + CAFSDET :: Bit -- Clear anticipated frame synchronization detection flag + CCNRDY :: Bit -- Clear codec not ready flag + _ :: Bit -- (Reserved) + CWCKCFG :: Bit -- Clear wrong clock configuration flag + CMUTEDET :: Bit -- Mute detection flag + COVRUDR :: Bit -- Clear overrun / underrun + + DR 0x40 - SAI AData register + DATA :: Bits 32 -- Data + + LTDC 0x40016800 LCD-TFT Controller + + SSCR 0x8 - Synchronization Size Configuration Register + _ :: Bits 4 -- (Reserved) + HSW :: Bits 12 -- Horizontal Synchronization Width (in units of pixel clock period) + _ :: Bits 5 -- (Reserved) + VSH :: Bits 11 -- Vertical Synchronization Height (in units of horizontal scan line) + + BPCR 0xc - Back Porch Configuration Register + _ :: Bits 4 -- (Reserved) + AHBP :: Bits 12 -- Accumulated Horizontal back porch (in units of pixel clock period) + _ :: Bits 5 -- (Reserved) + AVBP :: Bits 11 -- Accumulated Vertical back porch (in units of horizontal scan line) + + AWCR 0x10 - Active Width Configuration Register + _ :: Bits 4 -- (Reserved) + AAW :: Bits 12 -- Accumulated Active Width (in units of pixel clock period) + _ :: Bits 5 -- (Reserved) + AAH :: Bits 11 -- Accumulated Active Height (in units of horizontal scan line) + + TWCR 0x14 - Total Width Configuration Register + _ :: Bits 4 -- (Reserved) + TOTALW :: Bits 12 -- Total Width (in units of pixel clock period) + _ :: Bits 5 -- (Reserved) + TOTALH :: Bits 11 -- Total Height (in units of horizontal scan line) + + GCR 0x18 - Global Control Register + HSPOL :: Bit -- Horizontal Synchronization Polarity + VSPOL :: Bit -- Vertical Synchronization Polarity + DEPOL :: Bit -- Data Enable Polarity + PCPOL :: Bit -- Pixel Clock Polarity + _ :: Bits 11 -- (Reserved) + DEN :: Bit -- Dither Enable + _ :: Bit -- (Reserved) + DRW :: Bits 3 -- Dither Red Width + _ :: Bit -- (Reserved) + DGW :: Bits 3 -- Dither Green Width + _ :: Bit -- (Reserved) + DBW :: Bits 3 -- Dither Blue Width + _ :: Bits 3 -- (Reserved) + LTDCEN :: Bit -- LCD-TFT controller enable bit + + SRCR 0x24 - Shadow Reload Configuration Register + _ :: Bits 30 -- (Reserved) + VBR :: Bit -- Vertical Blanking Reload + IMR :: Bit -- Immediate Reload + + BCCR 0x2c - Background Color Configuration Register + _ :: Bits 8 -- (Reserved) + BCRED :: Bits 8 -- Background color red value + BCGREEN :: Bits 8 -- Background color green value + BCBLUE :: Bits 8 -- Background color blue value + + IER 0x34 - Interrupt Enable Register + _ :: Bits 28 -- (Reserved) + RRIE :: Bit -- Register Reload interrupt enable + TERRIE :: Bit -- Transfer Error Interrupt Enable + FUIE :: Bit -- FIFO Underrun Interrupt Enable + LIE :: Bit -- Line Interrupt Enable + + ISR 0x38 - Interrupt Status Register + _ :: Bits 28 -- (Reserved) + RRIF :: Bit -- Register Reload Interrupt Flag + TERRIF :: Bit -- Transfer Error interrupt flag + FUIF :: Bit -- FIFO Underrun Interrupt flag + LIF :: Bit -- Line Interrupt flag + + ICR 0x3c - Interrupt Clear Register + _ :: Bits 28 -- (Reserved) + CRRIF :: Bit -- Clears Register Reload Interrupt Flag + CTERRIF :: Bit -- Clears the Transfer Error Interrupt Flag + CFUIF :: Bit -- Clears the FIFO Underrun Interrupt flag + CLIF :: Bit -- Clears the Line Interrupt Flag + + LIPCR 0x40 - Line Interrupt Position Configuration Register + _ :: Bits 21 -- (Reserved) + LIPOS :: Bits 11 -- Line Interrupt Position + + CPSR 0x44 - Current Position Status Register + CXPOS :: Bits 16 -- Current X Position + CYPOS :: Bits 16 -- Current Y Position + + CDSR 0x48 - Current Display Status Register + _ :: Bits 28 -- (Reserved) + HSYNCS :: Bit -- Horizontal Synchronization display Status + VSYNCS :: Bit -- Vertical Synchronization display Status + HDES :: Bit -- Horizontal Data Enable display Status + VDES :: Bit -- Vertical Data Enable display Status + + CR 0x84 - Layerx Control Register + _ :: Bits 27 -- (Reserved) + CLUTEN :: Bit -- Color Look-Up Table Enable + _ :: Bits 2 -- (Reserved) + COLKEN :: Bit -- Color Keying Enable + LEN :: Bit -- Layer Enable + + WHPCR 0x88 - Layerx Window Horizontal Position Configuration Register + _ :: Bits 4 -- (Reserved) + WHSPPOS :: Bits 12 -- Window Horizontal Stop Position + _ :: Bits 4 -- (Reserved) + WHSTPOS :: Bits 12 -- Window Horizontal Start Position + + WVPCR 0x8c - Layerx Window Vertical Position Configuration Register + _ :: Bits 5 -- (Reserved) + WVSPPOS :: Bits 11 -- Window Vertical Stop Position + _ :: Bits 5 -- (Reserved) + WVSTPOS :: Bits 11 -- Window Vertical Start Position + + CKCR 0x90 - Layerx Color Keying Configuration Register + _ :: Bits 8 -- (Reserved) + CKRED :: Bits 8 -- Color Key Red value + CKGREEN :: Bits 8 -- Color Key Green value + CKBLUE :: Bits 8 -- Color Key Blue value + + PFCR 0x94 - Layerx Pixel Format Configuration Register + _ :: Bits 29 -- (Reserved) + PF :: Bits 3 -- Pixel Format + + CACR 0x98 - Layerx Constant Alpha Configuration Register + _ :: Bits 24 -- (Reserved) + CONSTA :: Bits 8 -- Constant Alpha + + DCCR 0x9c - Layerx Default Color Configuration Register + DCALPHA :: Bits 8 -- Default Color Alpha + DCRED :: Bits 8 -- Default Color Red + DCGREEN :: Bits 8 -- Default Color Green + DCBLUE :: Bits 8 -- Default Color Blue + + BFCR 0xa0 - Layerx Blending Factors Configuration Register + _ :: Bits 21 -- (Reserved) + BF1 :: Bits 3 -- Blending Factor 1 + _ :: Bits 5 -- (Reserved) + BF2 :: Bits 3 -- Blending Factor 2 + + CFBAR 0xac - Layerx Color Frame Buffer Address Register + CFBADD :: Bits 32 -- Color Frame Buffer Start Address + + CFBLR 0xb0 - Layerx Color Frame Buffer Length Register + _ :: Bits 3 -- (Reserved) + CFBP :: Bits 13 -- Color Frame Buffer Pitch in bytes + _ :: Bits 3 -- (Reserved) + CFBLL :: Bits 13 -- Color Frame Buffer Line Length + + CFBLNR 0xb4 - Layerx ColorFrame Buffer Line Number Register + _ :: Bits 21 -- (Reserved) + CFBLNBR :: Bits 11 -- Frame Buffer Line Number + + CLUTWR 0xc4 - Layerx CLUT Write Register + CLUTADD :: Bits 8 -- CLUT Address + RED :: Bits 8 -- Red value + GREEN :: Bits 8 -- Green value + BLUE :: Bits 8 -- Blue value + + CR 0x104 - Layerx Control Register + _ :: Bits 27 -- (Reserved) + CLUTEN :: Bit -- Color Look-Up Table Enable + _ :: Bits 2 -- (Reserved) + COLKEN :: Bit -- Color Keying Enable + LEN :: Bit -- Layer Enable + + WHPCR 0x108 - Layerx Window Horizontal Position Configuration Register + _ :: Bits 4 -- (Reserved) + WHSPPOS :: Bits 12 -- Window Horizontal Stop Position + _ :: Bits 4 -- (Reserved) + WHSTPOS :: Bits 12 -- Window Horizontal Start Position + + WVPCR 0x10c - Layerx Window Vertical Position Configuration Register + _ :: Bits 5 -- (Reserved) + WVSPPOS :: Bits 11 -- Window Vertical Stop Position + _ :: Bits 5 -- (Reserved) + WVSTPOS :: Bits 11 -- Window Vertical Start Position + + CKCR 0x110 - Layerx Color Keying Configuration Register + _ :: Bits 8 -- (Reserved) + CKRED :: Bits 8 -- Color Key Red value + CKGREEN :: Bits 8 -- Color Key Green value + CKBLUE :: Bits 8 -- Color Key Blue value + + PFCR 0x114 - Layerx Pixel Format Configuration Register + _ :: Bits 29 -- (Reserved) + PF :: Bits 3 -- Pixel Format + + CACR 0x118 - Layerx Constant Alpha Configuration Register + _ :: Bits 24 -- (Reserved) + CONSTA :: Bits 8 -- Constant Alpha + + DCCR 0x11c - Layerx Default Color Configuration Register + DCALPHA :: Bits 8 -- Default Color Alpha + DCRED :: Bits 8 -- Default Color Red + DCGREEN :: Bits 8 -- Default Color Green + DCBLUE :: Bits 8 -- Default Color Blue + + BFCR 0x120 - Layerx Blending Factors Configuration Register + _ :: Bits 21 -- (Reserved) + BF1 :: Bits 3 -- Blending Factor 1 + _ :: Bits 5 -- (Reserved) + BF2 :: Bits 3 -- Blending Factor 2 + + CFBAR 0x12c - Layerx Color Frame Buffer Address Register + CFBADD :: Bits 32 -- Color Frame Buffer Start Address + + CFBLR 0x130 - Layerx Color Frame Buffer Length Register + _ :: Bits 3 -- (Reserved) + CFBP :: Bits 13 -- Color Frame Buffer Pitch in bytes + _ :: Bits 3 -- (Reserved) + CFBLL :: Bits 13 -- Color Frame Buffer Line Length + + CFBLNR 0x134 - Layerx ColorFrame Buffer Line Number Register + _ :: Bits 21 -- (Reserved) + CFBLNBR :: Bits 11 -- Frame Buffer Line Number + + CLUTWR 0x144 - Layerx CLUT Write Register + CLUTADD :: Bits 8 -- CLUT Address + RED :: Bits 8 -- Red value + GREEN :: Bits 8 -- Green value + BLUE :: Bits 8 -- Blue value + + GPIOA 0x40020000 General-purpose I/Os + + MODER 0x0 - GPIO port mode register + MODER15 :: Bits 2 -- Port x configuration pin 15 + MODER14 :: Bits 2 -- Port x configuration pin 14 + MODER13 :: Bits 2 -- Port x configuration pin 13 + MODER12 :: Bits 2 -- Port x configuration pin 12 + MODER11 :: Bits 2 -- Port x configuration pin 11 + MODER10 :: Bits 2 -- Port x configuration pin 10 + MODER9 :: Bits 2 -- Port x configuration pin 9 + MODER8 :: Bits 2 -- Port x configuration pin 8 + MODER7 :: Bits 2 -- Port x configuration pin 7 + MODER6 :: Bits 2 -- Port x configuration pin 6 + MODER5 :: Bits 2 -- Port x configuration pin 5 + MODER4 :: Bits 2 -- Port x configuration pin 4 + MODER3 :: Bits 2 -- Port x configuration pin 3 + MODER2 :: Bits 2 -- Port x configuration pin 2 + MODER1 :: Bits 2 -- Port x configuration pin 1 + MODER0 :: Bits 2 -- Port x configuration pin 0 + + OTYPER 0x4 - GPIO port output type register + _ :: Bits 16 -- (Reserved) + OT15 :: Bit -- Port x configuration pin 15 + OT14 :: Bit -- Port x configuration pin 14 + OT13 :: Bit -- Port x configuration pin 13 + OT12 :: Bit -- Port x configuration pin 12 + OT11 :: Bit -- Port x configuration pin 11 + OT10 :: Bit -- Port x configuration pin 10 + OT9 :: Bit -- Port x configuration pin 9 + OT8 :: Bit -- Port x configuration pin 8 + OT7 :: Bit -- Port x configuration pin 7 + OT6 :: Bit -- Port x configuration pin 6 + OT5 :: Bit -- Port x configuration pin 5 + OT4 :: Bit -- Port x configuration pin 4 + OT3 :: Bit -- Port x configuration pin 3 + OT2 :: Bit -- Port x configuration pin 2 + OT1 :: Bit -- Port x configuration pin 1 + OT0 :: Bit -- Port x configuration pin 0 + + OSPEEDR 0x8 - GPIO port output speed register + OSPEEDR15 :: Bits 2 -- Port x configuration pin 15 + OSPEEDR14 :: Bits 2 -- Port x configuration pin 14 + OSPEEDR13 :: Bits 2 -- Port x configuration pin 13 + OSPEEDR12 :: Bits 2 -- Port x configuration pin 12 + OSPEEDR11 :: Bits 2 -- Port x configuration pin 11 + OSPEEDR10 :: Bits 2 -- Port x configuration pin 10 + OSPEEDR9 :: Bits 2 -- Port x configuration pin 9 + OSPEEDR8 :: Bits 2 -- Port x configuration pin 8 + OSPEEDR7 :: Bits 2 -- Port x configuration pin 7 + OSPEEDR6 :: Bits 2 -- Port x configuration pin 6 + OSPEEDR5 :: Bits 2 -- Port x configuration pin 5 + OSPEEDR4 :: Bits 2 -- Port x configuration pin 4 + OSPEEDR3 :: Bits 2 -- Port x configuration pin 3 + OSPEEDR2 :: Bits 2 -- Port x configuration pin 2 + OSPEEDR1 :: Bits 2 -- Port x configuration pin 1 + OSPEEDR0 :: Bits 2 -- Port x configuration pin 0 + + PUPDR 0xc - GPIO port pull-up/pull-down register + PUPDR15 :: Bits 2 -- Port x configuration pin 15 + PUPDR14 :: Bits 2 -- Port x configuration pin 14 + PUPDR13 :: Bits 2 -- Port x configuration pin 13 + PUPDR12 :: Bits 2 -- Port x configuration pin 12 + PUPDR11 :: Bits 2 -- Port x configuration pin 11 + PUPDR10 :: Bits 2 -- Port x configuration pin 10 + PUPDR9 :: Bits 2 -- Port x configuration pin 9 + PUPDR8 :: Bits 2 -- Port x configuration pin 8 + PUPDR7 :: Bits 2 -- Port x configuration pin 7 + PUPDR6 :: Bits 2 -- Port x configuration pin 6 + PUPDR5 :: Bits 2 -- Port x configuration pin 5 + PUPDR4 :: Bits 2 -- Port x configuration pin 4 + PUPDR3 :: Bits 2 -- Port x configuration pin 3 + PUPDR2 :: Bits 2 -- Port x configuration pin 2 + PUPDR1 :: Bits 2 -- Port x configuration pin 1 + PUPDR0 :: Bits 2 -- Port x configuration pin 0 + + IDR 0x10 - GPIO port input data register + _ :: Bits 16 -- (Reserved) + IDR15 :: Bit -- Port input data pin 15 + IDR14 :: Bit -- Port input data pin 14 + IDR13 :: Bit -- Port input data pin 13 + IDR12 :: Bit -- Port input data pin 12 + IDR11 :: Bit -- Port input data pin 11 + IDR10 :: Bit -- Port input data pin 10 + IDR9 :: Bit -- Port input data pin 9 + IDR8 :: Bit -- Port input data pin 8 + IDR7 :: Bit -- Port input data pin 7 + IDR6 :: Bit -- Port input data pin 6 + IDR5 :: Bit -- Port input data pin 5 + IDR4 :: Bit -- Port input data pin 4 + IDR3 :: Bit -- Port input data pin 3 + IDR2 :: Bit -- Port input data pin 2 + IDR1 :: Bit -- Port input data pin 1 + IDR0 :: Bit -- Port input data pin 0 + + ODR 0x14 - GPIO port output data register + _ :: Bits 16 -- (Reserved) + ODR15 :: Bit -- Port output data pin 15 + ODR14 :: Bit -- Port output data pin 14 + ODR13 :: Bit -- Port output data pin 13 + ODR12 :: Bit -- Port output data pin 12 + ODR11 :: Bit -- Port output data pin 11 + ODR10 :: Bit -- Port output data pin 10 + ODR9 :: Bit -- Port output data pin 9 + ODR8 :: Bit -- Port output data pin 8 + ODR7 :: Bit -- Port output data pin 7 + ODR6 :: Bit -- Port output data pin 6 + ODR5 :: Bit -- Port output data pin 5 + ODR4 :: Bit -- Port output data pin 4 + ODR3 :: Bit -- Port output data pin 3 + ODR2 :: Bit -- Port output data pin 2 + ODR1 :: Bit -- Port output data pin 1 + ODR0 :: Bit -- Port output data pin 0 + + BSRR 0x18 - GPIO port bit set/reset register + BR15 :: Bit -- Port x reset pin 15 + BR14 :: Bit -- Port x reset pin 14 + BR13 :: Bit -- Port x reset pin 13 + BR12 :: Bit -- Port x reset pin 12 + BR11 :: Bit -- Port x reset pin 11 + BR10 :: Bit -- Port x reset pin 10 + BR9 :: Bit -- Port x reset pin 9 + BR8 :: Bit -- Port x reset pin 8 + BR7 :: Bit -- Port x reset pin 7 + BR6 :: Bit -- Port x reset pin 6 + BR5 :: Bit -- Port x reset pin 5 + BR4 :: Bit -- Port x reset pin 4 + BR3 :: Bit -- Port x reset pin 3 + BR2 :: Bit -- Port x reset pin 2 + BR1 :: Bit -- Port x reset pin 1 + BR0 :: Bit -- Port x reset pin 0 + BS15 :: Bit -- Port x set pin 15 + BS14 :: Bit -- Port x set pin 14 + BS13 :: Bit -- Port x set pin 13 + BS12 :: Bit -- Port x set pin 12 + BS11 :: Bit -- Port x set pin 11 + BS10 :: Bit -- Port x set pin 10 + BS9 :: Bit -- Port x set pin 9 + BS8 :: Bit -- Port x set pin 8 + BS7 :: Bit -- Port x set pin 7 + BS6 :: Bit -- Port x set pin 6 + BS5 :: Bit -- Port x set pin 5 + BS4 :: Bit -- Port x set pin 4 + BS3 :: Bit -- Port x set pin 3 + BS2 :: Bit -- Port x set pin 2 + BS1 :: Bit -- Port x set pin 1 + BS0 :: Bit -- Port x set pin 0 + + LCKR 0x1c - GPIO port configuration lock register + _ :: Bits 15 -- (Reserved) + LCKK :: Bit -- Port x lock bit y (y= 0..15) + LCK15 :: Bit -- Port x lock pin 15 + LCK14 :: Bit -- Port x lock pin 14 + LCK13 :: Bit -- Port x lock pin 13 + LCK12 :: Bit -- Port x lock pin 12 + LCK11 :: Bit -- Port x lock pin 11 + LCK10 :: Bit -- Port x lock pin 10 + LCK9 :: Bit -- Port x lock pin 9 + LCK8 :: Bit -- Port x lock pin 8 + LCK7 :: Bit -- Port x lock pin 7 + LCK6 :: Bit -- Port x lock pin 6 + LCK5 :: Bit -- Port x lock pin 5 + LCK4 :: Bit -- Port x lock pin 4 + LCK3 :: Bit -- Port x lock pin 3 + LCK2 :: Bit -- Port x lock pin 2 + LCK1 :: Bit -- Port x lock pin 1 + LCK0 :: Bit -- Port x lock pin 0 + + AFRL 0x20 - GPIO alternate function low register + AFRL7 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL6 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL5 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL4 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL3 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL2 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL1 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL0 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + + AFRH 0x24 - GPIO alternate function high register + AFRH15 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH14 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH13 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH12 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH11 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH10 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH9 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH8 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + + GPIOB 0x40020400 General-purpose I/Os + + MODER 0x0 - GPIO port mode register + MODER15 :: Bits 2 -- Port x configuration pin 15 + MODER14 :: Bits 2 -- Port x configuration pin 14 + MODER13 :: Bits 2 -- Port x configuration pin 13 + MODER12 :: Bits 2 -- Port x configuration pin 12 + MODER11 :: Bits 2 -- Port x configuration pin 11 + MODER10 :: Bits 2 -- Port x configuration pin 10 + MODER9 :: Bits 2 -- Port x configuration pin 9 + MODER8 :: Bits 2 -- Port x configuration pin 8 + MODER7 :: Bits 2 -- Port x configuration pin 7 + MODER6 :: Bits 2 -- Port x configuration pin 6 + MODER5 :: Bits 2 -- Port x configuration pin 5 + MODER4 :: Bits 2 -- Port x configuration pin 4 + MODER3 :: Bits 2 -- Port x configuration pin 3 + MODER2 :: Bits 2 -- Port x configuration pin 2 + MODER1 :: Bits 2 -- Port x configuration pin 1 + MODER0 :: Bits 2 -- Port x configuration pin 0 + + OTYPER 0x4 - GPIO port output type register + _ :: Bits 16 -- (Reserved) + OT15 :: Bit -- Port x configuration pin 15 + OT14 :: Bit -- Port x configuration pin 14 + OT13 :: Bit -- Port x configuration pin 13 + OT12 :: Bit -- Port x configuration pin 12 + OT11 :: Bit -- Port x configuration pin 11 + OT10 :: Bit -- Port x configuration pin 10 + OT9 :: Bit -- Port x configuration pin 9 + OT8 :: Bit -- Port x configuration pin 8 + OT7 :: Bit -- Port x configuration pin 7 + OT6 :: Bit -- Port x configuration pin 6 + OT5 :: Bit -- Port x configuration pin 5 + OT4 :: Bit -- Port x configuration pin 4 + OT3 :: Bit -- Port x configuration pin 3 + OT2 :: Bit -- Port x configuration pin 2 + OT1 :: Bit -- Port x configuration pin 1 + OT0 :: Bit -- Port x configuration pin 0 + + OSPEEDR 0x8 - GPIO port output speed register + OSPEEDR15 :: Bits 2 -- Port x configuration pin 15 + OSPEEDR14 :: Bits 2 -- Port x configuration pin 14 + OSPEEDR13 :: Bits 2 -- Port x configuration pin 13 + OSPEEDR12 :: Bits 2 -- Port x configuration pin 12 + OSPEEDR11 :: Bits 2 -- Port x configuration pin 11 + OSPEEDR10 :: Bits 2 -- Port x configuration pin 10 + OSPEEDR9 :: Bits 2 -- Port x configuration pin 9 + OSPEEDR8 :: Bits 2 -- Port x configuration pin 8 + OSPEEDR7 :: Bits 2 -- Port x configuration pin 7 + OSPEEDR6 :: Bits 2 -- Port x configuration pin 6 + OSPEEDR5 :: Bits 2 -- Port x configuration pin 5 + OSPEEDR4 :: Bits 2 -- Port x configuration pin 4 + OSPEEDR3 :: Bits 2 -- Port x configuration pin 3 + OSPEEDR2 :: Bits 2 -- Port x configuration pin 2 + OSPEEDR1 :: Bits 2 -- Port x configuration pin 1 + OSPEEDR0 :: Bits 2 -- Port x configuration pin 0 + + PUPDR 0xc - GPIO port pull-up/pull-down register + PUPDR15 :: Bits 2 -- Port x configuration pin 15 + PUPDR14 :: Bits 2 -- Port x configuration pin 14 + PUPDR13 :: Bits 2 -- Port x configuration pin 13 + PUPDR12 :: Bits 2 -- Port x configuration pin 12 + PUPDR11 :: Bits 2 -- Port x configuration pin 11 + PUPDR10 :: Bits 2 -- Port x configuration pin 10 + PUPDR9 :: Bits 2 -- Port x configuration pin 9 + PUPDR8 :: Bits 2 -- Port x configuration pin 8 + PUPDR7 :: Bits 2 -- Port x configuration pin 7 + PUPDR6 :: Bits 2 -- Port x configuration pin 6 + PUPDR5 :: Bits 2 -- Port x configuration pin 5 + PUPDR4 :: Bits 2 -- Port x configuration pin 4 + PUPDR3 :: Bits 2 -- Port x configuration pin 3 + PUPDR2 :: Bits 2 -- Port x configuration pin 2 + PUPDR1 :: Bits 2 -- Port x configuration pin 1 + PUPDR0 :: Bits 2 -- Port x configuration pin 0 + + IDR 0x10 - GPIO port input data register + _ :: Bits 16 -- (Reserved) + IDR15 :: Bit -- Port input data pin 15 + IDR14 :: Bit -- Port input data pin 14 + IDR13 :: Bit -- Port input data pin 13 + IDR12 :: Bit -- Port input data pin 12 + IDR11 :: Bit -- Port input data pin 11 + IDR10 :: Bit -- Port input data pin 10 + IDR9 :: Bit -- Port input data pin 9 + IDR8 :: Bit -- Port input data pin 8 + IDR7 :: Bit -- Port input data pin 7 + IDR6 :: Bit -- Port input data pin 6 + IDR5 :: Bit -- Port input data pin 5 + IDR4 :: Bit -- Port input data pin 4 + IDR3 :: Bit -- Port input data pin 3 + IDR2 :: Bit -- Port input data pin 2 + IDR1 :: Bit -- Port input data pin 1 + IDR0 :: Bit -- Port input data pin 0 + + ODR 0x14 - GPIO port output data register + _ :: Bits 16 -- (Reserved) + ODR15 :: Bit -- Port output data pin 15 + ODR14 :: Bit -- Port output data pin 14 + ODR13 :: Bit -- Port output data pin 13 + ODR12 :: Bit -- Port output data pin 12 + ODR11 :: Bit -- Port output data pin 11 + ODR10 :: Bit -- Port output data pin 10 + ODR9 :: Bit -- Port output data pin 9 + ODR8 :: Bit -- Port output data pin 8 + ODR7 :: Bit -- Port output data pin 7 + ODR6 :: Bit -- Port output data pin 6 + ODR5 :: Bit -- Port output data pin 5 + ODR4 :: Bit -- Port output data pin 4 + ODR3 :: Bit -- Port output data pin 3 + ODR2 :: Bit -- Port output data pin 2 + ODR1 :: Bit -- Port output data pin 1 + ODR0 :: Bit -- Port output data pin 0 + + BSRR 0x18 - GPIO port bit set/reset register + BR15 :: Bit -- Port x reset pin 15 + BR14 :: Bit -- Port x reset pin 14 + BR13 :: Bit -- Port x reset pin 13 + BR12 :: Bit -- Port x reset pin 12 + BR11 :: Bit -- Port x reset pin 11 + BR10 :: Bit -- Port x reset pin 10 + BR9 :: Bit -- Port x reset pin 9 + BR8 :: Bit -- Port x reset pin 8 + BR7 :: Bit -- Port x reset pin 7 + BR6 :: Bit -- Port x reset pin 6 + BR5 :: Bit -- Port x reset pin 5 + BR4 :: Bit -- Port x reset pin 4 + BR3 :: Bit -- Port x reset pin 3 + BR2 :: Bit -- Port x reset pin 2 + BR1 :: Bit -- Port x reset pin 1 + BR0 :: Bit -- Port x reset pin 0 + BS15 :: Bit -- Port x set pin 15 + BS14 :: Bit -- Port x set pin 14 + BS13 :: Bit -- Port x set pin 13 + BS12 :: Bit -- Port x set pin 12 + BS11 :: Bit -- Port x set pin 11 + BS10 :: Bit -- Port x set pin 10 + BS9 :: Bit -- Port x set pin 9 + BS8 :: Bit -- Port x set pin 8 + BS7 :: Bit -- Port x set pin 7 + BS6 :: Bit -- Port x set pin 6 + BS5 :: Bit -- Port x set pin 5 + BS4 :: Bit -- Port x set pin 4 + BS3 :: Bit -- Port x set pin 3 + BS2 :: Bit -- Port x set pin 2 + BS1 :: Bit -- Port x set pin 1 + BS0 :: Bit -- Port x set pin 0 + + LCKR 0x1c - GPIO port configuration lock register + _ :: Bits 15 -- (Reserved) + LCKK :: Bit -- Port x lock bit y (y= 0..15) + LCK15 :: Bit -- Port x lock pin 15 + LCK14 :: Bit -- Port x lock pin 14 + LCK13 :: Bit -- Port x lock pin 13 + LCK12 :: Bit -- Port x lock pin 12 + LCK11 :: Bit -- Port x lock pin 11 + LCK10 :: Bit -- Port x lock pin 10 + LCK9 :: Bit -- Port x lock pin 9 + LCK8 :: Bit -- Port x lock pin 8 + LCK7 :: Bit -- Port x lock pin 7 + LCK6 :: Bit -- Port x lock pin 6 + LCK5 :: Bit -- Port x lock pin 5 + LCK4 :: Bit -- Port x lock pin 4 + LCK3 :: Bit -- Port x lock pin 3 + LCK2 :: Bit -- Port x lock pin 2 + LCK1 :: Bit -- Port x lock pin 1 + LCK0 :: Bit -- Port x lock pin 0 + + AFRL 0x20 - GPIO alternate function low register + AFRL7 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL6 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL5 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL4 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL3 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL2 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL1 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL0 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + + AFRH 0x24 - GPIO alternate function high register + AFRH15 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH14 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH13 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH12 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH11 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH10 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH9 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH8 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + + GPIOC 0x40020800 + + Derived from GPIOI + + GPIOD 0x40020c00 + + Derived from GPIOI + + GPIOE 0x40021000 + + Derived from GPIOI + + GPIOF 0x40021400 + + Derived from GPIOI + + GPIOG 0x40021800 + + Derived from GPIOI + + GPIOH 0x40021c00 + + Derived from GPIOI + + GPIOI 0x40022000 General-purpose I/Os + + MODER 0x0 - GPIO port mode register + MODER15 :: Bits 2 -- Port x configuration pin 15 + MODER14 :: Bits 2 -- Port x configuration pin 14 + MODER13 :: Bits 2 -- Port x configuration pin 13 + MODER12 :: Bits 2 -- Port x configuration pin 12 + MODER11 :: Bits 2 -- Port x configuration pin 11 + MODER10 :: Bits 2 -- Port x configuration pin 10 + MODER9 :: Bits 2 -- Port x configuration pin 9 + MODER8 :: Bits 2 -- Port x configuration pin 8 + MODER7 :: Bits 2 -- Port x configuration pin 7 + MODER6 :: Bits 2 -- Port x configuration pin 6 + MODER5 :: Bits 2 -- Port x configuration pin 5 + MODER4 :: Bits 2 -- Port x configuration pin 4 + MODER3 :: Bits 2 -- Port x configuration pin 3 + MODER2 :: Bits 2 -- Port x configuration pin 2 + MODER1 :: Bits 2 -- Port x configuration pin 1 + MODER0 :: Bits 2 -- Port x configuration pin 0 + + OTYPER 0x4 - GPIO port output type register + _ :: Bits 16 -- (Reserved) + OT15 :: Bit -- Port x configuration pin 15 + OT14 :: Bit -- Port x configuration pin 14 + OT13 :: Bit -- Port x configuration pin 13 + OT12 :: Bit -- Port x configuration pin 12 + OT11 :: Bit -- Port x configuration pin 11 + OT10 :: Bit -- Port x configuration pin 10 + OT9 :: Bit -- Port x configuration pin 9 + OT8 :: Bit -- Port x configuration pin 8 + OT7 :: Bit -- Port x configuration pin 7 + OT6 :: Bit -- Port x configuration pin 6 + OT5 :: Bit -- Port x configuration pin 5 + OT4 :: Bit -- Port x configuration pin 4 + OT3 :: Bit -- Port x configuration pin 3 + OT2 :: Bit -- Port x configuration pin 2 + OT1 :: Bit -- Port x configuration pin 1 + OT0 :: Bit -- Port x configuration pin 0 + + OSPEEDR 0x8 - GPIO port output speed register + OSPEEDR15 :: Bits 2 -- Port x configuration pin 15 + OSPEEDR14 :: Bits 2 -- Port x configuration pin 14 + OSPEEDR13 :: Bits 2 -- Port x configuration pin 13 + OSPEEDR12 :: Bits 2 -- Port x configuration pin 12 + OSPEEDR11 :: Bits 2 -- Port x configuration pin 11 + OSPEEDR10 :: Bits 2 -- Port x configuration pin 10 + OSPEEDR9 :: Bits 2 -- Port x configuration pin 9 + OSPEEDR8 :: Bits 2 -- Port x configuration pin 8 + OSPEEDR7 :: Bits 2 -- Port x configuration pin 7 + OSPEEDR6 :: Bits 2 -- Port x configuration pin 6 + OSPEEDR5 :: Bits 2 -- Port x configuration pin 5 + OSPEEDR4 :: Bits 2 -- Port x configuration pin 4 + OSPEEDR3 :: Bits 2 -- Port x configuration pin 3 + OSPEEDR2 :: Bits 2 -- Port x configuration pin 2 + OSPEEDR1 :: Bits 2 -- Port x configuration pin 1 + OSPEEDR0 :: Bits 2 -- Port x configuration pin 0 + + PUPDR 0xc - GPIO port pull-up/pull-down register + PUPDR15 :: Bits 2 -- Port x configuration pin 15 + PUPDR14 :: Bits 2 -- Port x configuration pin 14 + PUPDR13 :: Bits 2 -- Port x configuration pin 13 + PUPDR12 :: Bits 2 -- Port x configuration pin 12 + PUPDR11 :: Bits 2 -- Port x configuration pin 11 + PUPDR10 :: Bits 2 -- Port x configuration pin 10 + PUPDR9 :: Bits 2 -- Port x configuration pin 9 + PUPDR8 :: Bits 2 -- Port x configuration pin 8 + PUPDR7 :: Bits 2 -- Port x configuration pin 7 + PUPDR6 :: Bits 2 -- Port x configuration pin 6 + PUPDR5 :: Bits 2 -- Port x configuration pin 5 + PUPDR4 :: Bits 2 -- Port x configuration pin 4 + PUPDR3 :: Bits 2 -- Port x configuration pin 3 + PUPDR2 :: Bits 2 -- Port x configuration pin 2 + PUPDR1 :: Bits 2 -- Port x configuration pin 1 + PUPDR0 :: Bits 2 -- Port x configuration pin 0 + + IDR 0x10 - GPIO port input data register + _ :: Bits 16 -- (Reserved) + IDR15 :: Bit -- Port input data pin 15 + IDR14 :: Bit -- Port input data pin 14 + IDR13 :: Bit -- Port input data pin 13 + IDR12 :: Bit -- Port input data pin 12 + IDR11 :: Bit -- Port input data pin 11 + IDR10 :: Bit -- Port input data pin 10 + IDR9 :: Bit -- Port input data pin 9 + IDR8 :: Bit -- Port input data pin 8 + IDR7 :: Bit -- Port input data pin 7 + IDR6 :: Bit -- Port input data pin 6 + IDR5 :: Bit -- Port input data pin 5 + IDR4 :: Bit -- Port input data pin 4 + IDR3 :: Bit -- Port input data pin 3 + IDR2 :: Bit -- Port input data pin 2 + IDR1 :: Bit -- Port input data pin 1 + IDR0 :: Bit -- Port input data pin 0 + + ODR 0x14 - GPIO port output data register + _ :: Bits 16 -- (Reserved) + ODR15 :: Bit -- Port output data pin 15 + ODR14 :: Bit -- Port output data pin 14 + ODR13 :: Bit -- Port output data pin 13 + ODR12 :: Bit -- Port output data pin 12 + ODR11 :: Bit -- Port output data pin 11 + ODR10 :: Bit -- Port output data pin 10 + ODR9 :: Bit -- Port output data pin 9 + ODR8 :: Bit -- Port output data pin 8 + ODR7 :: Bit -- Port output data pin 7 + ODR6 :: Bit -- Port output data pin 6 + ODR5 :: Bit -- Port output data pin 5 + ODR4 :: Bit -- Port output data pin 4 + ODR3 :: Bit -- Port output data pin 3 + ODR2 :: Bit -- Port output data pin 2 + ODR1 :: Bit -- Port output data pin 1 + ODR0 :: Bit -- Port output data pin 0 + + BSRR 0x18 - GPIO port bit set/reset register + BR15 :: Bit -- Port x reset pin 15 + BR14 :: Bit -- Port x reset pin 14 + BR13 :: Bit -- Port x reset pin 13 + BR12 :: Bit -- Port x reset pin 12 + BR11 :: Bit -- Port x reset pin 11 + BR10 :: Bit -- Port x reset pin 10 + BR9 :: Bit -- Port x reset pin 9 + BR8 :: Bit -- Port x reset pin 8 + BR7 :: Bit -- Port x reset pin 7 + BR6 :: Bit -- Port x reset pin 6 + BR5 :: Bit -- Port x reset pin 5 + BR4 :: Bit -- Port x reset pin 4 + BR3 :: Bit -- Port x reset pin 3 + BR2 :: Bit -- Port x reset pin 2 + BR1 :: Bit -- Port x reset pin 1 + BR0 :: Bit -- Port x reset pin 0 + BS15 :: Bit -- Port x set pin 15 + BS14 :: Bit -- Port x set pin 14 + BS13 :: Bit -- Port x set pin 13 + BS12 :: Bit -- Port x set pin 12 + BS11 :: Bit -- Port x set pin 11 + BS10 :: Bit -- Port x set pin 10 + BS9 :: Bit -- Port x set pin 9 + BS8 :: Bit -- Port x set pin 8 + BS7 :: Bit -- Port x set pin 7 + BS6 :: Bit -- Port x set pin 6 + BS5 :: Bit -- Port x set pin 5 + BS4 :: Bit -- Port x set pin 4 + BS3 :: Bit -- Port x set pin 3 + BS2 :: Bit -- Port x set pin 2 + BS1 :: Bit -- Port x set pin 1 + BS0 :: Bit -- Port x set pin 0 + + LCKR 0x1c - GPIO port configuration lock register + _ :: Bits 15 -- (Reserved) + LCKK :: Bit -- Port x lock bit y (y= 0..15) + LCK15 :: Bit -- Port x lock pin 15 + LCK14 :: Bit -- Port x lock pin 14 + LCK13 :: Bit -- Port x lock pin 13 + LCK12 :: Bit -- Port x lock pin 12 + LCK11 :: Bit -- Port x lock pin 11 + LCK10 :: Bit -- Port x lock pin 10 + LCK9 :: Bit -- Port x lock pin 9 + LCK8 :: Bit -- Port x lock pin 8 + LCK7 :: Bit -- Port x lock pin 7 + LCK6 :: Bit -- Port x lock pin 6 + LCK5 :: Bit -- Port x lock pin 5 + LCK4 :: Bit -- Port x lock pin 4 + LCK3 :: Bit -- Port x lock pin 3 + LCK2 :: Bit -- Port x lock pin 2 + LCK1 :: Bit -- Port x lock pin 1 + LCK0 :: Bit -- Port x lock pin 0 + + AFRL 0x20 - GPIO alternate function low register + AFRL7 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL6 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL5 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL4 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL3 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL2 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL1 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + AFRL0 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7) + + AFRH 0x24 - GPIO alternate function high register + AFRH15 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH14 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH13 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH12 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH11 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH10 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH9 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + AFRH8 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15) + + GPIOJ 0x40022400 + + Derived from GPIOI + + GPIOK 0x40022800 + + Derived from GPIOI + + CRC 0x40023000 Cryptographic processor + + DR 0x0 - Data register + DR :: Bits 32 -- Data Register + + IDR 0x4 - Independent Data register + _ :: Bits 24 -- (Reserved) + IDR :: Bits 8 -- Independent Data register + + CR 0x8 - Control register + _ :: Bits 31 -- (Reserved) + RESET :: Bit -- Control regidter + + RCC 0x40023800 Reset and clock control + + CR 0x0 - clock control register + _ :: Bits 4 -- (Reserved) + PLLI2SRDY :: Bit -- PLLI2S clock ready flag + PLLI2SON :: Bit -- PLLI2S enable + PLLRDY :: Bit -- Main PLL (PLL) clock ready flag + PLLON :: Bit -- Main PLL (PLL) enable + _ :: Bits 4 -- (Reserved) + CSSON :: Bit -- Clock security system enable + HSEBYP :: Bit -- HSE clock bypass + HSERDY :: Bit -- HSE clock ready flag + HSEON :: Bit -- HSE clock enable + HSICAL :: Bits 8 -- Internal high-speed clock calibration + HSITRIM :: Bits 5 -- Internal high-speed clock trimming + _ :: Bit -- (Reserved) + HSIRDY :: Bit -- Internal high-speed clock ready flag + HSION :: Bit -- Internal high-speed clock enable + + PLLCFGR 0x4 - PLL configuration register + _ :: Bits 4 -- (Reserved) + PLLQ :: Bits 4 -- Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + _ :: Bit -- (Reserved) + PLLSRC :: Bit -- Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + _ :: Bits 4 -- (Reserved) + PLLP :: Bits 2 -- Main PLL (PLL) division factor for main system clock + _ :: Bit -- (Reserved) + PLLN :: Bits 9 -- Main PLL (PLL) multiplication factor for VCO + PLLM :: Bits 6 -- Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + + CFGR 0x8 - clock configuration register + MCO2 :: Bits 2 -- Microcontroller clock output 2 + MCO2PRE :: Bits 3 -- MCO2 prescaler + MCO1PRE :: Bits 3 -- MCO1 prescaler + I2SSRC :: Bit -- I2S clock selection + MCO1 :: Bits 2 -- Microcontroller clock output 1 + RTCPRE :: Bits 5 -- HSE division factor for RTC clock + PPRE2 :: Bits 3 -- APB high-speed prescaler (APB2) + PPRE1 :: Bits 3 -- APB Low speed prescaler (APB1) + _ :: Bits 2 -- (Reserved) + HPRE :: Bits 4 -- AHB prescaler + SWS :: Bits 2 -- System clock switch status + SW :: Bits 2 -- System clock switch + + CIR 0xc - clock interrupt register + _ :: Bits 8 -- (Reserved) + CSSC :: Bit -- Clock security system interrupt clear + _ :: Bit -- (Reserved) + PLLI2SRDYC :: Bit -- PLLI2S ready interrupt clear + PLLRDYC :: Bit -- Main PLL(PLL) ready interrupt clear + HSERDYC :: Bit -- HSE ready interrupt clear + HSIRDYC :: Bit -- HSI ready interrupt clear + LSERDYC :: Bit -- LSE ready interrupt clear + LSIRDYC :: Bit -- LSI ready interrupt clear + _ :: Bits 2 -- (Reserved) + PLLI2SRDYIE :: Bit -- PLLI2S ready interrupt enable + PLLRDYIE :: Bit -- Main PLL (PLL) ready interrupt enable + HSERDYIE :: Bit -- HSE ready interrupt enable + HSIRDYIE :: Bit -- HSI ready interrupt enable + LSERDYIE :: Bit -- LSE ready interrupt enable + LSIRDYIE :: Bit -- LSI ready interrupt enable + CSSF :: Bit -- Clock security system interrupt flag + _ :: Bit -- (Reserved) + PLLI2SRDYF :: Bit -- PLLI2S ready interrupt flag + PLLRDYF :: Bit -- Main PLL (PLL) ready interrupt flag + HSERDYF :: Bit -- HSE ready interrupt flag + HSIRDYF :: Bit -- HSI ready interrupt flag + LSERDYF :: Bit -- LSE ready interrupt flag + LSIRDYF :: Bit -- LSI ready interrupt flag + + AHB1RSTR 0x10 - AHB1 peripheral reset register + _ :: Bits 2 -- (Reserved) + OTGHSRST :: Bit -- USB OTG HS module reset + _ :: Bits 6 -- (Reserved) + DMA2RST :: Bit -- DMA2 reset + DMA1RST :: Bit -- DMA2 reset + _ :: Bits 8 -- (Reserved) + CRCRST :: Bit -- CRC reset + _ :: Bits 3 -- (Reserved) + GPIOIRST :: Bit -- IO port I reset + GPIOHRST :: Bit -- IO port H reset + GPIOGRST :: Bit -- IO port G reset + GPIOFRST :: Bit -- IO port F reset + GPIOERST :: Bit -- IO port E reset + GPIODRST :: Bit -- IO port D reset + GPIOCRST :: Bit -- IO port C reset + GPIOBRST :: Bit -- IO port B reset + GPIOARST :: Bit -- IO port A reset + + AHB2RSTR 0x14 - AHB2 peripheral reset register + _ :: Bits 24 -- (Reserved) + OTGFSRST :: Bit -- USB OTG FS module reset + RNGRST :: Bit -- Random number generator module reset + _ :: Bits 5 -- (Reserved) + DCMIRST :: Bit -- Camera interface reset + + AHB3RSTR 0x18 - AHB3 peripheral reset register + _ :: Bits 31 -- (Reserved) + FSMCRST :: Bit -- Flexible static memory controller module reset + + APB1RSTR 0x20 - APB1 peripheral reset register + _ :: Bits 2 -- (Reserved) + DACRST :: Bit -- DAC reset + PWRRST :: Bit -- Power interface reset + _ :: Bit -- (Reserved) + CAN2RST :: Bit -- CAN2 reset + CAN1RST :: Bit -- CAN1 reset + _ :: Bit -- (Reserved) + I2C3RST :: Bit -- I2C3 reset + I2C2RST :: Bit -- I2C 2 reset + I2C1RST :: Bit -- I2C 1 reset + UART5RST :: Bit -- USART 5 reset + UART4RST :: Bit -- USART 4 reset + USART3RST :: Bit -- USART 3 reset + USART2RST :: Bit -- USART 2 reset + _ :: Bit -- (Reserved) + SPI3RST :: Bit -- SPI 3 reset + SPI2RST :: Bit -- SPI 2 reset + _ :: Bits 2 -- (Reserved) + WWDGRST :: Bit -- Window watchdog reset + _ :: Bits 2 -- (Reserved) + TIM14RST :: Bit -- TIM14 reset + TIM13RST :: Bit -- TIM13 reset + TIM12RST :: Bit -- TIM12 reset + TIM7RST :: Bit -- TIM7 reset + TIM6RST :: Bit -- TIM6 reset + TIM5RST :: Bit -- TIM5 reset + TIM4RST :: Bit -- TIM4 reset + TIM3RST :: Bit -- TIM3 reset + TIM2RST :: Bit -- TIM2 reset + + APB2RSTR 0x24 - APB2 peripheral reset register + _ :: Bits 13 -- (Reserved) + TIM11RST :: Bit -- TIM11 reset + TIM10RST :: Bit -- TIM10 reset + TIM9RST :: Bit -- TIM9 reset + _ :: Bit -- (Reserved) + SYSCFGRST :: Bit -- System configuration controller reset + _ :: Bit -- (Reserved) + SPI1RST :: Bit -- SPI 1 reset + SDIORST :: Bit -- SDIO reset + _ :: Bits 2 -- (Reserved) + ADCRST :: Bit -- ADC interface reset (common to all ADCs) + _ :: Bits 2 -- (Reserved) + USART6RST :: Bit -- USART6 reset + USART1RST :: Bit -- USART1 reset + _ :: Bits 2 -- (Reserved) + TIM8RST :: Bit -- TIM8 reset + TIM1RST :: Bit -- TIM1 reset + + AHB1ENR 0x30 - AHB1 peripheral clock register + _ :: Bit -- (Reserved) + OTGHSULPIEN :: Bit -- USB OTG HSULPI clock enable + OTGHSEN :: Bit -- USB OTG HS clock enable + _ :: Bits 6 -- (Reserved) + DMA2EN :: Bit -- DMA2 clock enable + DMA1EN :: Bit -- DMA1 clock enable + _ :: Bits 2 -- (Reserved) + BKPSRAMEN :: Bit -- Backup SRAM interface clock enable + _ :: Bits 5 -- (Reserved) + CRCEN :: Bit -- CRC clock enable + _ :: Bits 3 -- (Reserved) + GPIOIEN :: Bit -- IO port I clock enable + GPIOHEN :: Bit -- IO port H clock enable + GPIOGEN :: Bit -- IO port G clock enable + GPIOFEN :: Bit -- IO port F clock enable + GPIOEEN :: Bit -- IO port E clock enable + GPIODEN :: Bit -- IO port D clock enable + GPIOCEN :: Bit -- IO port C clock enable + GPIOBEN :: Bit -- IO port B clock enable + GPIOAEN :: Bit -- IO port A clock enable + + AHB2ENR 0x34 - AHB2 peripheral clock enable register + _ :: Bits 24 -- (Reserved) + OTGFSEN :: Bit -- USB OTG FS clock enable + RNGEN :: Bit -- Random number generator clock enable + _ :: Bits 5 -- (Reserved) + DCMIEN :: Bit -- Camera interface enable + + AHB3ENR 0x38 - AHB3 peripheral clock enable register + _ :: Bits 31 -- (Reserved) + FSMCEN :: Bit -- Flexible static memory controller module clock enable + + APB1ENR 0x40 - APB1 peripheral clock enable register + _ :: Bits 2 -- (Reserved) + DACEN :: Bit -- DAC interface clock enable + PWREN :: Bit -- Power interface clock enable + _ :: Bit -- (Reserved) + CAN2EN :: Bit -- CAN 2 clock enable + CAN1EN :: Bit -- CAN 1 clock enable + _ :: Bit -- (Reserved) + I2C3EN :: Bit -- I2C3 clock enable + I2C2EN :: Bit -- I2C2 clock enable + I2C1EN :: Bit -- I2C1 clock enable + UART5EN :: Bit -- UART5 clock enable + UART4EN :: Bit -- UART4 clock enable + USART3EN :: Bit -- USART3 clock enable + USART2EN :: Bit -- USART 2 clock enable + _ :: Bit -- (Reserved) + SPI3EN :: Bit -- SPI3 clock enable + SPI2EN :: Bit -- SPI2 clock enable + _ :: Bits 2 -- (Reserved) + WWDGEN :: Bit -- Window watchdog clock enable + _ :: Bits 2 -- (Reserved) + TIM14EN :: Bit -- TIM14 clock enable + TIM13EN :: Bit -- TIM13 clock enable + TIM12EN :: Bit -- TIM12 clock enable + TIM7EN :: Bit -- TIM7 clock enable + TIM6EN :: Bit -- TIM6 clock enable + TIM5EN :: Bit -- TIM5 clock enable + TIM4EN :: Bit -- TIM4 clock enable + TIM3EN :: Bit -- TIM3 clock enable + TIM2EN :: Bit -- TIM2 clock enable + + APB2ENR 0x44 - APB2 peripheral clock enable register + _ :: Bits 13 -- (Reserved) + TIM11EN :: Bit -- TIM11 clock enable + TIM10EN :: Bit -- TIM10 clock enable + TIM9EN :: Bit -- TIM9 clock enable + _ :: Bit -- (Reserved) + SYSCFGEN :: Bit -- System configuration controller clock enable + _ :: Bit -- (Reserved) + SPI1EN :: Bit -- SPI1 clock enable + SDIOEN :: Bit -- SDIO clock enable + ADC3EN :: Bit -- ADC3 clock enable + ADC2EN :: Bit -- ADC2 clock enable + ADC1EN :: Bit -- ADC1 clock enable + _ :: Bits 2 -- (Reserved) + USART6EN :: Bit -- USART6 clock enable + USART1EN :: Bit -- USART1 clock enable + _ :: Bits 2 -- (Reserved) + TIM8EN :: Bit -- TIM8 clock enable + TIM1EN :: Bit -- TIM1 clock enable + + AHB1LPENR 0x50 - AHB1 peripheral clock enable in low power mode register + _ :: Bit -- (Reserved) + OTGHSULPILPEN :: Bit -- USB OTG HS ULPI clock enable during Sleep mode + OTGHSLPEN :: Bit -- USB OTG HS clock enable during Sleep mode + _ :: Bits 6 -- (Reserved) + DMA2LPEN :: Bit -- DMA2 clock enable during Sleep mode + DMA1LPEN :: Bit -- DMA1 clock enable during Sleep mode + _ :: Bits 2 -- (Reserved) + BKPSRAMLPEN :: Bit -- Backup SRAM interface clock enable during Sleep mode + SRAM2LPEN :: Bit -- SRAM 2 interface clock enable during Sleep mode + SRAM1LPEN :: Bit -- SRAM 1interface clock enable during Sleep mode + FLITFLPEN :: Bit -- Flash interface clock enable during Sleep mode + _ :: Bits 2 -- (Reserved) + CRCLPEN :: Bit -- CRC clock enable during Sleep mode + _ :: Bits 3 -- (Reserved) + GPIOILPEN :: Bit -- IO port I clock enable during Sleep mode + GPIOHLPEN :: Bit -- IO port H clock enable during Sleep mode + GPIOGLPEN :: Bit -- IO port G clock enable during Sleep mode + GPIOFLPEN :: Bit -- IO port F clock enable during Sleep mode + GPIOELPEN :: Bit -- IO port E clock enable during Sleep mode + GPIODLPEN :: Bit -- IO port D clock enable during Sleep mode + GPIOCLPEN :: Bit -- IO port C clock enable during Sleep mode + GPIOBLPEN :: Bit -- IO port B clock enable during Sleep mode + GPIOALPEN :: Bit -- IO port A clock enable during sleep mode + + AHB2LPENR 0x54 - AHB2 peripheral clock enable in low power mode register + _ :: Bits 24 -- (Reserved) + OTGFSLPEN :: Bit -- USB OTG FS clock enable during Sleep mode + RNGLPEN :: Bit -- Random number generator clock enable during Sleep mode + _ :: Bits 5 -- (Reserved) + DCMILPEN :: Bit -- Camera interface enable during Sleep mode + + AHB3LPENR 0x58 - AHB3 peripheral clock enable in low power mode register + _ :: Bits 31 -- (Reserved) + FSMCLPEN :: Bit -- Flexible static memory controller module clock enable during Sleep mode + + APB1LPENR 0x60 - APB1 peripheral clock enable in low power mode register + _ :: Bits 2 -- (Reserved) + DACLPEN :: Bit -- DAC interface clock enable during Sleep mode + PWRLPEN :: Bit -- Power interface clock enable during Sleep mode + _ :: Bit -- (Reserved) + CAN2LPEN :: Bit -- CAN 2 clock enable during Sleep mode + CAN1LPEN :: Bit -- CAN 1 clock enable during Sleep mode + _ :: Bit -- (Reserved) + I2C3LPEN :: Bit -- I2C3 clock enable during Sleep mode + I2C2LPEN :: Bit -- I2C2 clock enable during Sleep mode + I2C1LPEN :: Bit -- I2C1 clock enable during Sleep mode + UART5LPEN :: Bit -- UART5 clock enable during Sleep mode + UART4LPEN :: Bit -- UART4 clock enable during Sleep mode + USART3LPEN :: Bit -- USART3 clock enable during Sleep mode + USART2LPEN :: Bit -- USART2 clock enable during Sleep mode + _ :: Bit -- (Reserved) + SPI3LPEN :: Bit -- SPI3 clock enable during Sleep mode + SPI2LPEN :: Bit -- SPI2 clock enable during Sleep mode + _ :: Bits 2 -- (Reserved) + WWDGLPEN :: Bit -- Window watchdog clock enable during Sleep mode + _ :: Bits 2 -- (Reserved) + TIM14LPEN :: Bit -- TIM14 clock enable during Sleep mode + TIM13LPEN :: Bit -- TIM13 clock enable during Sleep mode + TIM12LPEN :: Bit -- TIM12 clock enable during Sleep mode + TIM7LPEN :: Bit -- TIM7 clock enable during Sleep mode + TIM6LPEN :: Bit -- TIM6 clock enable during Sleep mode + TIM5LPEN :: Bit -- TIM5 clock enable during Sleep mode + TIM4LPEN :: Bit -- TIM4 clock enable during Sleep mode + TIM3LPEN :: Bit -- TIM3 clock enable during Sleep mode + TIM2LPEN :: Bit -- TIM2 clock enable during Sleep mode + + APB2LPENR 0x64 - APB2 peripheral clock enabled in low power mode register + _ :: Bits 13 -- (Reserved) + TIM11LPEN :: Bit -- TIM11 clock enable during Sleep mode + TIM10LPEN :: Bit -- TIM10 clock enable during Sleep mode + TIM9LPEN :: Bit -- TIM9 clock enable during sleep mode + _ :: Bit -- (Reserved) + SYSCFGLPEN :: Bit -- System configuration controller clock enable during Sleep mode + _ :: Bit -- (Reserved) + SPI1LPEN :: Bit -- SPI 1 clock enable during Sleep mode + SDIOLPEN :: Bit -- SDIO clock enable during Sleep mode + ADC3LPEN :: Bit -- ADC 3 clock enable during Sleep mode + ADC2LPEN :: Bit -- ADC2 clock enable during Sleep mode + ADC1LPEN :: Bit -- ADC1 clock enable during Sleep mode + _ :: Bits 2 -- (Reserved) + USART6LPEN :: Bit -- USART6 clock enable during Sleep mode + USART1LPEN :: Bit -- USART1 clock enable during Sleep mode + _ :: Bits 2 -- (Reserved) + TIM8LPEN :: Bit -- TIM8 clock enable during Sleep mode + TIM1LPEN :: Bit -- TIM1 clock enable during Sleep mode + + BDCR 0x70 - Backup domain control register + _ :: Bits 15 -- (Reserved) + BDRST :: Bit -- Backup domain software reset + RTCEN :: Bit -- RTC clock enable + _ :: Bits 5 -- (Reserved) + RTCSEL :: Bits 2 -- RTC clock source selection + _ :: Bits 5 -- (Reserved) + LSEBYP :: Bit -- External low-speed oscillator bypass + LSERDY :: Bit -- External low-speed oscillator ready + LSEON :: Bit -- External low-speed oscillator enable + + CSR 0x74 - clock control & status register + LPWRRSTF :: Bit -- Low-power reset flag + WWDGRSTF :: Bit -- Window watchdog reset flag + WDGRSTF :: Bit -- Independent watchdog reset flag + SFTRSTF :: Bit -- Software reset flag + PORRSTF :: Bit -- POR/PDR reset flag + PADRSTF :: Bit -- PIN reset flag + BORRSTF :: Bit -- BOR reset flag + RMVF :: Bit -- Remove reset flag + _ :: Bits 22 -- (Reserved) + LSIRDY :: Bit -- Internal low-speed oscillator ready + LSION :: Bit -- Internal low-speed oscillator enable + + SSCGR 0x80 - spread spectrum clock generation register + SSCGEN :: Bit -- Spread spectrum modulation enable + SPREADSEL :: Bit -- Spread Select + _ :: Bits 2 -- (Reserved) + INCSTEP :: Bits 15 -- Incrementation step + MODPER :: Bits 13 -- Modulation period + + PLLI2SCFGR 0x84 - PLLI2S configuration register + _ :: Bit -- (Reserved) + PLLI2SR :: Bits 3 -- PLLI2S division factor for I2S clocks + _ :: Bits 13 -- (Reserved) + PLLI2SN :: Bits 9 -- PLLI2S multiplication factor for VCO + _ :: Bits 6 -- (Reserved) + + FLASH 0x40023c00 FLASH + + ACR 0x0 - Flash access control register + _ :: Bits 19 -- (Reserved) + DCRST :: Bit -- Data cache reset + ICRST :: Bit -- Instruction cache reset + DCEN :: Bit -- Data cache enable + ICEN :: Bit -- Instruction cache enable + PRFTEN :: Bit -- Prefetch enable + _ :: Bits 5 -- (Reserved) + LATENCY :: Bits 3 -- Latency + + KEYR 0x4 - Flash key register + KEY :: Bits 32 -- FPEC key + + OPTKEYR 0x8 - Flash option key register + OPTKEY :: Bits 32 -- Option byte key + + SR 0xc - Status register + _ :: Bits 15 -- (Reserved) + BSY :: Bit -- Busy + _ :: Bits 8 -- (Reserved) + PGSERR :: Bit -- Programming sequence error + PGPERR :: Bit -- Programming parallelism error + PGAERR :: Bit -- Programming alignment error + WRPERR :: Bit -- Write protection error + _ :: Bits 2 -- (Reserved) + OPERR :: Bit -- Operation error + EOP :: Bit -- End of operation + + CR 0x10 - Control register + LOCK :: Bit -- Lock + _ :: Bits 5 -- (Reserved) + ERRIE :: Bit -- Error interrupt enable + EOPIE :: Bit -- End of operation interrupt enable + _ :: Bits 7 -- (Reserved) + STRT :: Bit -- Start + _ :: Bits 6 -- (Reserved) + PSIZE :: Bits 2 -- Program size + _ :: Bit -- (Reserved) + SNB :: Bits 4 -- Sector number + MER :: Bit -- Mass Erase + SER :: Bit -- Sector Erase + PG :: Bit -- Programming + + OPTCR 0x14 - Flash option control register + _ :: Bits 4 -- (Reserved) + nWRP :: Bits 12 -- Not write protect + RDP :: Bits 8 -- Read protect + nRST_STDBY :: Bit -- nRST_STDBY User option bytes + nRST_STOP :: Bit -- nRST_STOP User option bytes + WDG_SW :: Bit -- WDG_SW User option bytes + _ :: Bit -- (Reserved) + BOR_LEV :: Bits 2 -- BOR reset Level + OPTSTRT :: Bit -- Option start + OPTLOCK :: Bit -- Option lock + + DMA1 0x40026000 + + Derived from DMA2 + + DMA2 0x40026400 DMA controller + + LISR 0x0 - low interrupt status register + _ :: Bits 4 -- (Reserved) + TCIF3 :: Bit -- Stream x transfer complete interrupt flag (x = 3..0) + HTIF3 :: Bit -- Stream x half transfer interrupt flag (x=3..0) + TEIF3 :: Bit -- Stream x transfer error interrupt flag (x=3..0) + DMEIF3 :: Bit -- Stream x direct mode error interrupt flag (x=3..0) + _ :: Bit -- (Reserved) + FEIF3 :: Bit -- Stream x FIFO error interrupt flag (x=3..0) + TCIF2 :: Bit -- Stream x transfer complete interrupt flag (x = 3..0) + HTIF2 :: Bit -- Stream x half transfer interrupt flag (x=3..0) + TEIF2 :: Bit -- Stream x transfer error interrupt flag (x=3..0) + DMEIF2 :: Bit -- Stream x direct mode error interrupt flag (x=3..0) + _ :: Bit -- (Reserved) + FEIF2 :: Bit -- Stream x FIFO error interrupt flag (x=3..0) + _ :: Bits 4 -- (Reserved) + TCIF1 :: Bit -- Stream x transfer complete interrupt flag (x = 3..0) + HTIF1 :: Bit -- Stream x half transfer interrupt flag (x=3..0) + TEIF1 :: Bit -- Stream x transfer error interrupt flag (x=3..0) + DMEIF1 :: Bit -- Stream x direct mode error interrupt flag (x=3..0) + _ :: Bit -- (Reserved) + FEIF1 :: Bit -- Stream x FIFO error interrupt flag (x=3..0) + TCIF0 :: Bit -- Stream x transfer complete interrupt flag (x = 3..0) + HTIF0 :: Bit -- Stream x half transfer interrupt flag (x=3..0) + TEIF0 :: Bit -- Stream x transfer error interrupt flag (x=3..0) + DMEIF0 :: Bit -- Stream x direct mode error interrupt flag (x=3..0) + _ :: Bit -- (Reserved) + FEIF0 :: Bit -- Stream x FIFO error interrupt flag (x=3..0) + + HISR 0x4 - high interrupt status register + _ :: Bits 4 -- (Reserved) + TCIF7 :: Bit -- Stream x transfer complete interrupt flag (x=7..4) + HTIF7 :: Bit -- Stream x half transfer interrupt flag (x=7..4) + TEIF7 :: Bit -- Stream x transfer error interrupt flag (x=7..4) + DMEIF7 :: Bit -- Stream x direct mode error interrupt flag (x=7..4) + _ :: Bit -- (Reserved) + FEIF7 :: Bit -- Stream x FIFO error interrupt flag (x=7..4) + TCIF6 :: Bit -- Stream x transfer complete interrupt flag (x=7..4) + HTIF6 :: Bit -- Stream x half transfer interrupt flag (x=7..4) + TEIF6 :: Bit -- Stream x transfer error interrupt flag (x=7..4) + DMEIF6 :: Bit -- Stream x direct mode error interrupt flag (x=7..4) + _ :: Bit -- (Reserved) + FEIF6 :: Bit -- Stream x FIFO error interrupt flag (x=7..4) + _ :: Bits 4 -- (Reserved) + TCIF5 :: Bit -- Stream x transfer complete interrupt flag (x=7..4) + HTIF5 :: Bit -- Stream x half transfer interrupt flag (x=7..4) + TEIF5 :: Bit -- Stream x transfer error interrupt flag (x=7..4) + DMEIF5 :: Bit -- Stream x direct mode error interrupt flag (x=7..4) + _ :: Bit -- (Reserved) + FEIF5 :: Bit -- Stream x FIFO error interrupt flag (x=7..4) + TCIF4 :: Bit -- Stream x transfer complete interrupt flag (x=7..4) + HTIF4 :: Bit -- Stream x half transfer interrupt flag (x=7..4) + TEIF4 :: Bit -- Stream x transfer error interrupt flag (x=7..4) + DMEIF4 :: Bit -- Stream x direct mode error interrupt flag (x=7..4) + _ :: Bit -- (Reserved) + FEIF4 :: Bit -- Stream x FIFO error interrupt flag (x=7..4) + + LIFCR 0x8 - low interrupt flag clear register + _ :: Bits 4 -- (Reserved) + CTCIF3 :: Bit -- Stream x clear transfer complete interrupt flag (x = 3..0) + CHTIF3 :: Bit -- Stream x clear half transfer interrupt flag (x = 3..0) + CTEIF3 :: Bit -- Stream x clear transfer error interrupt flag (x = 3..0) + CDMEIF3 :: Bit -- Stream x clear direct mode error interrupt flag (x = 3..0) + _ :: Bit -- (Reserved) + CFEIF3 :: Bit -- Stream x clear FIFO error interrupt flag (x = 3..0) + CTCIF2 :: Bit -- Stream x clear transfer complete interrupt flag (x = 3..0) + CHTIF2 :: Bit -- Stream x clear half transfer interrupt flag (x = 3..0) + CTEIF2 :: Bit -- Stream x clear transfer error interrupt flag (x = 3..0) + CDMEIF2 :: Bit -- Stream x clear direct mode error interrupt flag (x = 3..0) + _ :: Bit -- (Reserved) + CFEIF2 :: Bit -- Stream x clear FIFO error interrupt flag (x = 3..0) + _ :: Bits 4 -- (Reserved) + CTCIF1 :: Bit -- Stream x clear transfer complete interrupt flag (x = 3..0) + CHTIF1 :: Bit -- Stream x clear half transfer interrupt flag (x = 3..0) + CTEIF1 :: Bit -- Stream x clear transfer error interrupt flag (x = 3..0) + CDMEIF1 :: Bit -- Stream x clear direct mode error interrupt flag (x = 3..0) + _ :: Bit -- (Reserved) + CFEIF1 :: Bit -- Stream x clear FIFO error interrupt flag (x = 3..0) + CTCIF0 :: Bit -- Stream x clear transfer complete interrupt flag (x = 3..0) + CHTIF0 :: Bit -- Stream x clear half transfer interrupt flag (x = 3..0) + CTEIF0 :: Bit -- Stream x clear transfer error interrupt flag (x = 3..0) + CDMEIF0 :: Bit -- Stream x clear direct mode error interrupt flag (x = 3..0) + _ :: Bit -- (Reserved) + CFEIF0 :: Bit -- Stream x clear FIFO error interrupt flag (x = 3..0) + + HIFCR 0xc - high interrupt flag clear register + _ :: Bits 4 -- (Reserved) + CTCIF7 :: Bit -- Stream x clear transfer complete interrupt flag (x = 7..4) + CHTIF7 :: Bit -- Stream x clear half transfer interrupt flag (x = 7..4) + CTEIF7 :: Bit -- Stream x clear transfer error interrupt flag (x = 7..4) + CDMEIF7 :: Bit -- Stream x clear direct mode error interrupt flag (x = 7..4) + _ :: Bit -- (Reserved) + CFEIF7 :: Bit -- Stream x clear FIFO error interrupt flag (x = 7..4) + CTCIF6 :: Bit -- Stream x clear transfer complete interrupt flag (x = 7..4) + CHTIF6 :: Bit -- Stream x clear half transfer interrupt flag (x = 7..4) + CTEIF6 :: Bit -- Stream x clear transfer error interrupt flag (x = 7..4) + CDMEIF6 :: Bit -- Stream x clear direct mode error interrupt flag (x = 7..4) + _ :: Bit -- (Reserved) + CFEIF6 :: Bit -- Stream x clear FIFO error interrupt flag (x = 7..4) + _ :: Bits 4 -- (Reserved) + CTCIF5 :: Bit -- Stream x clear transfer complete interrupt flag (x = 7..4) + CHTIF5 :: Bit -- Stream x clear half transfer interrupt flag (x = 7..4) + CTEIF5 :: Bit -- Stream x clear transfer error interrupt flag (x = 7..4) + CDMEIF5 :: Bit -- Stream x clear direct mode error interrupt flag (x = 7..4) + _ :: Bit -- (Reserved) + CFEIF5 :: Bit -- Stream x clear FIFO error interrupt flag (x = 7..4) + CTCIF4 :: Bit -- Stream x clear transfer complete interrupt flag (x = 7..4) + CHTIF4 :: Bit -- Stream x clear half transfer interrupt flag (x = 7..4) + CTEIF4 :: Bit -- Stream x clear transfer error interrupt flag (x = 7..4) + CDMEIF4 :: Bit -- Stream x clear direct mode error interrupt flag (x = 7..4) + _ :: Bit -- (Reserved) + CFEIF4 :: Bit -- Stream x clear FIFO error interrupt flag (x = 7..4) + + CR 0x10 - stream x configuration register + _ :: Bits 4 -- (Reserved) + CHSEL :: Bits 3 -- Channel selection + MBURST :: Bits 2 -- Memory burst transfer configuration + PBURST :: Bits 2 -- Peripheral burst transfer configuration + _ :: Bit -- (Reserved) + CT :: Bit -- Current target (only in double buffer mode) + DBM :: Bit -- Double buffer mode + PL :: Bits 2 -- Priority level + PINCOS :: Bit -- Peripheral increment offset size + MSIZE :: Bits 2 -- Memory data size + PSIZE :: Bits 2 -- Peripheral data size + MINC :: Bit -- Memory increment mode + PINC :: Bit -- Peripheral increment mode + CIRC :: Bit -- Circular mode + DIR :: Bits 2 -- Data transfer direction + PFCTRL :: Bit -- Peripheral flow controller + TCIE :: Bit -- Transfer complete interrupt enable + HTIE :: Bit -- Half transfer interrupt enable + TEIE :: Bit -- Transfer error interrupt enable + DMEIE :: Bit -- Direct mode error interrupt enable + EN :: Bit -- Stream enable / flag stream ready when read low + + NDTR 0x14 - stream x number of data register + _ :: Bits 16 -- (Reserved) + NDT :: Bits 16 -- Number of data items to transfer + + PAR 0x18 - stream x peripheral address register + PA :: Bits 32 -- Peripheral address + + M0AR 0x1c - stream x memory 0 address register + M0A :: Bits 32 -- Memory 0 address + + M1AR 0x20 - stream x memory 1 address register + M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode) + + FCR 0x24 - stream x FIFO control register + _ :: Bits 24 -- (Reserved) + FEIE :: Bit -- FIFO error interrupt enable + _ :: Bit -- (Reserved) + FS :: Bits 3 -- FIFO status + DMDIS :: Bit -- Direct mode disable + FTH :: Bits 2 -- FIFO threshold selection + + CR 0x28 - stream x configuration register + _ :: Bits 4 -- (Reserved) + CHSEL :: Bits 3 -- Channel selection + MBURST :: Bits 2 -- Memory burst transfer configuration + PBURST :: Bits 2 -- Peripheral burst transfer configuration + _ :: Bit -- (Reserved) + CT :: Bit -- Current target (only in double buffer mode) + DBM :: Bit -- Double buffer mode + PL :: Bits 2 -- Priority level + PINCOS :: Bit -- Peripheral increment offset size + MSIZE :: Bits 2 -- Memory data size + PSIZE :: Bits 2 -- Peripheral data size + MINC :: Bit -- Memory increment mode + PINC :: Bit -- Peripheral increment mode + CIRC :: Bit -- Circular mode + DIR :: Bits 2 -- Data transfer direction + PFCTRL :: Bit -- Peripheral flow controller + TCIE :: Bit -- Transfer complete interrupt enable + HTIE :: Bit -- Half transfer interrupt enable + TEIE :: Bit -- Transfer error interrupt enable + DMEIE :: Bit -- Direct mode error interrupt enable + EN :: Bit -- Stream enable / flag stream ready when read low + + NDTR 0x2c - stream x number of data register + _ :: Bits 16 -- (Reserved) + NDT :: Bits 16 -- Number of data items to transfer + + PAR 0x30 - stream x peripheral address register + PA :: Bits 32 -- Peripheral address + + M0AR 0x34 - stream x memory 0 address register + M0A :: Bits 32 -- Memory 0 address + + M1AR 0x38 - stream x memory 1 address register + M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode) + + FCR 0x3c - stream x FIFO control register + _ :: Bits 24 -- (Reserved) + FEIE :: Bit -- FIFO error interrupt enable + _ :: Bit -- (Reserved) + FS :: Bits 3 -- FIFO status + DMDIS :: Bit -- Direct mode disable + FTH :: Bits 2 -- FIFO threshold selection + + CR 0x40 - stream x configuration register + _ :: Bits 4 -- (Reserved) + CHSEL :: Bits 3 -- Channel selection + MBURST :: Bits 2 -- Memory burst transfer configuration + PBURST :: Bits 2 -- Peripheral burst transfer configuration + _ :: Bit -- (Reserved) + CT :: Bit -- Current target (only in double buffer mode) + DBM :: Bit -- Double buffer mode + PL :: Bits 2 -- Priority level + PINCOS :: Bit -- Peripheral increment offset size + MSIZE :: Bits 2 -- Memory data size + PSIZE :: Bits 2 -- Peripheral data size + MINC :: Bit -- Memory increment mode + PINC :: Bit -- Peripheral increment mode + CIRC :: Bit -- Circular mode + DIR :: Bits 2 -- Data transfer direction + PFCTRL :: Bit -- Peripheral flow controller + TCIE :: Bit -- Transfer complete interrupt enable + HTIE :: Bit -- Half transfer interrupt enable + TEIE :: Bit -- Transfer error interrupt enable + DMEIE :: Bit -- Direct mode error interrupt enable + EN :: Bit -- Stream enable / flag stream ready when read low + + NDTR 0x44 - stream x number of data register + _ :: Bits 16 -- (Reserved) + NDT :: Bits 16 -- Number of data items to transfer + + PAR 0x48 - stream x peripheral address register + PA :: Bits 32 -- Peripheral address + + M0AR 0x4c - stream x memory 0 address register + M0A :: Bits 32 -- Memory 0 address + + M1AR 0x50 - stream x memory 1 address register + M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode) + + FCR 0x54 - stream x FIFO control register + _ :: Bits 24 -- (Reserved) + FEIE :: Bit -- FIFO error interrupt enable + _ :: Bit -- (Reserved) + FS :: Bits 3 -- FIFO status + DMDIS :: Bit -- Direct mode disable + FTH :: Bits 2 -- FIFO threshold selection + + CR 0x58 - stream x configuration register + _ :: Bits 4 -- (Reserved) + CHSEL :: Bits 3 -- Channel selection + MBURST :: Bits 2 -- Memory burst transfer configuration + PBURST :: Bits 2 -- Peripheral burst transfer configuration + _ :: Bit -- (Reserved) + CT :: Bit -- Current target (only in double buffer mode) + DBM :: Bit -- Double buffer mode + PL :: Bits 2 -- Priority level + PINCOS :: Bit -- Peripheral increment offset size + MSIZE :: Bits 2 -- Memory data size + PSIZE :: Bits 2 -- Peripheral data size + MINC :: Bit -- Memory increment mode + PINC :: Bit -- Peripheral increment mode + CIRC :: Bit -- Circular mode + DIR :: Bits 2 -- Data transfer direction + PFCTRL :: Bit -- Peripheral flow controller + TCIE :: Bit -- Transfer complete interrupt enable + HTIE :: Bit -- Half transfer interrupt enable + TEIE :: Bit -- Transfer error interrupt enable + DMEIE :: Bit -- Direct mode error interrupt enable + EN :: Bit -- Stream enable / flag stream ready when read low + + NDTR 0x5c - stream x number of data register + _ :: Bits 16 -- (Reserved) + NDT :: Bits 16 -- Number of data items to transfer + + PAR 0x60 - stream x peripheral address register + PA :: Bits 32 -- Peripheral address + + M0AR 0x64 - stream x memory 0 address register + M0A :: Bits 32 -- Memory 0 address + + M1AR 0x68 - stream x memory 1 address register + M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode) + + FCR 0x6c - stream x FIFO control register + _ :: Bits 24 -- (Reserved) + FEIE :: Bit -- FIFO error interrupt enable + _ :: Bit -- (Reserved) + FS :: Bits 3 -- FIFO status + DMDIS :: Bit -- Direct mode disable + FTH :: Bits 2 -- FIFO threshold selection + + CR 0x70 - stream x configuration register + _ :: Bits 4 -- (Reserved) + CHSEL :: Bits 3 -- Channel selection + MBURST :: Bits 2 -- Memory burst transfer configuration + PBURST :: Bits 2 -- Peripheral burst transfer configuration + _ :: Bit -- (Reserved) + CT :: Bit -- Current target (only in double buffer mode) + DBM :: Bit -- Double buffer mode + PL :: Bits 2 -- Priority level + PINCOS :: Bit -- Peripheral increment offset size + MSIZE :: Bits 2 -- Memory data size + PSIZE :: Bits 2 -- Peripheral data size + MINC :: Bit -- Memory increment mode + PINC :: Bit -- Peripheral increment mode + CIRC :: Bit -- Circular mode + DIR :: Bits 2 -- Data transfer direction + PFCTRL :: Bit -- Peripheral flow controller + TCIE :: Bit -- Transfer complete interrupt enable + HTIE :: Bit -- Half transfer interrupt enable + TEIE :: Bit -- Transfer error interrupt enable + DMEIE :: Bit -- Direct mode error interrupt enable + EN :: Bit -- Stream enable / flag stream ready when read low + + NDTR 0x74 - stream x number of data register + _ :: Bits 16 -- (Reserved) + NDT :: Bits 16 -- Number of data items to transfer + + PAR 0x78 - stream x peripheral address register + PA :: Bits 32 -- Peripheral address + + M0AR 0x7c - stream x memory 0 address register + M0A :: Bits 32 -- Memory 0 address + + M1AR 0x80 - stream x memory 1 address register + M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode) + + FCR 0x84 - stream x FIFO control register + _ :: Bits 24 -- (Reserved) + FEIE :: Bit -- FIFO error interrupt enable + _ :: Bit -- (Reserved) + FS :: Bits 3 -- FIFO status + DMDIS :: Bit -- Direct mode disable + FTH :: Bits 2 -- FIFO threshold selection + + CR 0x88 - stream x configuration register + _ :: Bits 4 -- (Reserved) + CHSEL :: Bits 3 -- Channel selection + MBURST :: Bits 2 -- Memory burst transfer configuration + PBURST :: Bits 2 -- Peripheral burst transfer configuration + _ :: Bit -- (Reserved) + CT :: Bit -- Current target (only in double buffer mode) + DBM :: Bit -- Double buffer mode + PL :: Bits 2 -- Priority level + PINCOS :: Bit -- Peripheral increment offset size + MSIZE :: Bits 2 -- Memory data size + PSIZE :: Bits 2 -- Peripheral data size + MINC :: Bit -- Memory increment mode + PINC :: Bit -- Peripheral increment mode + CIRC :: Bit -- Circular mode + DIR :: Bits 2 -- Data transfer direction + PFCTRL :: Bit -- Peripheral flow controller + TCIE :: Bit -- Transfer complete interrupt enable + HTIE :: Bit -- Half transfer interrupt enable + TEIE :: Bit -- Transfer error interrupt enable + DMEIE :: Bit -- Direct mode error interrupt enable + EN :: Bit -- Stream enable / flag stream ready when read low + + NDTR 0x8c - stream x number of data register + _ :: Bits 16 -- (Reserved) + NDT :: Bits 16 -- Number of data items to transfer + + PAR 0x90 - stream x peripheral address register + PA :: Bits 32 -- Peripheral address + + M0AR 0x94 - stream x memory 0 address register + M0A :: Bits 32 -- Memory 0 address + + M1AR 0x98 - stream x memory 1 address register + M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode) + + FCR 0x9c - stream x FIFO control register + _ :: Bits 24 -- (Reserved) + FEIE :: Bit -- FIFO error interrupt enable + _ :: Bit -- (Reserved) + FS :: Bits 3 -- FIFO status + DMDIS :: Bit -- Direct mode disable + FTH :: Bits 2 -- FIFO threshold selection + + CR 0xa0 - stream x configuration register + _ :: Bits 4 -- (Reserved) + CHSEL :: Bits 3 -- Channel selection + MBURST :: Bits 2 -- Memory burst transfer configuration + PBURST :: Bits 2 -- Peripheral burst transfer configuration + _ :: Bit -- (Reserved) + CT :: Bit -- Current target (only in double buffer mode) + DBM :: Bit -- Double buffer mode + PL :: Bits 2 -- Priority level + PINCOS :: Bit -- Peripheral increment offset size + MSIZE :: Bits 2 -- Memory data size + PSIZE :: Bits 2 -- Peripheral data size + MINC :: Bit -- Memory increment mode + PINC :: Bit -- Peripheral increment mode + CIRC :: Bit -- Circular mode + DIR :: Bits 2 -- Data transfer direction + PFCTRL :: Bit -- Peripheral flow controller + TCIE :: Bit -- Transfer complete interrupt enable + HTIE :: Bit -- Half transfer interrupt enable + TEIE :: Bit -- Transfer error interrupt enable + DMEIE :: Bit -- Direct mode error interrupt enable + EN :: Bit -- Stream enable / flag stream ready when read low + + NDTR 0xa4 - stream x number of data register + _ :: Bits 16 -- (Reserved) + NDT :: Bits 16 -- Number of data items to transfer + + PAR 0xa8 - stream x peripheral address register + PA :: Bits 32 -- Peripheral address + + M0AR 0xac - stream x memory 0 address register + M0A :: Bits 32 -- Memory 0 address + + M1AR 0xb0 - stream x memory 1 address register + M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode) + + FCR 0xb4 - stream x FIFO control register + _ :: Bits 24 -- (Reserved) + FEIE :: Bit -- FIFO error interrupt enable + _ :: Bit -- (Reserved) + FS :: Bits 3 -- FIFO status + DMDIS :: Bit -- Direct mode disable + FTH :: Bits 2 -- FIFO threshold selection + + CR 0xb8 - stream x configuration register + _ :: Bits 4 -- (Reserved) + CHSEL :: Bits 3 -- Channel selection + MBURST :: Bits 2 -- Memory burst transfer configuration + PBURST :: Bits 2 -- Peripheral burst transfer configuration + _ :: Bit -- (Reserved) + CT :: Bit -- Current target (only in double buffer mode) + DBM :: Bit -- Double buffer mode + PL :: Bits 2 -- Priority level + PINCOS :: Bit -- Peripheral increment offset size + MSIZE :: Bits 2 -- Memory data size + PSIZE :: Bits 2 -- Peripheral data size + MINC :: Bit -- Memory increment mode + PINC :: Bit -- Peripheral increment mode + CIRC :: Bit -- Circular mode + DIR :: Bits 2 -- Data transfer direction + PFCTRL :: Bit -- Peripheral flow controller + TCIE :: Bit -- Transfer complete interrupt enable + HTIE :: Bit -- Half transfer interrupt enable + TEIE :: Bit -- Transfer error interrupt enable + DMEIE :: Bit -- Direct mode error interrupt enable + EN :: Bit -- Stream enable / flag stream ready when read low + + NDTR 0xbc - stream x number of data register + _ :: Bits 16 -- (Reserved) + NDT :: Bits 16 -- Number of data items to transfer + + PAR 0xc0 - stream x peripheral address register + PA :: Bits 32 -- Peripheral address + + M0AR 0xc4 - stream x memory 0 address register + M0A :: Bits 32 -- Memory 0 address + + M1AR 0xc8 - stream x memory 1 address register + M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode) + + FCR 0xcc - stream x FIFO control register + _ :: Bits 24 -- (Reserved) + FEIE :: Bit -- FIFO error interrupt enable + _ :: Bit -- (Reserved) + FS :: Bits 3 -- FIFO status + DMDIS :: Bit -- Direct mode disable + FTH :: Bits 2 -- FIFO threshold selection + + OTG_HS_GLOBAL 0x40040000 USB on the go high speed + + GOTGCTL 0x0 - OTG_HS control and status register + _ :: Bits 12 -- (Reserved) + BSVLD :: Bit -- B-session valid + ASVLD :: Bit -- A-session valid + DBCT :: Bit -- Long/short debounce time + CIDSTS :: Bit -- Connector ID status + _ :: Bits 4 -- (Reserved) + DHNPEN :: Bit -- Device HNP enabled + HSHNPEN :: Bit -- Host set HNP enable + HNPRQ :: Bit -- HNP request + HNGSCS :: Bit -- Host negotiation success + _ :: Bits 6 -- (Reserved) + SRQ :: Bit -- Session request + SRQSCS :: Bit -- Session request success + + GOTGINT 0x4 - OTG_HS interrupt register + _ :: Bits 12 -- (Reserved) + DBCDNE :: Bit -- Debounce done + ADTOCHG :: Bit -- A-device timeout change + HNGDET :: Bit -- Host negotiation detected + _ :: Bits 7 -- (Reserved) + HNSSCHG :: Bit -- Host negotiation success status change + SRSSCHG :: Bit -- Session request success status change + _ :: Bits 5 -- (Reserved) + SEDET :: Bit -- Session end detected + _ :: Bits 2 -- (Reserved) + + GAHBCFG 0x8 - OTG_HS AHB configuration register + _ :: Bits 23 -- (Reserved) + PTXFELVL :: Bit -- Periodic TxFIFO empty level + TXFELVL :: Bit -- TxFIFO empty level + _ :: Bit -- (Reserved) + DMAEN :: Bit -- DMA enable + HBSTLEN :: Bits 4 -- Burst length/type + GINT :: Bit -- Global interrupt mask + + GUSBCFG 0xc - OTG_HS USB configuration register + CTXPKT :: Bit -- Corrupt Tx packet + FDMOD :: Bit -- Forced peripheral mode + FHMOD :: Bit -- Forced host mode + _ :: Bits 3 -- (Reserved) + ULPIIPD :: Bit -- ULPI interface protect disable + PTCI :: Bit -- Indicator pass through + PCCI :: Bit -- Indicator complement + TSDPS :: Bit -- TermSel DLine pulsing selection + ULPIEVBUSI :: Bit -- ULPI external VBUS indicator + ULPIEVBUSD :: Bit -- ULPI External VBUS Drive + ULPICSM :: Bit -- ULPI Clock SuspendM + ULPIAR :: Bit -- ULPI Auto-resume + ULPIFSLS :: Bit -- ULPI FS/LS select + _ :: Bit -- (Reserved) + PHYLPCS :: Bit -- PHY Low-power clock select + _ :: Bit -- (Reserved) + TRDT :: Bits 4 -- USB turnaround time + HNPCAP :: Bit -- HNP-capable + SRPCAP :: Bit -- SRP-capable + _ :: Bit -- (Reserved) + PHYSEL :: Bit -- USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select + _ :: Bits 3 -- (Reserved) + TOCAL :: Bits 3 -- FS timeout calibration + + GRSTCTL 0x10 - OTG_HS reset register + AHBIDL :: Bit -- AHB master idle + DMAREQ :: Bit -- DMA request signal + _ :: Bits 19 -- (Reserved) + TXFNUM :: Bits 5 -- TxFIFO number + TXFFLSH :: Bit -- TxFIFO flush + RXFFLSH :: Bit -- RxFIFO flush + _ :: Bit -- (Reserved) + FCRST :: Bit -- Host frame counter reset + HSRST :: Bit -- HCLK soft reset + CSRST :: Bit -- Core soft reset + + GINTSTS 0x14 - OTG_HS core interrupt register + WKUINT :: Bit -- Resume/remote wakeup detected interrupt + SRQINT :: Bit -- Session request/new session detected interrupt + DISCINT :: Bit -- Disconnect detected interrupt + CIDSCHG :: Bit -- Connector ID status change + _ :: Bit -- (Reserved) + PTXFE :: Bit -- Periodic TxFIFO empty + HCINT :: Bit -- Host channels interrupt + HPRTINT :: Bit -- Host port interrupt + _ :: Bit -- (Reserved) + DATAFSUSP :: Bit -- Data fetch suspended + PXFR_INCOMPISOOUT :: Bit -- Incomplete periodic transfer + IISOIXFR :: Bit -- Incomplete isochronous IN transfer + OEPINT :: Bit -- OUT endpoint interrupt + IEPINT :: Bit -- IN endpoint interrupt + _ :: Bits 2 -- (Reserved) + EOPF :: Bit -- End of periodic frame interrupt + ISOODRP :: Bit -- Isochronous OUT packet dropped interrupt + ENUMDNE :: Bit -- Enumeration done + USBRST :: Bit -- USB reset + USBSUSP :: Bit -- USB suspend + ESUSP :: Bit -- Early suspend + _ :: Bits 2 -- (Reserved) + BOUTNAKEFF :: Bit -- Global OUT NAK effective + GINAKEFF :: Bit -- Global IN nonperiodic NAK effective + NPTXFE :: Bit -- Nonperiodic TxFIFO empty + RXFLVL :: Bit -- RxFIFO nonempty + SOF :: Bit -- Start of frame + OTGINT :: Bit -- OTG interrupt + MMIS :: Bit -- Mode mismatch interrupt + CMOD :: Bit -- Current mode of operation + + GINTMSK 0x18 - OTG_HS interrupt mask register + WUIM :: Bit -- Resume/remote wakeup detected interrupt mask + SRQIM :: Bit -- Session request/new session detected interrupt mask + DISCINT :: Bit -- Disconnect detected interrupt mask + CIDSCHGM :: Bit -- Connector ID status change mask + _ :: Bit -- (Reserved) + PTXFEM :: Bit -- Periodic TxFIFO empty mask + HCIM :: Bit -- Host channels interrupt mask + PRTIM :: Bit -- Host port interrupt mask + _ :: Bit -- (Reserved) + FSUSPM :: Bit -- Data fetch suspended mask + PXFRM_IISOOXFRM :: Bit -- Incomplete periodic transfer mask + IISOIXFRM :: Bit -- Incomplete isochronous IN transfer mask + OEPINT :: Bit -- OUT endpoints interrupt mask + IEPINT :: Bit -- IN endpoints interrupt mask + EPMISM :: Bit -- Endpoint mismatch interrupt mask + _ :: Bit -- (Reserved) + EOPFM :: Bit -- End of periodic frame interrupt mask + ISOODRPM :: Bit -- Isochronous OUT packet dropped interrupt mask + ENUMDNEM :: Bit -- Enumeration done mask + USBRST :: Bit -- USB reset mask + USBSUSPM :: Bit -- USB suspend mask + ESUSPM :: Bit -- Early suspend mask + _ :: Bits 2 -- (Reserved) + GONAKEFFM :: Bit -- Global OUT NAK effective mask + GINAKEFFM :: Bit -- Global nonperiodic IN NAK effective mask + NPTXFEM :: Bit -- Nonperiodic TxFIFO empty mask + RXFLVLM :: Bit -- Receive FIFO nonempty mask + SOFM :: Bit -- Start of frame mask + OTGINT :: Bit -- OTG interrupt mask + MMISM :: Bit -- Mode mismatch interrupt mask + _ :: Bit -- (Reserved) + + GRXSTSR_Host 0x1c - OTG_HS Receive status debug read register (host mode) + _ :: Bits 11 -- (Reserved) + PKTSTS :: Bits 4 -- Packet status + DPID :: Bits 2 -- Data PID + BCNT :: Bits 11 -- Byte count + CHNUM :: Bits 4 -- Channel number + + GRXSTSR_Device 0x1c - OTG_HS Receive status debug read register (peripheral mode mode) + _ :: Bits 7 -- (Reserved) + FRMNUM :: Bits 4 -- Frame number + PKTSTS :: Bits 4 -- Packet status + DPID :: Bits 2 -- Data PID + BCNT :: Bits 11 -- Byte count + EPNUM :: Bits 4 -- Endpoint number + + GRXSTSP_Host 0x20 - OTG_HS status read and pop register (host mode) + _ :: Bits 11 -- (Reserved) + PKTSTS :: Bits 4 -- Packet status + DPID :: Bits 2 -- Data PID + BCNT :: Bits 11 -- Byte count + CHNUM :: Bits 4 -- Channel number + + GRXSTSP_Device 0x20 - OTG_HS status read and pop register (peripheral mode) + _ :: Bits 7 -- (Reserved) + FRMNUM :: Bits 4 -- Frame number + PKTSTS :: Bits 4 -- Packet status + DPID :: Bits 2 -- Data PID + BCNT :: Bits 11 -- Byte count + EPNUM :: Bits 4 -- Endpoint number + + GRXFSIZ 0x24 - OTG_HS Receive FIFO size register + _ :: Bits 16 -- (Reserved) + RXFD :: Bits 16 -- RxFIFO depth + + HNPTXFSIZ 0x28 - OTG_HS nonperiodic transmit FIFO size register (host mode) + NPTXFD :: Bits 16 -- Nonperiodic TxFIFO depth + NPTXFSA :: Bits 16 -- Nonperiodic transmit RAM start address + + DIEPTXF0 0x28 - Endpoint 0 transmit FIFO size (peripheral mode) + TX0FD :: Bits 16 -- Endpoint 0 TxFIFO depth + TX0FSA :: Bits 16 -- Endpoint 0 transmit RAM start address + + HNPTXSTS 0x2c - OTG_HS nonperiodic transmit FIFO/queue status register + _ :: Bit -- (Reserved) + NPTXQTOP :: Bits 7 -- Top of the nonperiodic transmit request queue + NPTQXSAV :: Bits 8 -- Nonperiodic transmit request queue space available + NPTXFSAV :: Bits 16 -- Nonperiodic TxFIFO space available + + GCCFG 0x38 - OTG_HS general core configuration register + _ :: Bits 10 -- (Reserved) + NOVBUSSENS :: Bit -- VBUS sensing disable option + SOFOUTEN :: Bit -- SOF output enable + VBUSBSEN :: Bit -- Enable the VBUS sensing device + VBUSASEN :: Bit -- Enable the VBUS sensing device + I2CPADEN :: Bit -- Enable I2C bus connection for the external I2C PHY interface + PWRDWN :: Bit -- Power down + _ :: Bits 16 -- (Reserved) + + CID 0x3c - OTG_HS core ID register + PRODUCT_ID :: Bits 32 -- Product ID field + + HPTXFSIZ 0x100 - OTG_HS Host periodic transmit FIFO size register + PTXFD :: Bits 16 -- Host periodic TxFIFO depth + PTXSA :: Bits 16 -- Host periodic TxFIFO start address + + DIEPTXF1 0x104 - OTG_HS device IN endpoint transmit FIFO size register + INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth + INEPTXSA :: Bits 16 -- IN endpoint FIFOx transmit RAM start address + + DIEPTXF2 0x108 - OTG_HS device IN endpoint transmit FIFO size register + INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth + INEPTXSA :: Bits 16 -- IN endpoint FIFOx transmit RAM start address + + DIEPTXF3 0x10c - OTG_HS device IN endpoint transmit FIFO size register + INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth + INEPTXSA :: Bits 16 -- IN endpoint FIFOx transmit RAM start address + + DIEPTXF4 0x110 - OTG_HS device IN endpoint transmit FIFO size register + INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth + INEPTXSA :: Bits 16 -- IN endpoint FIFOx transmit RAM start address + + DIEPTXF5 0x114 - OTG_HS device IN endpoint transmit FIFO size register + INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth + INEPTXSA :: Bits 16 -- IN endpoint FIFOx transmit RAM start address + + OTG_HS_HOST 0x40040400 USB on the go high speed + + HCFG 0x0 - OTG_HS host configuration register + _ :: Bits 29 -- (Reserved) + FSLSS :: Bit -- FS- and LS-only support + FSLSPCS :: Bits 2 -- FS/LS PHY clock select + + HFIR 0x4 - OTG_HS Host frame interval register + _ :: Bits 16 -- (Reserved) + FRIVL :: Bits 16 -- Frame interval + + HFNUM 0x8 - OTG_HS host frame number/frame time remaining register + FTREM :: Bits 16 -- Frame time remaining + FRNUM :: Bits 16 -- Frame number + + HPTXSTS 0x10 - OTG_HS_Host periodic transmit FIFO/queue status register + PTXQTOP :: Bits 8 -- Top of the periodic transmit request queue + PTXQSAV :: Bits 8 -- Periodic transmit request queue space available + PTXFSAVL :: Bits 16 -- Periodic transmit data FIFO space available + + HAINT 0x14 - OTG_HS Host all channels interrupt register + _ :: Bits 16 -- (Reserved) + HAINT :: Bits 16 -- Channel interrupts + + HAINTMSK 0x18 - OTG_HS host all channels interrupt mask register + _ :: Bits 16 -- (Reserved) + HAINTM :: Bits 16 -- Channel interrupt mask + + HPRT 0x40 - OTG_HS host port control and status register + _ :: Bits 13 -- (Reserved) + PSPD :: Bits 2 -- Port speed + PTCTL :: Bits 4 -- Port test control + PPWR :: Bit -- Port power + PLSTS :: Bits 2 -- Port line status + _ :: Bit -- (Reserved) + PRST :: Bit -- Port reset + PSUSP :: Bit -- Port suspend + PRES :: Bit -- Port resume + POCCHNG :: Bit -- Port overcurrent change + POCA :: Bit -- Port overcurrent active + PENCHNG :: Bit -- Port enable/disable change + PENA :: Bit -- Port enable + PCDET :: Bit -- Port connect detected + PCSTS :: Bit -- Port connect status + + CHAR 0x100 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x104 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x108 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x10c - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x110 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x114 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x120 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x124 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x128 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x12c - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x130 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x134 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x140 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x144 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x148 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x14c - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x150 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x154 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x160 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x164 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x168 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x16c - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x170 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x174 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x180 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x184 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x188 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x18c - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x190 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x194 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x1a0 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x1a4 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x1a8 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x1ac - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x1b0 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x1b4 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x1c0 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x1c4 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x1c8 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x1cc - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x1d0 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x1d4 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x1e0 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x1e4 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x1e8 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x1ec - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x1f0 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x1f4 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x200 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x204 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x208 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x20c - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x210 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x214 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x220 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x224 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x228 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x22c - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x230 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x234 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x240 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x244 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x248 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x24c - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x250 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x254 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CHAR 0x260 - OTG_HS host channel-0 characteristics register + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MC :: Bits 2 -- Multi Count (MC) / Error Count (EC) + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + SPLT 0x264 - OTG_HS host channel-0 split control register + SPLITEN :: Bit -- Split enable + _ :: Bits 14 -- (Reserved) + COMPLSPLT :: Bit -- Do complete split + XACTPOS :: Bits 2 -- XACTPOS + HUBADDR :: Bits 7 -- Hub address + PRTADDR :: Bits 7 -- Port address + + INT 0x268 - OTG_HS host channel-11 interrupt register + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + NYET :: Bit -- Response received interrupt + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + AHBERR :: Bit -- AHB error + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x26c - OTG_HS host channel-11 interrupt mask register + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + AHBERR :: Bit -- AHB error + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x270 - OTG_HS host channel-11 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x274 - OTG_HS host channel-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + OTG_HS_DEVICE 0x40040800 USB on the go high speed + + DCFG 0x0 - OTG_HS device configuration register + _ :: Bits 6 -- (Reserved) + PERSCHIVL :: Bits 2 -- Periodic scheduling interval + _ :: Bits 11 -- (Reserved) + PFIVL :: Bits 2 -- Periodic (micro)frame interval + DAD :: Bits 7 -- Device address + _ :: Bit -- (Reserved) + NZLSOHSK :: Bit -- Nonzero-length status OUT handshake + DSPD :: Bits 2 -- Device speed + + DCTL 0x4 - OTG_HS device control register + _ :: Bits 20 -- (Reserved) + POPRGDNE :: Bit -- Power-on programming done + CGONAK :: Bit -- Clear global OUT NAK + SGONAK :: Bit -- Set global OUT NAK + CGINAK :: Bit -- Clear global IN NAK + SGINAK :: Bit -- Set global IN NAK + TCTL :: Bits 3 -- Test control + GONSTS :: Bit -- Global OUT NAK status + GINSTS :: Bit -- Global IN NAK status + SDIS :: Bit -- Soft disconnect + RWUSIG :: Bit -- Remote wakeup signaling + + DSTS 0x8 - OTG_HS device status register + _ :: Bits 10 -- (Reserved) + FNSOF :: Bits 14 -- Frame number of the received SOF + _ :: Bits 4 -- (Reserved) + EERR :: Bit -- Erratic error + ENUMSPD :: Bits 2 -- Enumerated speed + SUSPSTS :: Bit -- Suspend status + + DIEPMSK 0x10 - OTG_HS device IN endpoint common interrupt mask register + _ :: Bits 22 -- (Reserved) + BIM :: Bit -- BNA interrupt mask + TXFURM :: Bit -- FIFO underrun mask + _ :: Bit -- (Reserved) + INEPNEM :: Bit -- IN endpoint NAK effective mask + INEPNMM :: Bit -- IN token received with EP mismatch mask + ITTXFEMSK :: Bit -- IN token received when TxFIFO empty mask + TOM :: Bit -- Timeout condition mask (nonisochronous endpoints) + _ :: Bit -- (Reserved) + EPDM :: Bit -- Endpoint disabled interrupt mask + XFRCM :: Bit -- Transfer completed interrupt mask + + DOEPMSK 0x14 - OTG_HS device OUT endpoint common interrupt mask register + _ :: Bits 22 -- (Reserved) + BOIM :: Bit -- BNA interrupt mask + OPEM :: Bit -- OUT packet error mask + _ :: Bit -- (Reserved) + B2BSTUP :: Bit -- Back-to-back SETUP packets received mask + _ :: Bit -- (Reserved) + OTEPDM :: Bit -- OUT token received when endpoint disabled mask + STUPM :: Bit -- SETUP phase done mask + _ :: Bit -- (Reserved) + EPDM :: Bit -- Endpoint disabled interrupt mask + XFRCM :: Bit -- Transfer completed interrupt mask + + DAINT 0x18 - OTG_HS device all endpoints interrupt register + OEPINT :: Bits 16 -- OUT endpoint interrupt bits + IEPINT :: Bits 16 -- IN endpoint interrupt bits + + DAINTMSK 0x1c - OTG_HS all endpoints interrupt mask register + OEPM :: Bits 16 -- OUT EP interrupt mask bits + IEPM :: Bits 16 -- IN EP interrupt mask bits + + DVBUSDIS 0x28 - OTG_HS device VBUS discharge time register + _ :: Bits 16 -- (Reserved) + VBUSDT :: Bits 16 -- Device VBUS discharge time + + DVBUSPULSE 0x2c - OTG_HS device VBUS pulsing time register + _ :: Bits 20 -- (Reserved) + DVBUSP :: Bits 12 -- Device VBUS pulsing time + + DTHRCTL 0x30 - OTG_HS Device threshold control register + _ :: Bits 4 -- (Reserved) + ARPEN :: Bit -- Arbiter parking enable + _ :: Bit -- (Reserved) + RXTHRLEN :: Bits 9 -- Receive threshold length + RXTHREN :: Bit -- Receive threshold enable + _ :: Bits 5 -- (Reserved) + TXTHRLEN :: Bits 9 -- Transmit threshold length + ISOTHREN :: Bit -- ISO IN endpoint threshold enable + NONISOTHREN :: Bit -- Nonisochronous IN endpoints threshold enable + + DIEPEMPMSK 0x34 - OTG_HS device IN endpoint FIFO empty interrupt mask register + _ :: Bits 16 -- (Reserved) + INEPTXFEM :: Bits 16 -- IN EP Tx FIFO empty interrupt mask bits + + DEACHINT 0x38 - OTG_HS device each endpoint interrupt register + _ :: Bits 14 -- (Reserved) + OEP1INT :: Bit -- OUT endpoint 1 interrupt bit + _ :: Bits 15 -- (Reserved) + IEP1INT :: Bit -- IN endpoint 1interrupt bit + _ :: Bit -- (Reserved) + + DEACHINTMSK 0x3c - OTG_HS device each endpoint interrupt register mask + _ :: Bits 14 -- (Reserved) + OEP1INTM :: Bit -- OUT Endpoint 1 interrupt mask bit + _ :: Bits 15 -- (Reserved) + IEP1INTM :: Bit -- IN Endpoint 1 interrupt mask bit + _ :: Bit -- (Reserved) + + DIEPEACHMSK1 0x44 - OTG_HS device each in endpoint-1 interrupt register + _ :: Bits 18 -- (Reserved) + NAKM :: Bit -- NAK interrupt mask + _ :: Bits 3 -- (Reserved) + BIM :: Bit -- BNA interrupt mask + TXFURM :: Bit -- FIFO underrun mask + _ :: Bit -- (Reserved) + INEPNEM :: Bit -- IN endpoint NAK effective mask + INEPNMM :: Bit -- IN token received with EP mismatch mask + ITTXFEMSK :: Bit -- IN token received when TxFIFO empty mask + TOM :: Bit -- Timeout condition mask (nonisochronous endpoints) + _ :: Bit -- (Reserved) + EPDM :: Bit -- Endpoint disabled interrupt mask + XFRCM :: Bit -- Transfer completed interrupt mask + + DOEPEACHMSK1 0x84 - OTG_HS device each OUT endpoint-1 interrupt register + _ :: Bits 17 -- (Reserved) + NYETM :: Bit -- NYET interrupt mask + NAKM :: Bit -- NAK interrupt mask + BERRM :: Bit -- Bubble error interrupt mask + _ :: Bits 2 -- (Reserved) + BIM :: Bit -- BNA interrupt mask + TXFURM :: Bit -- OUT packet error mask + _ :: Bit -- (Reserved) + INEPNEM :: Bit -- IN endpoint NAK effective mask + INEPNMM :: Bit -- IN token received with EP mismatch mask + ITTXFEMSK :: Bit -- IN token received when TxFIFO empty mask + TOM :: Bit -- Timeout condition mask + _ :: Bit -- (Reserved) + EPDM :: Bit -- Endpoint disabled interrupt mask + XFRCM :: Bit -- Transfer completed interrupt mask + + CTL 0x100 - OTG device endpoint-0 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + TXFNUM :: Bits 4 -- TxFIFO number + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even/odd frame + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x108 - OTG device endpoint-0 interrupt register + _ :: Bits 18 -- (Reserved) + NAK :: Bit -- NAK interrupt + BERR :: Bit -- Babble error interrupt + PKTDRPSTS :: Bit -- Packet dropped status + _ :: Bit -- (Reserved) + BNA :: Bit -- Buffer not available interrupt + TXFIFOUDRN :: Bit -- Transmit Fifo Underrun + TXFE :: Bit -- Transmit FIFO empty + INEPNE :: Bit -- IN endpoint NAK effective + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- IN token received when TxFIFO is empty + TOC :: Bit -- Timeout condition + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x110 - OTG_HS device IN endpoint 0 transfer size register + _ :: Bits 11 -- (Reserved) + PKTCNT :: Bits 2 -- Packet count + _ :: Bits 12 -- (Reserved) + XFRSIZ :: Bits 7 -- Transfer size + + DMA 0x114 - OTG_HS device endpoint-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + TXFSTS 0x118 - OTG_HS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail + + CTL 0x120 - OTG device endpoint-1 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + TXFNUM :: Bits 4 -- TxFIFO number + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even/odd frame + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x128 - OTG device endpoint-1 interrupt register + _ :: Bits 18 -- (Reserved) + NAK :: Bit -- NAK interrupt + BERR :: Bit -- Babble error interrupt + PKTDRPSTS :: Bit -- Packet dropped status + _ :: Bit -- (Reserved) + BNA :: Bit -- Buffer not available interrupt + TXFIFOUDRN :: Bit -- Transmit Fifo Underrun + TXFE :: Bit -- Transmit FIFO empty + INEPNE :: Bit -- IN endpoint NAK effective + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- IN token received when TxFIFO is empty + TOC :: Bit -- Timeout condition + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x130 - OTG_HS device endpoint transfer size register + _ :: Bit -- (Reserved) + MCNT :: Bits 2 -- Multi count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x134 - OTG_HS device endpoint-1 DMA address register + DMAADDR :: Bits 32 -- DMA address + + TXFSTS 0x138 - OTG_HS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail + + CTL 0x140 - OTG device endpoint-1 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + TXFNUM :: Bits 4 -- TxFIFO number + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even/odd frame + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x148 - OTG device endpoint-1 interrupt register + _ :: Bits 18 -- (Reserved) + NAK :: Bit -- NAK interrupt + BERR :: Bit -- Babble error interrupt + PKTDRPSTS :: Bit -- Packet dropped status + _ :: Bit -- (Reserved) + BNA :: Bit -- Buffer not available interrupt + TXFIFOUDRN :: Bit -- Transmit Fifo Underrun + TXFE :: Bit -- Transmit FIFO empty + INEPNE :: Bit -- IN endpoint NAK effective + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- IN token received when TxFIFO is empty + TOC :: Bit -- Timeout condition + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x150 - OTG_HS device endpoint transfer size register + _ :: Bit -- (Reserved) + MCNT :: Bits 2 -- Multi count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x154 - OTG_HS device endpoint-1 DMA address register + DMAADDR :: Bits 32 -- DMA address + + TXFSTS 0x158 - OTG_HS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail + + CTL 0x160 - OTG device endpoint-1 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + TXFNUM :: Bits 4 -- TxFIFO number + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even/odd frame + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x168 - OTG device endpoint-1 interrupt register + _ :: Bits 18 -- (Reserved) + NAK :: Bit -- NAK interrupt + BERR :: Bit -- Babble error interrupt + PKTDRPSTS :: Bit -- Packet dropped status + _ :: Bit -- (Reserved) + BNA :: Bit -- Buffer not available interrupt + TXFIFOUDRN :: Bit -- Transmit Fifo Underrun + TXFE :: Bit -- Transmit FIFO empty + INEPNE :: Bit -- IN endpoint NAK effective + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- IN token received when TxFIFO is empty + TOC :: Bit -- Timeout condition + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x170 - OTG_HS device endpoint transfer size register + _ :: Bit -- (Reserved) + MCNT :: Bits 2 -- Multi count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x174 - OTG_HS device endpoint-1 DMA address register + DMAADDR :: Bits 32 -- DMA address + + TXFSTS 0x178 - OTG_HS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail + + CTL 0x180 - OTG device endpoint-1 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + TXFNUM :: Bits 4 -- TxFIFO number + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even/odd frame + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x188 - OTG device endpoint-1 interrupt register + _ :: Bits 18 -- (Reserved) + NAK :: Bit -- NAK interrupt + BERR :: Bit -- Babble error interrupt + PKTDRPSTS :: Bit -- Packet dropped status + _ :: Bit -- (Reserved) + BNA :: Bit -- Buffer not available interrupt + TXFIFOUDRN :: Bit -- Transmit Fifo Underrun + TXFE :: Bit -- Transmit FIFO empty + INEPNE :: Bit -- IN endpoint NAK effective + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- IN token received when TxFIFO is empty + TOC :: Bit -- Timeout condition + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x190 - OTG_HS device endpoint transfer size register + _ :: Bit -- (Reserved) + MCNT :: Bits 2 -- Multi count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x194 - OTG_HS device endpoint-1 DMA address register + DMAADDR :: Bits 32 -- DMA address + + TXFSTS 0x198 - OTG_HS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail + + CTL 0x1a0 - OTG device endpoint-1 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + TXFNUM :: Bits 4 -- TxFIFO number + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even/odd frame + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x1a8 - OTG device endpoint-1 interrupt register + _ :: Bits 18 -- (Reserved) + NAK :: Bit -- NAK interrupt + BERR :: Bit -- Babble error interrupt + PKTDRPSTS :: Bit -- Packet dropped status + _ :: Bit -- (Reserved) + BNA :: Bit -- Buffer not available interrupt + TXFIFOUDRN :: Bit -- Transmit Fifo Underrun + TXFE :: Bit -- Transmit FIFO empty + INEPNE :: Bit -- IN endpoint NAK effective + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- IN token received when TxFIFO is empty + TOC :: Bit -- Timeout condition + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x1b0 - OTG_HS device endpoint transfer size register + _ :: Bit -- (Reserved) + MCNT :: Bits 2 -- Multi count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x1b4 - OTG_HS device endpoint-1 DMA address register + DMAADDR :: Bits 32 -- DMA address + + TXFSTS 0x1b8 - OTG_HS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail + + CTL 0x300 - OTG_HS device control OUT endpoint 0 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + _ :: Bits 2 -- (Reserved) + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- Snoop mode + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + _ :: Bit -- (Reserved) + USBAEP :: Bit -- USB active endpoint + _ :: Bits 13 -- (Reserved) + MPSIZ :: Bits 2 -- Maximum packet size + + INT 0x308 - OTG_HS device endpoint-0 interrupt register + _ :: Bits 17 -- (Reserved) + NYET :: Bit -- NYET interrupt + _ :: Bits 7 -- (Reserved) + B2BSTUP :: Bit -- Back-to-back SETUP packets received + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OUT token received when endpoint disabled + STUP :: Bit -- SETUP phase done + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x310 - OTG_HS device endpoint-1 transfer size register + _ :: Bit -- (Reserved) + STUPCNT :: Bits 2 -- SETUP packet count + _ :: Bits 9 -- (Reserved) + PKTCNT :: Bit -- Packet count + _ :: Bits 12 -- (Reserved) + XFRSIZ :: Bits 7 -- Transfer size + + DMA 0x314 - OTG_HS device endpoint-0 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CTL 0x320 - OTG device endpoint-1 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID/Set even frame + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- Snoop mode + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even odd frame/Endpoint data PID + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x328 - OTG_HS device endpoint-1 interrupt register + _ :: Bits 17 -- (Reserved) + NYET :: Bit -- NYET interrupt + _ :: Bits 7 -- (Reserved) + B2BSTUP :: Bit -- Back-to-back SETUP packets received + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OUT token received when endpoint disabled + STUP :: Bit -- SETUP phase done + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x330 - OTG_HS device endpoint-2 transfer size register + _ :: Bit -- (Reserved) + RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x334 - OTG_HS device endpoint-1 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CTL 0x340 - OTG device endpoint-1 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID/Set even frame + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- Snoop mode + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even odd frame/Endpoint data PID + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x348 - OTG_HS device endpoint-1 interrupt register + _ :: Bits 17 -- (Reserved) + NYET :: Bit -- NYET interrupt + _ :: Bits 7 -- (Reserved) + B2BSTUP :: Bit -- Back-to-back SETUP packets received + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OUT token received when endpoint disabled + STUP :: Bit -- SETUP phase done + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x350 - OTG_HS device endpoint-2 transfer size register + _ :: Bit -- (Reserved) + RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x354 - OTG_HS device endpoint-1 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CTL 0x360 - OTG device endpoint-1 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID/Set even frame + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- Snoop mode + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even odd frame/Endpoint data PID + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x368 - OTG_HS device endpoint-1 interrupt register + _ :: Bits 17 -- (Reserved) + NYET :: Bit -- NYET interrupt + _ :: Bits 7 -- (Reserved) + B2BSTUP :: Bit -- Back-to-back SETUP packets received + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OUT token received when endpoint disabled + STUP :: Bit -- SETUP phase done + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x370 - OTG_HS device endpoint-2 transfer size register + _ :: Bit -- (Reserved) + RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x374 - OTG_HS device endpoint-1 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CTL 0x380 - OTG device endpoint-1 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID/Set even frame + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- Snoop mode + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even odd frame/Endpoint data PID + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x388 - OTG_HS device endpoint-1 interrupt register + _ :: Bits 17 -- (Reserved) + NYET :: Bit -- NYET interrupt + _ :: Bits 7 -- (Reserved) + B2BSTUP :: Bit -- Back-to-back SETUP packets received + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OUT token received when endpoint disabled + STUP :: Bit -- SETUP phase done + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x390 - OTG_HS device endpoint-2 transfer size register + _ :: Bit -- (Reserved) + RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x394 - OTG_HS device endpoint-1 DMA address register + DMAADDR :: Bits 32 -- DMA address + + CTL 0x3a0 - OTG device endpoint-1 control register + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + SODDFRM :: Bit -- Set odd frame + SD0PID_SEVNFRM :: Bit -- Set DATA0 PID/Set even frame + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- Snoop mode + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + EONUM_DPID :: Bit -- Even odd frame/Endpoint data PID + USBAEP :: Bit -- USB active endpoint + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x3a8 - OTG_HS device endpoint-1 interrupt register + _ :: Bits 17 -- (Reserved) + NYET :: Bit -- NYET interrupt + _ :: Bits 7 -- (Reserved) + B2BSTUP :: Bit -- Back-to-back SETUP packets received + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OUT token received when endpoint disabled + STUP :: Bit -- SETUP phase done + _ :: Bit -- (Reserved) + EPDISD :: Bit -- Endpoint disabled interrupt + XFRC :: Bit -- Transfer completed interrupt + + TSIZ 0x3b0 - OTG_HS device endpoint-2 transfer size register + _ :: Bit -- (Reserved) + RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + DMA 0x3b4 - OTG_HS device endpoint-1 DMA address register + DMAADDR :: Bits 32 -- DMA address + + OTG_HS_PWRCLK 0x40040e00 USB on the go high speed + + PCGCCTL 0x0 - Power and clock gating control register + _ :: Bits 27 -- (Reserved) + PHYSUSP :: Bit -- PHY suspended + _ :: Bits 2 -- (Reserved) + GATEHCLK :: Bit -- Gate HCLK + STPPCLK :: Bit -- Stop PHY clock + + OTG_FS_GLOBAL 0x50000000 USB on the go full speed + + GOTGCTL 0x0 - OTG_FS control and status register (OTG_FS_GOTGCTL) + _ :: Bits 12 -- (Reserved) + BSVLD :: Bit -- B-session valid + ASVLD :: Bit -- A-session valid + DBCT :: Bit -- Long/short debounce time + CIDSTS :: Bit -- Connector ID status + _ :: Bits 4 -- (Reserved) + DHNPEN :: Bit -- Device HNP enabled + HSHNPEN :: Bit -- Host set HNP enable + HNPRQ :: Bit -- HNP request + HNGSCS :: Bit -- Host negotiation success + _ :: Bits 6 -- (Reserved) + SRQ :: Bit -- Session request + SRQSCS :: Bit -- Session request success + + GOTGINT 0x4 - OTG_FS interrupt register (OTG_FS_GOTGINT) + _ :: Bits 12 -- (Reserved) + DBCDNE :: Bit -- Debounce done + ADTOCHG :: Bit -- A-device timeout change + HNGDET :: Bit -- Host negotiation detected + _ :: Bits 7 -- (Reserved) + HNSSCHG :: Bit -- Host negotiation success status change + SRSSCHG :: Bit -- Session request success status change + _ :: Bits 5 -- (Reserved) + SEDET :: Bit -- Session end detected + _ :: Bits 2 -- (Reserved) + + GAHBCFG 0x8 - OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + _ :: Bits 23 -- (Reserved) + PTXFELVL :: Bit -- Periodic TxFIFO empty level + TXFELVL :: Bit -- TxFIFO empty level + _ :: Bits 6 -- (Reserved) + GINT :: Bit -- Global interrupt mask + + GUSBCFG 0xc - OTG_FS USB configuration register (OTG_FS_GUSBCFG) + CTXPKT :: Bit -- Corrupt Tx packet + FDMOD :: Bit -- Force device mode + FHMOD :: Bit -- Force host mode + _ :: Bits 15 -- (Reserved) + TRDT :: Bits 4 -- USB turnaround time + HNPCAP :: Bit -- HNP-capable + SRPCAP :: Bit -- SRP-capable + _ :: Bit -- (Reserved) + PHYSEL :: Bit -- Full Speed serial transceiver select + _ :: Bits 3 -- (Reserved) + TOCAL :: Bits 3 -- FS timeout calibration + + GRSTCTL 0x10 - OTG_FS reset register (OTG_FS_GRSTCTL) + AHBIDL :: Bit -- AHB master idle + _ :: Bits 20 -- (Reserved) + TXFNUM :: Bits 5 -- TxFIFO number + TXFFLSH :: Bit -- TxFIFO flush + RXFFLSH :: Bit -- RxFIFO flush + _ :: Bit -- (Reserved) + FCRST :: Bit -- Host frame counter reset + HSRST :: Bit -- HCLK soft reset + CSRST :: Bit -- Core soft reset + + GINTSTS 0x14 - OTG_FS core interrupt register (OTG_FS_GINTSTS) + WKUPINT :: Bit -- Resume/remote wakeup detected interrupt + SRQINT :: Bit -- Session request/new session detected interrupt + DISCINT :: Bit -- Disconnect detected interrupt + CIDSCHG :: Bit -- Connector ID status change + _ :: Bit -- (Reserved) + PTXFE :: Bit -- Periodic TxFIFO empty + HCINT :: Bit -- Host channels interrupt + HPRTINT :: Bit -- Host port interrupt + _ :: Bits 2 -- (Reserved) + IPXFR_INCOMPISOOUT :: Bit -- Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + IISOIXFR :: Bit -- Incomplete isochronous IN transfer + OEPINT :: Bit -- OUT endpoint interrupt + IEPINT :: Bit -- IN endpoint interrupt + _ :: Bits 2 -- (Reserved) + EOPF :: Bit -- End of periodic frame interrupt + ISOODRP :: Bit -- Isochronous OUT packet dropped interrupt + ENUMDNE :: Bit -- Enumeration done + USBRST :: Bit -- USB reset + USBSUSP :: Bit -- USB suspend + ESUSP :: Bit -- Early suspend + _ :: Bits 2 -- (Reserved) + GOUTNAKEFF :: Bit -- Global OUT NAK effective + GINAKEFF :: Bit -- Global IN non-periodic NAK effective + NPTXFE :: Bit -- Non-periodic TxFIFO empty + RXFLVL :: Bit -- RxFIFO non-empty + SOF :: Bit -- Start of frame + OTGINT :: Bit -- OTG interrupt + MMIS :: Bit -- Mode mismatch interrupt + CMOD :: Bit -- Current mode of operation + + GINTMSK 0x18 - OTG_FS interrupt mask register (OTG_FS_GINTMSK) + WUIM :: Bit -- Resume/remote wakeup detected interrupt mask + SRQIM :: Bit -- Session request/new session detected interrupt mask + DISCINT :: Bit -- Disconnect detected interrupt mask + CIDSCHGM :: Bit -- Connector ID status change mask + _ :: Bit -- (Reserved) + PTXFEM :: Bit -- Periodic TxFIFO empty mask + HCIM :: Bit -- Host channels interrupt mask + PRTIM :: Bit -- Host port interrupt mask + _ :: Bits 2 -- (Reserved) + IPXFRM_IISOOXFRM :: Bit -- Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + IISOIXFRM :: Bit -- Incomplete isochronous IN transfer mask + OEPINT :: Bit -- OUT endpoints interrupt mask + IEPINT :: Bit -- IN endpoints interrupt mask + EPMISM :: Bit -- Endpoint mismatch interrupt mask + _ :: Bit -- (Reserved) + EOPFM :: Bit -- End of periodic frame interrupt mask + ISOODRPM :: Bit -- Isochronous OUT packet dropped interrupt mask + ENUMDNEM :: Bit -- Enumeration done mask + USBRST :: Bit -- USB reset mask + USBSUSPM :: Bit -- USB suspend mask + ESUSPM :: Bit -- Early suspend mask + _ :: Bits 2 -- (Reserved) + GONAKEFFM :: Bit -- Global OUT NAK effective mask + GINAKEFFM :: Bit -- Global non-periodic IN NAK effective mask + NPTXFEM :: Bit -- Non-periodic TxFIFO empty mask + RXFLVLM :: Bit -- Receive FIFO non-empty mask + SOFM :: Bit -- Start of frame mask + OTGINT :: Bit -- OTG interrupt mask + MMISM :: Bit -- Mode mismatch interrupt mask + _ :: Bit -- (Reserved) + + GRXSTSR_Device 0x1c - OTG_FS Receive status debug read(Device mode) + _ :: Bits 7 -- (Reserved) + FRMNUM :: Bits 4 -- Frame number + PKTSTS :: Bits 4 -- Packet status + DPID :: Bits 2 -- Data PID + BCNT :: Bits 11 -- Byte count + EPNUM :: Bits 4 -- Endpoint number + + GRXSTSR_Host 0x1c - OTG status debug read (host mode) + _ :: Bits 11 -- (Reserved) + PKTSTS :: Bits 4 -- Packet status + DPID :: Bits 2 -- Data PID + BCNT :: Bits 11 -- Byte count + CHNUM :: Bits 4 -- Channel number + + GRXSTSP_Device 0x20 - OTG status read and pop (device mode) + _ :: Bits 7 -- (Reserved) + FRMNUM :: Bits 4 -- Frame number + PKTSTS :: Bits 4 -- Packet status + DPID :: Bits 2 -- Data PID + BCNT :: Bits 11 -- Byte count + EPNUM :: Bits 4 -- Endpoint number + + GRXSTSP_Host 0x20 - OTG status read and pop (host mode) + _ :: Bits 11 -- (Reserved) + PKTSTS :: Bits 4 -- Packet status + DPID :: Bits 2 -- Data PID + BCNT :: Bits 11 -- Byte count + CHNUM :: Bits 4 -- Channel number + + GRXFSIZ 0x24 - OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + _ :: Bits 16 -- (Reserved) + RXFD :: Bits 16 -- RxFIFO depth + + DIEPTXF0 0x28 - OTG_FS non-periodic transmit FIFO size register (Device mode) + TX0FD :: Bits 16 -- Endpoint 0 TxFIFO depth + TX0FSA :: Bits 16 -- Endpoint 0 transmit RAM start address + + HNPTXFSIZ 0x28 - OTG_FS non-periodic transmit FIFO size register (Host mode) + NPTXFD :: Bits 16 -- Non-periodic TxFIFO depth + NPTXFSA :: Bits 16 -- Non-periodic transmit RAM start address + + GNPTXSTS 0x2c - OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) + _ :: Bit -- (Reserved) + NPTXQTOP :: Bits 7 -- Top of the non-periodic transmit request queue + NPTQXSAV :: Bits 8 -- Non-periodic transmit request queue space available + NPTXFSAV :: Bits 16 -- Non-periodic TxFIFO space available + + GCCFG 0x38 - OTG_FS general core configuration register (OTG_FS_GCCFG) + _ :: Bits 10 -- (Reserved) + NOVBUSSENS :: Bit -- Vbus sensing disable option + SOFOUTEN :: Bit -- SOF output enable + VBUSBSEN :: Bit -- Enable the VBUS sensing device + VBUSASEN :: Bit -- Enable the VBUS sensing device + _ :: Bit -- (Reserved) + PWRDWN :: Bit -- Power down + _ :: Bits 16 -- (Reserved) + + CID 0x3c - core ID register + PRODUCT_ID :: Bits 32 -- Product ID field + + HPTXFSIZ 0x100 - OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + PTXFSIZ :: Bits 16 -- Host periodic TxFIFO depth + PTXSA :: Bits 16 -- Host periodic TxFIFO start address + + DIEPTXF1 0x104 - OTF_FS device IN endpoint transmit FIFO size register + INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth + INEPTXSA :: Bits 16 -- IN endpoint FIFO2 transmit RAM start address + + DIEPTXF2 0x108 - OTF_FS device IN endpoint transmit FIFO size register + INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth + INEPTXSA :: Bits 16 -- IN endpoint FIFO2 transmit RAM start address + + DIEPTXF3 0x10c - OTF_FS device IN endpoint transmit FIFO size register + INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth + INEPTXSA :: Bits 16 -- IN endpoint FIFO2 transmit RAM start address + + DIEPTXF4 0x110 - OTF_FS device IN endpoint transmit FIFO size register + INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth + INEPTXSA :: Bits 16 -- IN endpoint FIFO2 transmit RAM start address + + DIEPTXF5 0x114 - OTF_FS device IN endpoint transmit FIFO size register + INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth + INEPTXSA :: Bits 16 -- IN endpoint FIFO2 transmit RAM start address + + OTG_FS_HOST 0x50000400 USB on the go full speed + + HCFG 0x0 - OTG_FS host configuration register (OTG_FS_HCFG) + _ :: Bits 29 -- (Reserved) + FSLSS :: Bit -- FS- and LS-only support + FSLSPCS :: Bits 2 -- FS/LS PHY clock select + + HFIR 0x4 - OTG_FS Host frame interval register + _ :: Bits 16 -- (Reserved) + FRIVL :: Bits 16 -- Frame interval + + HFNUM 0x8 - OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) + FTREM :: Bits 16 -- Frame time remaining + FRNUM :: Bits 16 -- Frame number + + HPTXSTS 0x10 - OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) + PTXQTOP :: Bits 8 -- Top of the periodic transmit request queue + PTXQSAV :: Bits 8 -- Periodic transmit request queue space available + PTXFSAVL :: Bits 16 -- Periodic transmit data FIFO space available + + HAINT 0x14 - OTG_FS Host all channels interrupt register + _ :: Bits 16 -- (Reserved) + HAINT :: Bits 16 -- Channel interrupts + + HAINTMSK 0x18 - OTG_FS host all channels interrupt mask register + _ :: Bits 16 -- (Reserved) + HAINTM :: Bits 16 -- Channel interrupt mask + + HPRT 0x40 - OTG_FS host port control and status register (OTG_FS_HPRT) + _ :: Bits 13 -- (Reserved) + PSPD :: Bits 2 -- Port speed + PTCTL :: Bits 4 -- Port test control + PPWR :: Bit -- Port power + PLSTS :: Bits 2 -- Port line status + _ :: Bit -- (Reserved) + PRST :: Bit -- Port reset + PSUSP :: Bit -- Port suspend + PRES :: Bit -- Port resume + POCCHNG :: Bit -- Port overcurrent change + POCA :: Bit -- Port overcurrent active + PENCHNG :: Bit -- Port enable/disable change + PENA :: Bit -- Port enable + PCDET :: Bit -- Port connect detected + PCSTS :: Bit -- Port connect status + + CHAR 0x100 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x108 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x10c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x110 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x120 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x128 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x12c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x130 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x140 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x148 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x14c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x150 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x160 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x168 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x16c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x170 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x180 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x188 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x18c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x190 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x1a0 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x1a8 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x1ac - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x1b0 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x1c0 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x1c8 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x1cc - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x1d0 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x1e0 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x1e8 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x1ec - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x1f0 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x200 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x208 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x20c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x210 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x220 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x228 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x22c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x230 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x240 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x248 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x24c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x250 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CHAR 0x260 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + CHENA :: Bit -- Channel enable + CHDIS :: Bit -- Channel disable + ODDFRM :: Bit -- Odd frame + DAD :: Bits 7 -- Device address + MCNT :: Bits 2 -- Multicount + EPTYP :: Bits 2 -- Endpoint type + LSDEV :: Bit -- Low-speed device + _ :: Bit -- (Reserved) + EPDIR :: Bit -- Endpoint direction + EPNUM :: Bits 4 -- Endpoint number + MPSIZ :: Bits 11 -- Maximum packet size + + INT 0x268 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + _ :: Bits 21 -- (Reserved) + DTERR :: Bit -- Data toggle error + FRMOR :: Bit -- Frame overrun + BBERR :: Bit -- Babble error + TXERR :: Bit -- Transaction error + _ :: Bit -- (Reserved) + ACK :: Bit -- ACK response received/transmitted interrupt + NAK :: Bit -- NAK response received interrupt + STALL :: Bit -- STALL response received interrupt + _ :: Bit -- (Reserved) + CHH :: Bit -- Channel halted + XFRC :: Bit -- Transfer completed + + INTMSK 0x26c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + _ :: Bits 21 -- (Reserved) + DTERRM :: Bit -- Data toggle error mask + FRMORM :: Bit -- Frame overrun mask + BBERRM :: Bit -- Babble error mask + TXERRM :: Bit -- Transaction error mask + NYET :: Bit -- response received interrupt mask + ACKM :: Bit -- ACK response received/transmitted interrupt mask + NAKM :: Bit -- NAK response received interrupt mask + STALLM :: Bit -- STALL response received interrupt mask + _ :: Bit -- (Reserved) + CHHM :: Bit -- Channel halted mask + XFRCM :: Bit -- Transfer completed mask + + TSIZ 0x270 - OTG_FS host channel-0 transfer size register + _ :: Bit -- (Reserved) + DPID :: Bits 2 -- Data PID + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + OTG_FS_DEVICE 0x50000800 USB on the go full speed + + DCFG 0x0 - OTG_FS device configuration register (OTG_FS_DCFG) + _ :: Bits 19 -- (Reserved) + PFIVL :: Bits 2 -- Periodic frame interval + DAD :: Bits 7 -- Device address + _ :: Bit -- (Reserved) + NZLSOHSK :: Bit -- Non-zero-length status OUT handshake + DSPD :: Bits 2 -- Device speed + + DCTL 0x4 - OTG_FS device control register (OTG_FS_DCTL) + _ :: Bits 20 -- (Reserved) + POPRGDNE :: Bit -- Power-on programming done + CGONAK :: Bit -- Clear global OUT NAK + SGONAK :: Bit -- Set global OUT NAK + CGINAK :: Bit -- Clear global IN NAK + SGINAK :: Bit -- Set global IN NAK + TCTL :: Bits 3 -- Test control + GONSTS :: Bit -- Global OUT NAK status + GINSTS :: Bit -- Global IN NAK status + SDIS :: Bit -- Soft disconnect + RWUSIG :: Bit -- Remote wakeup signaling + + DSTS 0x8 - OTG_FS device status register (OTG_FS_DSTS) + _ :: Bits 10 -- (Reserved) + FNSOF :: Bits 14 -- Frame number of the received SOF + _ :: Bits 4 -- (Reserved) + EERR :: Bit -- Erratic error + ENUMSPD :: Bits 2 -- Enumerated speed + SUSPSTS :: Bit -- Suspend status + + DIEPMSK 0x10 - OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) + _ :: Bits 25 -- (Reserved) + INEPNEM :: Bit -- IN endpoint NAK effective mask + INEPNMM :: Bit -- IN token received with EP mismatch mask + ITTXFEMSK :: Bit -- IN token received when TxFIFO empty mask + TOM :: Bit -- Timeout condition mask (Non-isochronous endpoints) + _ :: Bit -- (Reserved) + EPDM :: Bit -- Endpoint disabled interrupt mask + XFRCM :: Bit -- Transfer completed interrupt mask + + DOEPMSK 0x14 - OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) + _ :: Bits 27 -- (Reserved) + OTEPDM :: Bit -- OUT token received when endpoint disabled mask + STUPM :: Bit -- SETUP phase done mask + _ :: Bit -- (Reserved) + EPDM :: Bit -- Endpoint disabled interrupt mask + XFRCM :: Bit -- Transfer completed interrupt mask + + DAINT 0x18 - OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + OEPINT :: Bits 16 -- OUT endpoint interrupt bits + IEPINT :: Bits 16 -- IN endpoint interrupt bits + + DAINTMSK 0x1c - OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + OEPM :: Bits 16 -- OUT EP interrupt mask bits + IEPM :: Bits 16 -- IN EP interrupt mask bits + + DVBUSDIS 0x28 - OTG_FS device VBUS discharge time register + _ :: Bits 16 -- (Reserved) + VBUSDT :: Bits 16 -- Device VBUS discharge time + + DVBUSPULSE 0x2c - OTG_FS device VBUS pulsing time register + _ :: Bits 20 -- (Reserved) + DVBUSP :: Bits 12 -- Device VBUS pulsing time + + DIEPEMPMSK 0x34 - OTG_FS device IN endpoint FIFO empty interrupt mask register + _ :: Bits 16 -- (Reserved) + INEPTXFEM :: Bits 16 -- IN EP Tx FIFO empty interrupt mask bits + + CTL 0x100 - OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) + EPENA :: Bit -- Endpoint enable + EPDIS :: Bit -- Endpoint disable + _ :: Bits 2 -- (Reserved) + SNAK :: Bit -- Set NAK + CNAK :: Bit -- Clear NAK + TXFNUM :: Bits 4 -- TxFIFO number + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- Endpoint type + NAKSTS :: Bit -- NAK status + _ :: Bit -- (Reserved) + USBAEP :: Bit -- USB active endpoint + _ :: Bits 13 -- (Reserved) + MPSIZ :: Bits 2 -- Maximum packet size + + INT 0x108 - device endpoint-x interrupt register + _ :: Bits 24 -- (Reserved) + TXFE :: Bit -- TXFE + INEPNE :: Bit -- INEPNE + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- ITTXFE + TOC :: Bit -- TOC + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x110 - device endpoint-0 transfer size register + _ :: Bits 11 -- (Reserved) + PKTCNT :: Bits 2 -- Packet count + _ :: Bits 12 -- (Reserved) + XFRSIZ :: Bits 7 -- Transfer size + + TXFSTS 0x118 - OTG_FS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available + + CTL 0x120 - OTG device endpoint-1 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + SODDFRM_SD1PID :: Bit -- SODDFRM/SD1PID + SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + TXFNUM :: Bits 4 -- TXFNUM + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + EONUM_DPID :: Bit -- EONUM/DPID + USBAEP :: Bit -- USBAEP + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- MPSIZ + + INT 0x128 - device endpoint-1 interrupt register + _ :: Bits 24 -- (Reserved) + TXFE :: Bit -- TXFE + INEPNE :: Bit -- INEPNE + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- ITTXFE + TOC :: Bit -- TOC + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x130 - device endpoint-1 transfer size register + _ :: Bit -- (Reserved) + MCNT :: Bits 2 -- Multi count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + TXFSTS 0x138 - OTG_FS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available + + CTL 0x140 - OTG device endpoint-1 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + SODDFRM_SD1PID :: Bit -- SODDFRM/SD1PID + SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + TXFNUM :: Bits 4 -- TXFNUM + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + EONUM_DPID :: Bit -- EONUM/DPID + USBAEP :: Bit -- USBAEP + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- MPSIZ + + INT 0x148 - device endpoint-1 interrupt register + _ :: Bits 24 -- (Reserved) + TXFE :: Bit -- TXFE + INEPNE :: Bit -- INEPNE + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- ITTXFE + TOC :: Bit -- TOC + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x150 - device endpoint-1 transfer size register + _ :: Bit -- (Reserved) + MCNT :: Bits 2 -- Multi count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + TXFSTS 0x158 - OTG_FS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available + + CTL 0x160 - OTG device endpoint-1 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + SODDFRM_SD1PID :: Bit -- SODDFRM/SD1PID + SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + TXFNUM :: Bits 4 -- TXFNUM + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + EONUM_DPID :: Bit -- EONUM/DPID + USBAEP :: Bit -- USBAEP + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- MPSIZ + + INT 0x168 - device endpoint-1 interrupt register + _ :: Bits 24 -- (Reserved) + TXFE :: Bit -- TXFE + INEPNE :: Bit -- INEPNE + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- ITTXFE + TOC :: Bit -- TOC + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x170 - device endpoint-1 transfer size register + _ :: Bit -- (Reserved) + MCNT :: Bits 2 -- Multi count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + TXFSTS 0x178 - OTG_FS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available + + CTL 0x180 - OTG device endpoint-1 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + SODDFRM_SD1PID :: Bit -- SODDFRM/SD1PID + SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + TXFNUM :: Bits 4 -- TXFNUM + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + EONUM_DPID :: Bit -- EONUM/DPID + USBAEP :: Bit -- USBAEP + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- MPSIZ + + INT 0x188 - device endpoint-1 interrupt register + _ :: Bits 24 -- (Reserved) + TXFE :: Bit -- TXFE + INEPNE :: Bit -- INEPNE + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- ITTXFE + TOC :: Bit -- TOC + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x190 - device endpoint-1 transfer size register + _ :: Bit -- (Reserved) + MCNT :: Bits 2 -- Multi count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + TXFSTS 0x198 - OTG_FS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available + + CTL 0x1a0 - OTG device endpoint-1 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + SODDFRM_SD1PID :: Bit -- SODDFRM/SD1PID + SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + TXFNUM :: Bits 4 -- TXFNUM + STALL :: Bit -- STALL handshake + _ :: Bit -- (Reserved) + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + EONUM_DPID :: Bit -- EONUM/DPID + USBAEP :: Bit -- USBAEP + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- MPSIZ + + INT 0x1a8 - device endpoint-1 interrupt register + _ :: Bits 24 -- (Reserved) + TXFE :: Bit -- TXFE + INEPNE :: Bit -- INEPNE + _ :: Bit -- (Reserved) + ITTXFE :: Bit -- ITTXFE + TOC :: Bit -- TOC + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x1b0 - device endpoint-1 transfer size register + _ :: Bit -- (Reserved) + MCNT :: Bits 2 -- Multi count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + TXFSTS 0x1b8 - OTG_FS device IN endpoint transmit FIFO status register + _ :: Bits 16 -- (Reserved) + INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available + + CTL 0x300 - device endpoint-0 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + _ :: Bits 2 -- (Reserved) + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- SNPM + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + _ :: Bit -- (Reserved) + USBAEP :: Bit -- USBAEP + _ :: Bits 13 -- (Reserved) + MPSIZ :: Bits 2 -- MPSIZ + + INT 0x308 - device endpoint-0 interrupt register + _ :: Bits 25 -- (Reserved) + B2BSTUP :: Bit -- B2BSTUP + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OTEPDIS + STUP :: Bit -- STUP + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x310 - device OUT endpoint-0 transfer size register + _ :: Bit -- (Reserved) + STUPCNT :: Bits 2 -- SETUP packet count + _ :: Bits 9 -- (Reserved) + PKTCNT :: Bit -- Packet count + _ :: Bits 12 -- (Reserved) + XFRSIZ :: Bits 7 -- Transfer size + + CTL 0x320 - device endpoint-1 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + SODDFRM :: Bit -- SODDFRM + SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- SNPM + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + EONUM_DPID :: Bit -- EONUM/DPID + USBAEP :: Bit -- USBAEP + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- MPSIZ + + INT 0x328 - device endpoint-1 interrupt register + _ :: Bits 25 -- (Reserved) + B2BSTUP :: Bit -- B2BSTUP + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OTEPDIS + STUP :: Bit -- STUP + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x330 - device OUT endpoint-1 transfer size register + _ :: Bit -- (Reserved) + RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CTL 0x340 - device endpoint-1 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + SODDFRM :: Bit -- SODDFRM + SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- SNPM + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + EONUM_DPID :: Bit -- EONUM/DPID + USBAEP :: Bit -- USBAEP + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- MPSIZ + + INT 0x348 - device endpoint-1 interrupt register + _ :: Bits 25 -- (Reserved) + B2BSTUP :: Bit -- B2BSTUP + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OTEPDIS + STUP :: Bit -- STUP + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x350 - device OUT endpoint-1 transfer size register + _ :: Bit -- (Reserved) + RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CTL 0x360 - device endpoint-1 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + SODDFRM :: Bit -- SODDFRM + SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- SNPM + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + EONUM_DPID :: Bit -- EONUM/DPID + USBAEP :: Bit -- USBAEP + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- MPSIZ + + INT 0x368 - device endpoint-1 interrupt register + _ :: Bits 25 -- (Reserved) + B2BSTUP :: Bit -- B2BSTUP + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OTEPDIS + STUP :: Bit -- STUP + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x370 - device OUT endpoint-1 transfer size register + _ :: Bit -- (Reserved) + RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CTL 0x380 - device endpoint-1 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + SODDFRM :: Bit -- SODDFRM + SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- SNPM + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + EONUM_DPID :: Bit -- EONUM/DPID + USBAEP :: Bit -- USBAEP + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- MPSIZ + + INT 0x388 - device endpoint-1 interrupt register + _ :: Bits 25 -- (Reserved) + B2BSTUP :: Bit -- B2BSTUP + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OTEPDIS + STUP :: Bit -- STUP + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x390 - device OUT endpoint-1 transfer size register + _ :: Bit -- (Reserved) + RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + CTL 0x3a0 - device endpoint-1 control register + EPENA :: Bit -- EPENA + EPDIS :: Bit -- EPDIS + SODDFRM :: Bit -- SODDFRM + SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM + SNAK :: Bit -- SNAK + CNAK :: Bit -- CNAK + _ :: Bits 4 -- (Reserved) + STALL :: Bit -- STALL handshake + SNPM :: Bit -- SNPM + EPTYP :: Bits 2 -- EPTYP + NAKSTS :: Bit -- NAKSTS + EONUM_DPID :: Bit -- EONUM/DPID + USBAEP :: Bit -- USBAEP + _ :: Bits 4 -- (Reserved) + MPSIZ :: Bits 11 -- MPSIZ + + INT 0x3a8 - device endpoint-1 interrupt register + _ :: Bits 25 -- (Reserved) + B2BSTUP :: Bit -- B2BSTUP + _ :: Bit -- (Reserved) + OTEPDIS :: Bit -- OTEPDIS + STUP :: Bit -- STUP + _ :: Bit -- (Reserved) + EPDISD :: Bit -- EPDISD + XFRC :: Bit -- XFRC + + TSIZ 0x3b0 - device OUT endpoint-1 transfer size register + _ :: Bit -- (Reserved) + RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count + PKTCNT :: Bits 10 -- Packet count + XFRSIZ :: Bits 19 -- Transfer size + + OTG_FS_PWRCLK 0x50000e00 USB on the go full speed + + PCGCCTL 0x0 - OTG_FS power and clock gating control register + _ :: Bits 27 -- (Reserved) + PHYSUSP :: Bit -- PHY Suspended + _ :: Bits 2 -- (Reserved) + GATEHCLK :: Bit -- Gate HCLK + STPPCLK :: Bit -- Stop PHY clock + + DCMI 0x50050000 Digital camera interface + + CR 0x0 - control register 1 + _ :: Bits 17 -- (Reserved) + ENABLE :: Bit -- DCMI enable + _ :: Bits 2 -- (Reserved) + EDM :: Bits 2 -- Extended data mode + FCRC :: Bits 2 -- Frame capture rate control + VSPOL :: Bit -- Vertical synchronization polarity + HSPOL :: Bit -- Horizontal synchronization polarity + PCKPOL :: Bit -- Pixel clock polarity + ESS :: Bit -- Embedded synchronization select + JPEG :: Bit -- JPEG format + CROP :: Bit -- Crop feature + CM :: Bit -- Capture mode + CAPTURE :: Bit -- Capture enable + + SR 0x4 - status register + _ :: Bits 29 -- (Reserved) + FNE :: Bit -- FIFO not empty + VSYNC :: Bit -- VSYNC + HSYNC :: Bit -- HSYNC + + RIS 0x8 - raw interrupt status register + _ :: Bits 27 -- (Reserved) + LINE_RIS :: Bit -- Line raw interrupt status + VSYNC_RIS :: Bit -- VSYNC raw interrupt status + ERR_RIS :: Bit -- Synchronization error raw interrupt status + OVR_RIS :: Bit -- Overrun raw interrupt status + FRAME_RIS :: Bit -- Capture complete raw interrupt status + + IER 0xc - interrupt enable register + _ :: Bits 27 -- (Reserved) + LINE_IE :: Bit -- Line interrupt enable + VSYNC_IE :: Bit -- VSYNC interrupt enable + ERR_IE :: Bit -- Synchronization error interrupt enable + OVR_IE :: Bit -- Overrun interrupt enable + FRAME_IE :: Bit -- Capture complete interrupt enable + + MIS 0x10 - masked interrupt status register + _ :: Bits 27 -- (Reserved) + LINE_MIS :: Bit -- Line masked interrupt status + VSYNC_MIS :: Bit -- VSYNC masked interrupt status + ERR_MIS :: Bit -- Synchronization error masked interrupt status + OVR_MIS :: Bit -- Overrun masked interrupt status + FRAME_MIS :: Bit -- Capture complete masked interrupt status + + ICR 0x14 - interrupt clear register + _ :: Bits 27 -- (Reserved) + LINE_ISC :: Bit -- line interrupt status clear + VSYNC_ISC :: Bit -- Vertical synch interrupt status clear + ERR_ISC :: Bit -- Synchronization error interrupt status clear + OVR_ISC :: Bit -- Overrun interrupt status clear + FRAME_ISC :: Bit -- Capture complete interrupt status clear + + ESCR 0x18 - embedded synchronization code register + FEC :: Bits 8 -- Frame end delimiter code + LEC :: Bits 8 -- Line end delimiter code + LSC :: Bits 8 -- Line start delimiter code + FSC :: Bits 8 -- Frame start delimiter code + + ESUR 0x1c - embedded synchronization unmask register + FEU :: Bits 8 -- Frame end delimiter unmask + LEU :: Bits 8 -- Line end delimiter unmask + LSU :: Bits 8 -- Line start delimiter unmask + FSU :: Bits 8 -- Frame start delimiter unmask + + CWSTRT 0x20 - crop window start + _ :: Bits 3 -- (Reserved) + VST :: Bits 13 -- Vertical start line count + _ :: Bits 2 -- (Reserved) + HOFFCNT :: Bits 14 -- Horizontal offset count + + CWSIZE 0x24 - crop window size + _ :: Bits 2 -- (Reserved) + VLINE :: Bits 14 -- Vertical line count + _ :: Bits 2 -- (Reserved) + CAPCNT :: Bits 14 -- Capture count + + DR 0x28 - data register + Byte3 :: Bits 8 -- Data byte 3 + Byte2 :: Bits 8 -- Data byte 2 + Byte1 :: Bits 8 -- Data byte 1 + Byte0 :: Bits 8 -- Data byte 0 + + CRYP 0x50060000 Cryptographic processor + + CR 0x0 - control register + _ :: Bits 12 -- (Reserved) + ALGOMODE3 :: Bit -- ALGOMODE + _ :: Bit -- (Reserved) + GCM_CCMPH :: Bits 2 -- GCM_CCMPH + CRYPEN :: Bit -- Cryptographic processor enable + FFLUSH :: Bit -- FIFO flush + _ :: Bits 4 -- (Reserved) + KEYSIZE :: Bits 2 -- Key size selection (AES mode only) + DATATYPE :: Bits 2 -- Data type selection + ALGOMODE0 :: Bits 3 -- Algorithm mode + ALGODIR :: Bit -- Algorithm direction + _ :: Bits 2 -- (Reserved) + + SR 0x4 - status register + _ :: Bits 27 -- (Reserved) + BUSY :: Bit -- Busy bit + OFFU :: Bit -- Output FIFO full + OFNE :: Bit -- Output FIFO not empty + IFNF :: Bit -- Input FIFO not full + IFEM :: Bit -- Input FIFO empty + + DIN 0x8 - data input register + DATAIN :: Bits 32 -- Data input + + DOUT 0xc - data output register + DATAOUT :: Bits 32 -- Data output + + DMACR 0x10 - DMA control register + _ :: Bits 30 -- (Reserved) + DOEN :: Bit -- DMA output enable + DIEN :: Bit -- DMA input enable + + IMSCR 0x14 - interrupt mask set/clear register + _ :: Bits 30 -- (Reserved) + OUTIM :: Bit -- Output FIFO service interrupt mask + INIM :: Bit -- Input FIFO service interrupt mask + + RISR 0x18 - raw interrupt status register + _ :: Bits 30 -- (Reserved) + OUTRIS :: Bit -- Output FIFO service raw interrupt status + INRIS :: Bit -- Input FIFO service raw interrupt status + + MISR 0x1c - masked interrupt status register + _ :: Bits 30 -- (Reserved) + OUTMIS :: Bit -- Output FIFO service masked interrupt status + INMIS :: Bit -- Input FIFO service masked interrupt status + + KLR 0x20 - key registers + b2 :: Bits 32 -- b224 + + KRR 0x24 - key registers + b :: Bits 32 -- b192 + + KLR 0x28 - key registers + b2 :: Bits 32 -- b224 + + KRR 0x2c - key registers + b :: Bits 32 -- b192 + + KLR 0x30 - key registers + b2 :: Bits 32 -- b224 + + KRR 0x34 - key registers + b :: Bits 32 -- b192 + + KLR 0x38 - key registers + b2 :: Bits 32 -- b224 + + KRR 0x3c - key registers + b :: Bits 32 -- b192 + + IVLR 0x40 - initialization vector registers + IV :: Bits 32 -- IV31 + + IVRR 0x44 - initialization vector registers + IV :: Bits 32 -- IV63 + + IVLR 0x48 - initialization vector registers + IV :: Bits 32 -- IV31 + + IVRR 0x4c - initialization vector registers + IV :: Bits 32 -- IV63 + + CSGCMCCM0R 0x50 - context swap register + CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R + + CSGCMCCM1R 0x54 - context swap register + CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R + + CSGCMCCM2R 0x58 - context swap register + CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R + + CSGCMCCM3R 0x5c - context swap register + CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R + + CSGCMCCM4R 0x60 - context swap register + CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R + + CSGCMCCM5R 0x64 - context swap register + CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R + + CSGCMCCM6R 0x68 - context swap register + CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R + + CSGCMCCM7R 0x6c - context swap register + CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R + + CSGCM0R 0x70 - context swap register + CSGCMR :: Bits 32 -- CSGCM0R + + CSGCM1R 0x74 - context swap register + CSGCMR :: Bits 32 -- CSGCM0R + + CSGCM2R 0x78 - context swap register + CSGCMR :: Bits 32 -- CSGCM0R + + CSGCM3R 0x7c - context swap register + CSGCMR :: Bits 32 -- CSGCM0R + + CSGCM4R 0x80 - context swap register + CSGCMR :: Bits 32 -- CSGCM0R + + CSGCM5R 0x84 - context swap register + CSGCMR :: Bits 32 -- CSGCM0R + + CSGCM6R 0x88 - context swap register + CSGCMR :: Bits 32 -- CSGCM0R + + CSGCM7R 0x8c - context swap register + CSGCMR :: Bits 32 -- CSGCM0R + + HASH 0x50060400 Hash processor + + CR 0x0 - control register + _ :: Bits 13 -- (Reserved) + ALGO1 :: Bit -- ALGO + _ :: Bit -- (Reserved) + LKEY :: Bit -- Long key selection + _ :: Bits 2 -- (Reserved) + MDMAT :: Bit -- Multiple DMA Transfers + DINNE :: Bit -- DIN not empty + NBW :: Bits 4 -- Number of words already pushed + ALGO0 :: Bit -- Algorithm selection + MODE :: Bit -- Mode selection + DATATYPE :: Bits 2 -- Data type selection + DMAE :: Bit -- DMA enable + INIT :: Bit -- Initialize message digest calculation + _ :: Bits 2 -- (Reserved) + + DIN 0x4 - data input register + DATAIN :: Bits 32 -- Data input + + STR 0x8 - start register + _ :: Bits 23 -- (Reserved) + DCAL :: Bit -- Digest calculation + _ :: Bits 3 -- (Reserved) + NBLW :: Bits 5 -- Number of valid bits in the last word of the message + + HR0 0xc - digest registers + H :: Bits 32 -- H0 + + HR1 0x10 - digest registers + H :: Bits 32 -- H0 + + HR2 0x14 - digest registers + H :: Bits 32 -- H0 + + HR3 0x18 - digest registers + H :: Bits 32 -- H0 + + HR4 0x1c - digest registers + H :: Bits 32 -- H0 + + IMR 0x20 - interrupt enable register + _ :: Bits 30 -- (Reserved) + DCIE :: Bit -- Digest calculation completion interrupt enable + DINIE :: Bit -- Data input interrupt enable + + SR 0x24 - status register + _ :: Bits 28 -- (Reserved) + BUSY :: Bit -- Busy bit + DMAS :: Bit -- DMA Status + DCIS :: Bit -- Digest calculation completion interrupt status + DINIS :: Bit -- Data input interrupt status + + CSR0 0xf8 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR1 0xfc - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR2 0x100 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR3 0x104 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR4 0x108 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR5 0x10c - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR6 0x110 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR7 0x114 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR8 0x118 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR9 0x11c - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR10 0x120 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR11 0x124 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR12 0x128 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR13 0x12c - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR14 0x130 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR15 0x134 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR16 0x138 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR17 0x13c - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR18 0x140 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR19 0x144 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR20 0x148 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR21 0x14c - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR22 0x150 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR23 0x154 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR24 0x158 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR25 0x15c - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR26 0x160 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR27 0x164 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR28 0x168 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR29 0x16c - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR30 0x170 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR31 0x174 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR32 0x178 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR33 0x17c - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR34 0x180 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR35 0x184 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR36 0x188 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR37 0x18c - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR38 0x190 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR39 0x194 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR40 0x198 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR41 0x19c - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR42 0x1a0 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR43 0x1a4 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR44 0x1a8 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR45 0x1ac - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR46 0x1b0 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR47 0x1b4 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR48 0x1b8 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR49 0x1bc - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR50 0x1c0 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR51 0x1c4 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR52 0x1c8 - context swap registers + CSR :: Bits 32 -- CSR0 + + CSR53 0x1cc - context swap registers + CSR :: Bits 32 -- CSR0 + + HASH_HR0 0x310 - HASH digest register 0 + H :: Bits 32 -- H0 + + HASH_HR1 0x314 - HASH digest register 1 + H :: Bits 32 -- H0 + + HASH_HR2 0x318 - HASH digest register 2 + H :: Bits 32 -- H0 + + HASH_HR3 0x31c - HASH digest register 3 + H :: Bits 32 -- H0 + + HASH_HR4 0x320 - HASH digest register 4 + H :: Bits 32 -- H0 + + HASH_HR5 0x324 - HASH digest register 5 + H :: Bits 32 -- H0 + + HASH_HR6 0x328 - HASH digest register 6 + H :: Bits 32 -- H0 + + HASH_HR7 0x32c - HASH digest register 7 + H :: Bits 32 -- H0 + + RNG 0x50060800 Random number generator + + CR 0x0 - control register + _ :: Bits 28 -- (Reserved) + IE :: Bit -- Interrupt enable + RNGEN :: Bit -- Random number generator enable + _ :: Bits 2 -- (Reserved) + + SR 0x4 - status register + _ :: Bits 25 -- (Reserved) + SEIS :: Bit -- Seed error interrupt status + CEIS :: Bit -- Clock error interrupt status + _ :: Bits 2 -- (Reserved) + SECS :: Bit -- Seed error current status + CECS :: Bit -- Clock error current status + DRDY :: Bit -- Data ready + + DR 0x8 - data register + RNDATA :: Bits 32 -- Random data + + FSMC 0xa0000000 Flexible static memory controller + + BCR1 0x0 - SRAM/NOR-Flash chip-select control register 1 + _ :: Bits 12 -- (Reserved) + CBURSTRW :: Bit -- CBURSTRW + CPSIZE :: Bits 3 -- CRAM page size + ASYNCWAIT :: Bit -- ASYNCWAIT + EXTMOD :: Bit -- EXTMOD + WAITEN :: Bit -- WAITEN + WREN :: Bit -- WREN + WAITCFG :: Bit -- WAITCFG + WRAPMOD :: Bit -- WRAPMOD + WAITPOL :: Bit -- WAITPOL + BURSTEN :: Bit -- BURSTEN + _ :: Bit -- (Reserved) + FACCEN :: Bit -- FACCEN + MWID :: Bits 2 -- MWID + MTYP :: Bits 2 -- MTYP + MUXEN :: Bit -- MUXEN + MBKEN :: Bit -- MBKEN + + BTR1 0x4 - SRAM/NOR-Flash chip-select timing register 1 + _ :: Bits 2 -- (Reserved) + ACCMOD :: Bits 2 -- ACCMOD + DATLAT :: Bits 4 -- DATLAT + CLKDIV :: Bits 4 -- CLKDIV + BUSTURN :: Bits 4 -- BUSTURN + DATAST :: Bits 8 -- DATAST + ADDHLD :: Bits 4 -- ADDHLD + ADDSET :: Bits 4 -- ADDSET + + BCR2 0x8 - SRAM/NOR-Flash chip-select control register 2 + _ :: Bits 12 -- (Reserved) + CBURSTRW :: Bit -- CBURSTRW + CPSIZE :: Bits 3 -- CRAM page size + ASYNCWAIT :: Bit -- ASYNCWAIT + EXTMOD :: Bit -- EXTMOD + WAITEN :: Bit -- WAITEN + WREN :: Bit -- WREN + WAITCFG :: Bit -- WAITCFG + WRAPMOD :: Bit -- WRAPMOD + WAITPOL :: Bit -- WAITPOL + BURSTEN :: Bit -- BURSTEN + _ :: Bit -- (Reserved) + FACCEN :: Bit -- FACCEN + MWID :: Bits 2 -- MWID + MTYP :: Bits 2 -- MTYP + MUXEN :: Bit -- MUXEN + MBKEN :: Bit -- MBKEN + + BTR2 0xc - SRAM/NOR-Flash chip-select timing register 1 + _ :: Bits 2 -- (Reserved) + ACCMOD :: Bits 2 -- ACCMOD + DATLAT :: Bits 4 -- DATLAT + CLKDIV :: Bits 4 -- CLKDIV + BUSTURN :: Bits 4 -- BUSTURN + DATAST :: Bits 8 -- DATAST + ADDHLD :: Bits 4 -- ADDHLD + ADDSET :: Bits 4 -- ADDSET + + BCR3 0x10 - SRAM/NOR-Flash chip-select control register 2 + _ :: Bits 12 -- (Reserved) + CBURSTRW :: Bit -- CBURSTRW + CPSIZE :: Bits 3 -- CRAM page size + ASYNCWAIT :: Bit -- ASYNCWAIT + EXTMOD :: Bit -- EXTMOD + WAITEN :: Bit -- WAITEN + WREN :: Bit -- WREN + WAITCFG :: Bit -- WAITCFG + WRAPMOD :: Bit -- WRAPMOD + WAITPOL :: Bit -- WAITPOL + BURSTEN :: Bit -- BURSTEN + _ :: Bit -- (Reserved) + FACCEN :: Bit -- FACCEN + MWID :: Bits 2 -- MWID + MTYP :: Bits 2 -- MTYP + MUXEN :: Bit -- MUXEN + MBKEN :: Bit -- MBKEN + + BTR3 0x14 - SRAM/NOR-Flash chip-select timing register 1 + _ :: Bits 2 -- (Reserved) + ACCMOD :: Bits 2 -- ACCMOD + DATLAT :: Bits 4 -- DATLAT + CLKDIV :: Bits 4 -- CLKDIV + BUSTURN :: Bits 4 -- BUSTURN + DATAST :: Bits 8 -- DATAST + ADDHLD :: Bits 4 -- ADDHLD + ADDSET :: Bits 4 -- ADDSET + + BCR4 0x18 - SRAM/NOR-Flash chip-select control register 2 + _ :: Bits 12 -- (Reserved) + CBURSTRW :: Bit -- CBURSTRW + CPSIZE :: Bits 3 -- CRAM page size + ASYNCWAIT :: Bit -- ASYNCWAIT + EXTMOD :: Bit -- EXTMOD + WAITEN :: Bit -- WAITEN + WREN :: Bit -- WREN + WAITCFG :: Bit -- WAITCFG + WRAPMOD :: Bit -- WRAPMOD + WAITPOL :: Bit -- WAITPOL + BURSTEN :: Bit -- BURSTEN + _ :: Bit -- (Reserved) + FACCEN :: Bit -- FACCEN + MWID :: Bits 2 -- MWID + MTYP :: Bits 2 -- MTYP + MUXEN :: Bit -- MUXEN + MBKEN :: Bit -- MBKEN + + BTR4 0x1c - SRAM/NOR-Flash chip-select timing register 1 + _ :: Bits 2 -- (Reserved) + ACCMOD :: Bits 2 -- ACCMOD + DATLAT :: Bits 4 -- DATLAT + CLKDIV :: Bits 4 -- CLKDIV + BUSTURN :: Bits 4 -- BUSTURN + DATAST :: Bits 8 -- DATAST + ADDHLD :: Bits 4 -- ADDHLD + ADDSET :: Bits 4 -- ADDSET + + PCR2 0x60 - PC Card/NAND Flash control register 2 + _ :: Bits 12 -- (Reserved) + ECCPS :: Bits 3 -- ECCPS + TAR :: Bits 4 -- TAR + TCLR :: Bits 4 -- TCLR + _ :: Bits 2 -- (Reserved) + ECCEN :: Bit -- ECCEN + PWID :: Bits 2 -- PWID + PTYP :: Bit -- PTYP + PBKEN :: Bit -- PBKEN + PWAITEN :: Bit -- PWAITEN + _ :: Bit -- (Reserved) + + SR2 0x64 - FIFO status and interrupt register 2 + _ :: Bits 25 -- (Reserved) + FEMPT :: Bit -- FEMPT + IFEN :: Bit -- IFEN + ILEN :: Bit -- ILEN + IREN :: Bit -- IREN + IFS :: Bit -- IFS + ILS :: Bit -- ILS + IRS :: Bit -- IRS + + PMEM2 0x68 - Common memory space timing register 2 + MEMHIZ :: Bits 8 -- MEMHIZx + MEMHOLD :: Bits 8 -- MEMHOLDx + MEMWAIT :: Bits 8 -- MEMWAITx + MEMSET :: Bits 8 -- MEMSETx + + PATT2 0x6c - Attribute memory space timing register 2 + ATTHIZ :: Bits 8 -- ATTHIZx + ATTHOLD :: Bits 8 -- ATTHOLDx + ATTWAIT :: Bits 8 -- ATTWAITx + ATTSET :: Bits 8 -- ATTSETx + + ECCR2 0x74 - ECC result register 2 + ECC :: Bits 32 -- ECCx + + PCR3 0x80 - PC Card/NAND Flash control register 2 + _ :: Bits 12 -- (Reserved) + ECCPS :: Bits 3 -- ECCPS + TAR :: Bits 4 -- TAR + TCLR :: Bits 4 -- TCLR + _ :: Bits 2 -- (Reserved) + ECCEN :: Bit -- ECCEN + PWID :: Bits 2 -- PWID + PTYP :: Bit -- PTYP + PBKEN :: Bit -- PBKEN + PWAITEN :: Bit -- PWAITEN + _ :: Bit -- (Reserved) + + SR3 0x84 - FIFO status and interrupt register 2 + _ :: Bits 25 -- (Reserved) + FEMPT :: Bit -- FEMPT + IFEN :: Bit -- IFEN + ILEN :: Bit -- ILEN + IREN :: Bit -- IREN + IFS :: Bit -- IFS + ILS :: Bit -- ILS + IRS :: Bit -- IRS + + PMEM3 0x88 - Common memory space timing register 3 + MEMHIZ :: Bits 8 -- MEMHIZx + MEMHOLD :: Bits 8 -- MEMHOLDx + MEMWAIT :: Bits 8 -- MEMWAITx + MEMSET :: Bits 8 -- MEMSETx + + PATT3 0x8c - Attribute memory space timing register 3 + ATTHIZ :: Bits 8 -- ATTHIZx + ATTHOLD :: Bits 8 -- ATTHOLDx + ATTWAIT :: Bits 8 -- ATTWAITx + ATTSET :: Bits 8 -- ATTSETx + + ECCR3 0x94 - ECC result register 3 + ECC :: Bits 32 -- ECCx + + PCR4 0xa0 - PC Card/NAND Flash control register 2 + _ :: Bits 12 -- (Reserved) + ECCPS :: Bits 3 -- ECCPS + TAR :: Bits 4 -- TAR + TCLR :: Bits 4 -- TCLR + _ :: Bits 2 -- (Reserved) + ECCEN :: Bit -- ECCEN + PWID :: Bits 2 -- PWID + PTYP :: Bit -- PTYP + PBKEN :: Bit -- PBKEN + PWAITEN :: Bit -- PWAITEN + _ :: Bit -- (Reserved) + + SR4 0xa4 - FIFO status and interrupt register 2 + _ :: Bits 25 -- (Reserved) + FEMPT :: Bit -- FEMPT + IFEN :: Bit -- IFEN + ILEN :: Bit -- ILEN + IREN :: Bit -- IREN + IFS :: Bit -- IFS + ILS :: Bit -- ILS + IRS :: Bit -- IRS + + PMEM4 0xa8 - Common memory space timing register 4 + MEMHIZ :: Bits 8 -- MEMHIZx + MEMHOLD :: Bits 8 -- MEMHOLDx + MEMWAIT :: Bits 8 -- MEMWAITx + MEMSET :: Bits 8 -- MEMSETx + + PATT4 0xac - Attribute memory space timing register 4 + ATTHIZ :: Bits 8 -- ATTHIZx + ATTHOLD :: Bits 8 -- ATTHOLDx + ATTWAIT :: Bits 8 -- ATTWAITx + ATTSET :: Bits 8 -- ATTSETx + + PIO4 0xb0 - I/O space timing register 4 + IOHIZx :: Bits 8 -- IOHIZx + IOHOLDx :: Bits 8 -- IOHOLDx + IOWAITx :: Bits 8 -- IOWAITx + IOSETx :: Bits 8 -- IOSETx + + BWTR1 0x104 - SRAM/NOR-Flash write timing registers 1 + _ :: Bits 2 -- (Reserved) + ACCMOD :: Bits 2 -- ACCMOD + DATLAT :: Bits 4 -- DATLAT + CLKDIV :: Bits 4 -- CLKDIV + BUSTURN :: Bits 4 -- Bus turnaround phase duration + DATAST :: Bits 8 -- DATAST + ADDHLD :: Bits 4 -- ADDHLD + ADDSET :: Bits 4 -- ADDSET + + BWTR2 0x10c - SRAM/NOR-Flash write timing registers 1 + _ :: Bits 2 -- (Reserved) + ACCMOD :: Bits 2 -- ACCMOD + DATLAT :: Bits 4 -- DATLAT + CLKDIV :: Bits 4 -- CLKDIV + BUSTURN :: Bits 4 -- Bus turnaround phase duration + DATAST :: Bits 8 -- DATAST + ADDHLD :: Bits 4 -- ADDHLD + ADDSET :: Bits 4 -- ADDSET + + BWTR3 0x114 - SRAM/NOR-Flash write timing registers 1 + _ :: Bits 2 -- (Reserved) + ACCMOD :: Bits 2 -- ACCMOD + DATLAT :: Bits 4 -- DATLAT + CLKDIV :: Bits 4 -- CLKDIV + BUSTURN :: Bits 4 -- Bus turnaround phase duration + DATAST :: Bits 8 -- DATAST + ADDHLD :: Bits 4 -- ADDHLD + ADDSET :: Bits 4 -- ADDSET + + BWTR4 0x11c - SRAM/NOR-Flash write timing registers 1 + _ :: Bits 2 -- (Reserved) + ACCMOD :: Bits 2 -- ACCMOD + DATLAT :: Bits 4 -- DATLAT + CLKDIV :: Bits 4 -- CLKDIV + BUSTURN :: Bits 4 -- Bus turnaround phase duration + DATAST :: Bits 8 -- DATAST + ADDHLD :: Bits 4 -- ADDHLD + ADDSET :: Bits 4 -- ADDSET + + SCB_ACTRL 0xe000e008 System control block ACTLR + + ACTRL 0x0 - Auxiliary control register + _ :: Bits 22 -- (Reserved) + DISOOFP :: Bit -- DISOOFP + DISFPCA :: Bit -- DISFPCA + _ :: Bits 5 -- (Reserved) + DISFOLD :: Bit -- DISFOLD + DISDEFWBUF :: Bit -- DISDEFWBUF + DISMCYCINT :: Bit -- DISMCYCINT + + STK 0xe000e010 SysTick timer + + CTRL 0x0 - SysTick control and status register + _ :: Bits 15 -- (Reserved) + COUNTFLAG :: Bit -- COUNTFLAG + _ :: Bits 13 -- (Reserved) + CLKSOURCE :: Bit -- Clock source selection + TICKINT :: Bit -- SysTick exception request enable + ENABLE :: Bit -- Counter enable + + LOAD 0x4 - SysTick reload value register + _ :: Bits 8 -- (Reserved) + RELOAD :: Bits 24 -- RELOAD value + + VAL 0x8 - SysTick current value register + _ :: Bits 8 -- (Reserved) + CURRENT :: Bits 24 -- Current counter value + + CALIB 0xc - SysTick calibration value register + NOREF :: Bit -- NOREF flag. Reads as zero + SKEW :: Bit -- SKEW flag: Indicates whether the TENMS value is exact + _ :: Bits 6 -- (Reserved) + TENMS :: Bits 24 -- Calibration value + + NVIC 0xe000e100 Nested Vectored Interrupt Controller + + ISER0 0x0 - Interrupt Set-Enable Register + SETENA :: Bits 32 -- SETENA + + ISER1 0x4 - Interrupt Set-Enable Register + SETENA :: Bits 32 -- SETENA + + ISER2 0x8 - Interrupt Set-Enable Register + SETENA :: Bits 32 -- SETENA + + ICER0 0x80 - Interrupt Clear-Enable Register + CLRENA :: Bits 32 -- CLRENA + + ICER1 0x84 - Interrupt Clear-Enable Register + CLRENA :: Bits 32 -- CLRENA + + ICER2 0x88 - Interrupt Clear-Enable Register + CLRENA :: Bits 32 -- CLRENA + + ISPR0 0x100 - Interrupt Set-Pending Register + SETPEND :: Bits 32 -- SETPEND + + ISPR1 0x104 - Interrupt Set-Pending Register + SETPEND :: Bits 32 -- SETPEND + + ISPR2 0x108 - Interrupt Set-Pending Register + SETPEND :: Bits 32 -- SETPEND + + ICPR0 0x180 - Interrupt Clear-Pending Register + CLRPEND :: Bits 32 -- CLRPEND + + ICPR1 0x184 - Interrupt Clear-Pending Register + CLRPEND :: Bits 32 -- CLRPEND + + ICPR2 0x188 - Interrupt Clear-Pending Register + CLRPEND :: Bits 32 -- CLRPEND + + IABR0 0x200 - Interrupt Active Bit Register + ACTIVE :: Bits 32 -- ACTIVE + + IABR1 0x204 - Interrupt Active Bit Register + ACTIVE :: Bits 32 -- ACTIVE + + IABR2 0x208 - Interrupt Active Bit Register + ACTIVE :: Bits 32 -- ACTIVE + + IPR0 0x300 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR1 0x304 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR2 0x308 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR3 0x30c - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR4 0x310 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR5 0x314 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR6 0x318 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR7 0x31c - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR8 0x320 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR9 0x324 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR10 0x328 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR11 0x32c - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR12 0x330 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR13 0x334 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR14 0x338 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR15 0x33c - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR16 0x340 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR17 0x344 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR18 0x348 - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + IPR19 0x34c - Interrupt Priority Register + IPR_N3 :: Bits 8 -- IPR_N3 + IPR_N2 :: Bits 8 -- IPR_N2 + IPR_N1 :: Bits 8 -- IPR_N1 + IPR_N0 :: Bits 8 -- IPR_N0 + + SCB 0xe000ed00 System control block + + CPUID 0x0 - CPUID base register + Implementer :: Bits 8 -- Implementer code + Variant :: Bits 4 -- Variant number + Constant :: Bits 4 -- Reads as 0xF + PartNo :: Bits 12 -- Part number of the processor + Revision :: Bits 4 -- Revision number + + ICSR 0x4 - Interrupt control and state register + NMIPENDSET :: Bit -- NMI set-pending bit. + _ :: Bits 2 -- (Reserved) + PENDSVSET :: Bit -- PendSV set-pending bit + PENDSVCLR :: Bit -- PendSV clear-pending bit + PENDSTSET :: Bit -- SysTick exception set-pending bit + PENDSTCLR :: Bit -- SysTick exception clear-pending bit + _ :: Bits 2 -- (Reserved) + ISRPENDING :: Bit -- Interrupt pending flag + _ :: Bits 3 -- (Reserved) + VECTPENDING :: Bits 7 -- Pending vector + RETTOBASE :: Bit -- Return to base level + _ :: Bits 2 -- (Reserved) + VECTACTIVE :: Bits 9 -- Active vector + + VTOR 0x8 - Vector table offset register + _ :: Bits 2 -- (Reserved) + TBLOFF :: Bits 21 -- Vector table base offset field + _ :: Bits 9 -- (Reserved) + + AIRCR 0xc - Application interrupt and reset control register + VECTKEYSTAT :: Bits 16 -- Register key + ENDIANESS :: Bit -- ENDIANESS + _ :: Bits 4 -- (Reserved) + PRIGROUP :: Bits 3 -- PRIGROUP + _ :: Bits 5 -- (Reserved) + SYSRESETREQ :: Bit -- SYSRESETREQ + VECTCLRACTIVE :: Bit -- VECTCLRACTIVE + VECTRESET :: Bit -- VECTRESET + + SCR 0x10 - System control register + _ :: Bits 27 -- (Reserved) + SEVEONPEND :: Bit -- Send Event on Pending bit + _ :: Bit -- (Reserved) + SLEEPDEEP :: Bit -- SLEEPDEEP + SLEEPONEXIT :: Bit -- SLEEPONEXIT + _ :: Bit -- (Reserved) + + CCR 0x14 - Configuration and control register + _ :: Bits 22 -- (Reserved) + STKALIGN :: Bit -- STKALIGN + BFHFNMIGN :: Bit -- BFHFNMIGN + _ :: Bits 3 -- (Reserved) + DIV_0_TRP :: Bit -- DIV_0_TRP + UNALIGN__TRP :: Bit -- UNALIGN_ TRP + _ :: Bit -- (Reserved) + USERSETMPEND :: Bit -- USERSETMPEND + NONBASETHRDENA :: Bit -- Configures how the processor enters Thread mode + + SHPR1 0x18 - System handler priority registers + _ :: Bits 8 -- (Reserved) + PRI_6 :: Bits 8 -- Priority of system handler 6 + PRI_5 :: Bits 8 -- Priority of system handler 5 + PRI_4 :: Bits 8 -- Priority of system handler 4 + + SHPR2 0x1c - System handler priority registers + PRI_11 :: Bits 8 -- Priority of system handler 11 + _ :: Bits 24 -- (Reserved) + + SHPR3 0x20 - System handler priority registers + PRI_15 :: Bits 8 -- Priority of system handler 15 + PRI_14 :: Bits 8 -- Priority of system handler 14 + _ :: Bits 16 -- (Reserved) + + SHCRS 0x24 - System handler control and state register + _ :: Bits 13 -- (Reserved) + USGFAULTENA :: Bit -- Usage fault enable bit + BUSFAULTENA :: Bit -- Bus fault enable bit + MEMFAULTENA :: Bit -- Memory management fault enable bit + SVCALLPENDED :: Bit -- SVC call pending bit + BUSFAULTPENDED :: Bit -- Bus fault exception pending bit + MEMFAULTPENDED :: Bit -- Memory management fault exception pending bit + USGFAULTPENDED :: Bit -- Usage fault exception pending bit + SYSTICKACT :: Bit -- SysTick exception active bit + PENDSVACT :: Bit -- PendSV exception active bit + _ :: Bit -- (Reserved) + MONITORACT :: Bit -- Debug monitor active bit + SVCALLACT :: Bit -- SVC call active bit + _ :: Bits 3 -- (Reserved) + USGFAULTACT :: Bit -- Usage fault exception active bit + _ :: Bit -- (Reserved) + BUSFAULTACT :: Bit -- Bus fault exception active bit + MEMFAULTACT :: Bit -- Memory management fault exception active bit + + CFSR_UFSR_BFSR_MMFSR 0x28 - Configurable fault status register + _ :: Bits 6 -- (Reserved) + DIVBYZERO :: Bit -- Divide by zero usage fault + UNALIGNED :: Bit -- Unaligned access usage fault + _ :: Bits 4 -- (Reserved) + NOCP :: Bit -- No coprocessor usage fault. + INVPC :: Bit -- Invalid PC load usage fault + INVSTATE :: Bit -- Invalid state usage fault + UNDEFINSTR :: Bit -- Undefined instruction usage fault + BFARVALID :: Bit -- Bus Fault Address Register (BFAR) valid flag + _ :: Bit -- (Reserved) + LSPERR :: Bit -- Bus fault on floating-point lazy state preservation + STKERR :: Bit -- Bus fault on stacking for exception entry + UNSTKERR :: Bit -- Bus fault on unstacking for a return from exception + IMPRECISERR :: Bit -- Imprecise data bus error + PRECISERR :: Bit -- Precise data bus error + IBUSERR :: Bit -- Instruction bus error + MMARVALID :: Bit -- Memory Management Fault Address Register (MMAR) valid flag + _ :: Bit -- (Reserved) + MLSPERR :: Bit -- MLSPERR + MSTKERR :: Bit -- Memory manager fault on stacking for exception entry. + MUNSTKERR :: Bit -- Memory manager fault on unstacking for a return from exception + _ :: Bit -- (Reserved) + IACCVIOL :: Bit -- Instruction access violation flag + _ :: Bit -- (Reserved) + + HFSR 0x2c - Hard fault status register + DEBUG_VT :: Bit -- Reserved for Debug use + FORCED :: Bit -- Forced hard fault + _ :: Bits 28 -- (Reserved) + VECTTBL :: Bit -- Vector table hard fault + _ :: Bit -- (Reserved) + + MMFAR 0x34 - Memory management fault address register + MMFAR :: Bits 32 -- Memory management fault address + + BFAR 0x38 - Bus fault address register + BFAR :: Bits 32 -- Bus fault address + + AFSR 0x3c - Auxiliary fault status register + IMPDEF :: Bits 32 -- Implementation defined + + FPU_CPACR 0xe000ed88 Floating point unit CPACR + + CPACR 0x0 - Coprocessor access control register + _ :: Bits 8 -- (Reserved) + CP :: Bits 4 -- CP + _ :: Bits 20 -- (Reserved) + + MPU 0xe000ed90 Memory protection unit + + TYPER 0x0 - MPU type register + _ :: Bits 8 -- (Reserved) + IREGION :: Bits 8 -- Number of MPU instruction regions + DREGION :: Bits 8 -- Number of MPU data regions + _ :: Bits 7 -- (Reserved) + SEPARATE :: Bit -- Separate flag + + CTRL 0x4 - MPU control register + _ :: Bits 29 -- (Reserved) + PRIVDEFENA :: Bit -- Enable priviliged software access to default memory map + HFNMIENA :: Bit -- Enables the operation of MPU during hard fault + ENABLE :: Bit -- Enables the MPU + + RNR 0x8 - MPU region number register + _ :: Bits 24 -- (Reserved) + REGION :: Bits 8 -- MPU region + + RBAR 0xc - MPU region base address register + ADDR :: Bits 27 -- Region base address field + VALID :: Bit -- MPU region number valid + REGION :: Bits 4 -- MPU region field + + RASR 0x10 - MPU region attribute and size register + _ :: Bits 3 -- (Reserved) + XN :: Bit -- Instruction access disable bit + _ :: Bit -- (Reserved) + AP :: Bits 3 -- Access permission + _ :: Bits 2 -- (Reserved) + TEX :: Bits 3 -- memory attribute + S :: Bit -- Shareable memory attribute + C :: Bit -- memory attribute + B :: Bit -- memory attribute + SRD :: Bits 8 -- Subregion disable bits + _ :: Bits 2 -- (Reserved) + SIZE :: Bits 5 -- Size of the MPU protection region + ENABLE :: Bit -- Region enable bit. + + NVIC_STIR 0xe000ef00 Nested vectored interrupt controller + + STIR 0x0 - Software trigger interrupt register + _ :: Bits 23 -- (Reserved) + INTID :: Bits 9 -- Software generated interrupt ID + + FPU 0xe000ef34 Floting point unit + + FPCCR 0x0 - Floating-point context control register + ASPEN :: Bit -- ASPEN + LSPEN :: Bit -- LSPEN + _ :: Bits 21 -- (Reserved) + MONRDY :: Bit -- MONRDY + _ :: Bit -- (Reserved) + BFRDY :: Bit -- BFRDY + MMRDY :: Bit -- MMRDY + HFRDY :: Bit -- HFRDY + THREAD :: Bit -- THREAD + _ :: Bit -- (Reserved) + USER :: Bit -- USER + LSPACT :: Bit -- LSPACT + + FPCAR 0x4 - Floating-point context address register + ADDRESS :: Bits 29 -- Location of unpopulated floating-point + _ :: Bits 3 -- (Reserved) + + FPSCR 0x8 - Floating-point status control register + N :: Bit -- Negative condition code flag + Z :: Bit -- Zero condition code flag + C :: Bit -- Carry condition code flag + V :: Bit -- Overflow condition code flag + _ :: Bit -- (Reserved) + AHP :: Bit -- Alternative half-precision control bit + DN :: Bit -- Default NaN mode control bit + FZ :: Bit -- Flush-to-zero mode control bit: + RMode :: Bits 2 -- Rounding Mode control field + _ :: Bits 14 -- (Reserved) + IDC :: Bit -- Input denormal cumulative exception bit. + _ :: Bits 2 -- (Reserved) + IXC :: Bit -- Inexact cumulative exception bit + UFC :: Bit -- Underflow cumulative exception bit + OFC :: Bit -- Overflow cumulative exception bit + DZC :: Bit -- Division by zero cumulative exception bit. + IOC :: Bit -- Invalid operation cumulative exception bit + + DBGMCU 0xe0042000 Debug support + + IDCODE 0x0 - IDCODE + REV_ID :: Bits 16 -- REV_ID + _ :: Bits 4 -- (Reserved) + DEV_ID :: Bits 12 -- DEV_ID + + CR 0x4 - Control Register + _ :: Bits 11 -- (Reserved) + DBG_TIM7_STOP :: Bit -- DBG_TIM7_STOP + DBG_TIM6_STOP :: Bit -- DBG_TIM6_STOP + DBG_TIM5_STOP :: Bit -- DBG_TIM5_STOP + DBG_TIM8_STOP :: Bit -- DBG_TIM8_STOP + DBG_I2C2_SMBUS_TIMEOUT :: Bit -- DBG_I2C2_SMBUS_TIMEOUT + _ :: Bits 8 -- (Reserved) + TRACE_MODE :: Bits 2 -- TRACE_MODE + TRACE_IOEN :: Bit -- TRACE_IOEN + _ :: Bits 2 -- (Reserved) + DBG_STANDBY :: Bit -- DBG_STANDBY + DBG_STOP :: Bit -- DBG_STOP + DBG_SLEEP :: Bit -- DBG_SLEEP + + APB1_FZ 0x8 - Debug MCU APB1 Freeze registe + _ :: Bits 5 -- (Reserved) + DBG_CAN2_STOP :: Bit -- DBG_CAN2_STOP + DBG_CAN1_STOP :: Bit -- DBG_CAN1_STOP + _ :: Bit -- (Reserved) + DBG_J2C3SMBUS_TIMEOUT :: Bit -- DBG_J2C3SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT :: Bit -- DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT :: Bit -- DBG_J2C1_SMBUS_TIMEOUT + _ :: Bits 8 -- (Reserved) + DBG_IWDG_STOP :: Bit -- DBG_IWDEG_STOP + DBG_WWDG_STOP :: Bit -- DBG_WWDG_STOP + _ :: Bits 2 -- (Reserved) + DBG_TIM14_STOP :: Bit -- DBG_TIM14_STOP + DBG_TIM13_STOP :: Bit -- DBG_TIM13_STOP + DBG_TIM12_STOP :: Bit -- DBG_TIM12_STOP + DBG_TIM7_STOP :: Bit -- DBG_TIM7_STOP + DBG_TIM6_STOP :: Bit -- DBG_TIM6_STOP + DBG_TIM5_STOP :: Bit -- DBG_TIM5_STOP + DBG_TIM4_STOP :: Bit -- DBG_TIM4_STOP + DBG_TIM3_STOP :: Bit -- DBG_TIM3 _STOP + DBG_TIM2_STOP :: Bit -- DBG_TIM2_STOP + + APB2_FZ 0xc - Debug MCU APB2 Freeze registe + _ :: Bits 13 -- (Reserved) + DBG_TIM11_STOP :: Bit -- TIM11 counter stopped when core is halted + DBG_TIM10_STOP :: Bit -- TIM10 counter stopped when core is halted + DBG_TIM9_STOP :: Bit -- TIM9 counter stopped when core is halted + _ :: Bits 14 -- (Reserved) + DBG_TIM8_STOP :: Bit -- TIM8 counter stopped when core is halted + DBG_TIM1_STOP :: Bit -- TIM1 counter stopped when core is halted diff --git a/CHANGELOG.md b/CHANGELOG.md new file mode 100644 --- /dev/null +++ b/CHANGELOG.md @@ -0,0 +1,10 @@ +# Version [0.1.0.0](https://github.com/DistRap/data-svd/compare/de41e81...0.1.0.0) (2023-12-24) + +* Initial release + +--- + +`data-svd` uses [PVP Versioning][1]. + +[1]: https://pvp.haskell.org + diff --git a/LICENSE b/LICENSE new file mode 100644 --- /dev/null +++ b/LICENSE @@ -0,0 +1,30 @@ +Copyright sorki (c) 2023 + +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + * Neither the name of Author name here nor the names of other + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/README.md b/README.md new file mode 100644 --- /dev/null +++ b/README.md @@ -0,0 +1,12 @@ +# data-svd + +[![GitHub Workflow Status](https://img.shields.io/github/actions/workflow/status/DistRap/data-svd/ci.yaml?branch=main)](https://github.com/DistRap/data-svd/actions/workflows/ci.yaml) +[![Hackage version](https://img.shields.io/hackage/v/data-svd.svg?color=success)](https://hackage.haskell.org/package/data-svd) +[![Dependencies](https://img.shields.io/hackage-deps/v/data-svd?label=Dependencies)](https://packdeps.haskellers.com/feed?needle=data-svd) + +SVD (System view description) file handling. + +Parsing, pretty printing, diffing and various utilities. + +Mostly targets STM32 SVD files but other ones should work just as well, file +a PR/Issue if not. diff --git a/app/Main.hs b/app/Main.hs new file mode 100644 --- /dev/null +++ b/app/Main.hs @@ -0,0 +1,14 @@ +{-# LANGUAGE LambdaCase #-} +module Main where + +import qualified Data.SVD +import qualified System.Environment + +main :: IO () +main = System.Environment.getArgs >>= \case + [filename] -> do + Data.SVD.parseSVD filename >>= \case + Left e -> error $ show e + Right p -> + putStrLn $ Data.SVD.displayDevice p + _ -> error "No input svd file" diff --git a/data-svd.cabal b/data-svd.cabal new file mode 100644 --- /dev/null +++ b/data-svd.cabal @@ -0,0 +1,84 @@ +cabal-version: 2.2 +name: data-svd +version: 0.1.0.0 +synopsis: SVD (System view description) file handling +description: Parse, print, diff SVD files +homepage: https://github.com/DistRap/data-svd +license: BSD-3-Clause +license-file: LICENSE +author: sorki +maintainer: srk@48.io +copyright: 2023 sorki +category: Embedded +build-type: Simple + +extra-source-files: + LICENSE + README.md + .golden/stm32f405/golden + .golden/stm32f405-isrs/golden + .golden/stm32f405-memmap/golden + test/samples/stm32f405.svd + +extra-doc-files: + CHANGELOG.md + +library + ghc-options: -Wall + hs-source-dirs: src + exposed-modules: Data.Bits.Pretty + Data.SVD + Data.SVD.Diff + Data.SVD.Dim + Data.SVD.IO + Data.SVD.Lens + Data.SVD.Parse + Data.SVD.Pretty + Data.SVD.Types + Data.SVD.Util + build-depends: base >= 4.7 && < 5 + , bytestring + , containers + , cereal + , data-default-class + , Diff + , directory + , hashable + , hxt + , hxt-xpath + , lens + , prettyprinter + , prettyprinter-ansi-terminal + , safe + , text + default-language: Haskell2010 + +executable pretty-svd + hs-source-dirs: app + main-is: Main.hs + ghc-options: -threaded -rtsopts -with-rtsopts=-N + build-depends: base + , data-svd + default-language: Haskell2010 + +test-suite spec + type: exitcode-stdio-1.0 + hs-source-dirs: test + main-is: Spec.hs + other-modules: DimSpec + PrettyBitsSpec + SamplesSpec + build-tool-depends: + hspec-discover:hspec-discover + build-depends: base >= 4.7 && < 5 + , data-svd + , data-default-class + , hspec + , hspec-golden + , lens + , prettyprinter + default-language: Haskell2010 + +source-repository head + type: git + location: https://github.com/DistRap/data-svd diff --git a/src/Data/Bits/Pretty.hs b/src/Data/Bits/Pretty.hs new file mode 100644 --- /dev/null +++ b/src/Data/Bits/Pretty.hs @@ -0,0 +1,95 @@ +module Data.Bits.Pretty + ( + -- * Show in base + showBin + , showDec + , showHex + , formatHex + -- * Show binary groups + , showBinGroups + -- * Size of Int + , platformSizeOfInt + -- * Shorthand + , showHex8 + , showHex16 + , showHex32 + ) where + +import Data.Bits (FiniteBits, (.&.), shiftR) +import Data.Word (Word8, Word16, Word32) +import Text.Printf (PrintfArg, printf) +import qualified Data.Bits + +-- * Show in base + +-- | Format number using binary notation with leading 0b, +-- padded according to its bit size +showBin :: (PrintfArg t, FiniteBits t) => t -> String +showBin x = + printf + ("0b%0" + ++ (show $ Data.Bits.finiteBitSize x) + ++ "b" + ) + x + +-- | Format number using decimal +showDec :: (PrintfArg t, FiniteBits t) => t -> String +showDec x = + printf ("%0" ++ (show decSize) ++ "u") x + where + decSize :: Int + decSize = + ceiling + $ logBase + (10 :: Double) + (2 ^ (Data.Bits.finiteBitSize x)) + +-- | Format number using hexadecimal notation with leading 0x, +-- padded according to its bit size +showHex :: (PrintfArg t, FiniteBits t) => t -> String +showHex x = + printf + ("0x%0" + ++ (show $ Data.Bits.finiteBitSize x `div` 4) + ++ "X" + ) + x + +-- | Format number using hexadecimal notation with leading 0x +formatHex :: PrintfArg t => t -> String +formatHex = printf "0x%x" + +-- * Show binary groups + +-- | Print number in binary with bits grouped by `groupSize` +-- e.g. with `groupSize = 4` we would get `0000 1010 0000 0101` +showBinGroups :: (PrintfArg b, Num b, FiniteBits b) => Int -> b -> String +showBinGroups groupSize x = + unwords + $ flip map [gs -1 ,gs - 2 .. 0] + $ \g -> ((printf ("%0" ++ (show groupSize) ++ "b") (mask g x)) :: String) + where + mask g n = (2^groupSize - 1) .&. (n `shiftR` (fromIntegral (g * groupSize))) + gs = sz `div` groupSize + sz = fromIntegral $ Data.Bits.finiteBitSize x + +-- * Size of Int + +-- | Size of `Int` at the current platform +platformSizeOfInt :: Int +platformSizeOfInt = Data.Bits.finiteBitSize (0 :: Int) + +-- * Shorthand + +-- | Format Int as 32-bit unsigned hexadecimal string +showHex32 :: Int -> String +showHex32 = showHex . (fromIntegral :: Int -> Word32) + +-- | Format Int as 16-bit unsigned hexadecimal string +showHex16 :: Int -> String +showHex16 = showHex . (fromIntegral :: Int -> Word16) + +-- | Format Int as 8-bit unsigned hexadecimal string +showHex8 :: Int -> String +showHex8 = showHex . (fromIntegral :: Int -> Word8) diff --git a/src/Data/SVD.hs b/src/Data/SVD.hs new file mode 100644 --- /dev/null +++ b/src/Data/SVD.hs @@ -0,0 +1,19 @@ +module Data.SVD ( + module Data.SVD.Diff + , module Data.SVD.Dim + , module Data.SVD.IO + , module Data.SVD.Lens + , module Data.SVD.Parse + , module Data.SVD.Pretty + , module Data.SVD.Types + , module Data.SVD.Util + ) where + +import Data.SVD.Diff +import Data.SVD.Dim +import Data.SVD.IO +import Data.SVD.Lens +import Data.SVD.Parse +import Data.SVD.Pretty +import Data.SVD.Types +import Data.SVD.Util diff --git a/src/Data/SVD/Diff.hs b/src/Data/SVD/Diff.hs new file mode 100644 --- /dev/null +++ b/src/Data/SVD/Diff.hs @@ -0,0 +1,103 @@ +module Data.SVD.Diff where + +import Data.Algorithm.Diff (Diff, PolyDiff(..)) +import qualified Data.Algorithm.Diff +import qualified Data.List +import qualified Data.Maybe +import qualified Safe + +import Data.SVD.Types + ( Device(..) + , Peripheral(..) + , Register(..) + , Field(..) + ) + +import Data.SVD.Util + ( fieldNames + , registerNames + ) + +diffPeriphNames + :: Device + -> Device + -> [Diff String] +diffPeriphNames dev1 dev2 = + Data.Algorithm.Diff.getDiff + (Data.List.sort $ map periphName $ devicePeripherals dev1) + (Data.List.sort $ map periphName $ devicePeripherals dev2) + +diffRegisterNames + :: String + -> Device + -> Device + -> [Diff String] +diffRegisterNames pName dev1 dev2 = + Data.Algorithm.Diff.getDiff + (Data.List.sort $ registerNames pName dev1) + (Data.List.sort $ registerNames pName dev2) + +regNames :: Peripheral -> [String] +regNames = map regName . periphRegisters + +diffRegNames :: Peripheral -> Peripheral -> [Diff String] +diffRegNames = diff regNames + +regNameFields :: String -> Peripheral -> [Field] +regNameFields rName = + regFields + . Safe.headNote "regNameFields" + . filter((==rName) . regName) + . periphRegisters + +diff + :: Ord a + => (t -> [a]) + -> t + -> t + -> [Diff a] +diff fn x y = + Data.Algorithm.Diff.getDiff + (Data.List.sort $ fn x) + (Data.List.sort $ fn y) + +diffFieldNames + :: String + -> String + -> Device + -> Device + -> [Diff String] +diffFieldNames pName regName' dev1 dev2 = + Data.Algorithm.Diff.getDiff + (Data.List.sort $ fieldNames regName' pName dev1) + (Data.List.sort $ fieldNames regName' pName dev2) + +diffFields + :: [Field] + -> [Field] + -> [PolyDiff Field Field] +diffFields as bs = + Data.Algorithm.Diff.getDiffBy + (\x y -> + cmps fieldName x y + && cmps fieldBitWidth x y + && cmps fieldBitOffset x y + ) + (Data.List.sortOn fieldBitOffset as) + (Data.List.sortOn fieldBitOffset bs) + where + cmps fn a b = fn a == fn b + +diffDistance :: [PolyDiff a b] -> Int +diffDistance x = + sum $ map go x + where + go (Both _ _) = 0 + go (First _) = 1 + go (Second _) = 1 + +getBoths :: [PolyDiff a b] -> [a] +getBoths = Data.Maybe.catMaybes . map ex + where + ex (Both x _) = Just x + ex _ = Nothing diff --git a/src/Data/SVD/Dim.hs b/src/Data/SVD/Dim.hs new file mode 100644 --- /dev/null +++ b/src/Data/SVD/Dim.hs @@ -0,0 +1,145 @@ +{-# LANGUAGE FlexibleContexts #-} +{-# LANGUAGE LambdaCase #-} +{-# LANGUAGE ScopedTypeVariables #-} + +module Data.SVD.Dim + ( expandDevice + -- * For testing + , expandCluster + , expandField + , expandRegister + ) where + +import Control.Lens ((^.), set, over) +import Data.SVD.Lens +import Data.SVD.Types + +-- * Dimension expansion + +-- Expand @Cluster@, @Field@, @Register@ into multiples +-- according to its @Dimension@ +-- +-- If @Dimension@ is nothing return singleton with the original +expandDim + :: ( HasName a String + , HasDescription a String + , HasDimension a (Maybe Dimension) + ) + => (a -> Int) -- ^ Address offset or bit offset getter + -> (Int -> a -> a) -- ^ Address offset or bit offset setter + -> a + -> [a] +expandDim getOffset setOffset element = + case element ^. dimension of + Nothing -> pure element + Just dim -> + let ixs = case dim ^. index of + DimensionIndex_FromTo f t -> map show [f .. t] + DimensionIndex_List l -> l + + gen z i ix = + let nameTemplate = z ^. name + descTemplate = z ^. description + baseOffset = getOffset z + template ('%':'s':xs) replacement = replacement ++ xs + template (x:xs) replacement = x:(template xs replacement) + template [] _ = mempty + in + setOffset + (baseOffset + dim ^. increment * i) + . set + name + (template nameTemplate ix) + . set + description + (template descTemplate ix) + $ set + dimension + Nothing + z + in + [ gen element i ix | (i, ix) <- zip [0..] ixs ] + +-- | Expand @Field@ into multiple fields if it has a @Dimension@ +-- return just the field if not +expandField :: Field -> [Field] +expandField = expandDim (^. bitOffset) (set bitOffset) + +-- | Expand @Cluster@ into multiple cluster if it has a @Dimension@ +-- return just the cluster if not +expandCluster :: Cluster -> [Cluster] +expandCluster = expandDim (^. addressOffset) (set addressOffset) + +-- | Expand @Register@ into multiple registers if it has a @Dimension@ +-- return just the register if not +expandRegister :: Register -> [Register] +expandRegister = expandDim (^. addressOffset) (set addressOffset) + +-- | Expand all fields of a register +expandRegFields :: Register -> Register +expandRegFields r = + set + fields + (concatMap expandField (r ^. fields)) + r + +-- | Expand all registers of a peripheral +expandPeriphRegisters :: Peripheral -> Peripheral +expandPeriphRegisters p = + set + registers + (concatMap expandRegister (p ^. registers)) + p + +-- | Expand all cluster of a peripheral +-- then eliminate all of them into registers +expandPeriphClusters :: Peripheral -> Peripheral +expandPeriphClusters p = + set + clusters + mempty + $ set + registers + (let + expClusters = + concatMap + expandCluster + (p ^. clusters) + in + (p ^. registers) + ++ concatMap + eliminateCluster + expClusters + ) + p + +-- | Turn expanded @Cluster@ into @Register@s +-- adding its addressOffset to each registers addressOffset +eliminateCluster :: Cluster -> [Register] +eliminateCluster c = + map + (\r -> + over + addressOffset + (+(c ^. addressOffset)) + r + ) + $ c ^. registers + +-- | Expand all dimensions and clusters +-- +-- In order +-- - Expand and eliminate each cluster +-- - Expand fields of each register +-- - Expand each register +expandDevice :: Device -> Device +expandDevice = + over + (peripherals . traverse) + expandPeriphRegisters + . over + (peripherals . traverse . registers . traverse) + expandRegFields + . over + (peripherals . traverse) + expandPeriphClusters diff --git a/src/Data/SVD/IO.hs b/src/Data/SVD/IO.hs new file mode 100644 --- /dev/null +++ b/src/Data/SVD/IO.hs @@ -0,0 +1,133 @@ +{-# LANGUAGE DeriveGeneric #-} +{-# LANGUAGE LambdaCase #-} +{-# LANGUAGE RecordWildCards #-} + +module Data.SVD.IO + ( parseSVD + , parseSVDOptions + , SVDOptions(..) + ) where + +import Data.Default.Class (Default(def)) +import Data.Hashable (Hashable) +import Data.SVD.Types (Device) +import GHC.Generics (Generic) +import Text.XML.HXT.Core (readString, runX, (>>>)) + +import qualified Data.Bool +import qualified Data.ByteString.Char8 +import qualified Data.Hashable +import qualified Data.Serialize +import qualified Data.SVD.Dim +import qualified Data.SVD.Parse +import qualified Data.SVD.Util +import qualified System.Directory + +data SVDSort + = SVDSort_DontSort + | SVDSort_SortByNames + | SVDSort_SortByAddresses + deriving (Eq, Ord, Generic, Show) + +instance Hashable SVDSort + +data SVDOptions = SVDOptions + { svdOptionsAddReservedFields :: Bool + -- ^ Fill in dummy reserved fields where + -- holes would be in registers + , svdOptionsCache :: Bool + -- ^ Cache parsed SVD in /tmp + -- based on a hash of the input svd file + , svdOptionsCheckContinuity :: Bool + -- ^ Check register continuity + , svdOptionsExpand :: Bool + -- ^ Expand dimensions and clusters + , svdOptionsSort :: SVDSort + -- ^ Sorting + } deriving (Eq, Ord, Generic, Show) + +instance Default SVDOptions where + def = SVDOptions + { svdOptionsAddReservedFields = True + , svdOptionsCache = True + , svdOptionsCheckContinuity = True + , svdOptionsExpand = True + , svdOptionsSort = SVDSort_SortByAddresses + } + +instance Hashable SVDOptions + +parseSVDOptions + :: SVDOptions + -> String + -> IO (Either String Device) +parseSVDOptions opts@SVDOptions{..} f = do + s <- readFile f + -- If caching is enabled we hash the input + -- string + options and try to load + -- serialized binary from cache if it exists + -- or create one if not for further invocations + let fHash = Data.Hashable.hash s + optsHash = Data.Hashable.hash opts + caFile = + "/tmp/svdCache-" + <> show fHash + <> "-" + <> show optsHash + + if not svdOptionsCache + then parseSVDFromString opts s + else do + hasCached <- System.Directory.doesFileExist caFile + if hasCached + then + Data.Serialize.decode + <$> Data.ByteString.Char8.readFile caFile + >>= \case + Left e -> + error + $ "Can't decode cached svd from " + <> caFile + <> " error was " + <> e + Right x -> pure x + else do + res <- parseSVDFromString opts s + Data.ByteString.Char8.writeFile + caFile + $ Data.Serialize.encode res + pure res + +parseSVDFromString + :: SVDOptions + -> String + -> IO (Either String Device) +parseSVDFromString SVDOptions{..} s = do + res <- runX (readString [] s >>> Data.SVD.Parse.svd) + case res of + [] -> pure $ Left "No device parsed" + [x] -> + pure + . Data.Bool.bool + Right + Data.SVD.Util.checkDeviceRegisterContinuity + svdOptionsCheckContinuity + . case svdOptionsSort of + SVDSort_DontSort -> id + SVDSort_SortByAddresses -> Data.SVD.Util.sortDeviceByAddresses + SVDSort_SortByNames -> Data.SVD.Util.sortDeviceByNames + . Data.Bool.bool + id + Data.SVD.Util.addReservedFields + svdOptionsAddReservedFields + . Data.Bool.bool + id + Data.SVD.Dim.expandDevice + svdOptionsExpand + $ x + _ -> pure $ Left "Multiple devices parsed" + +parseSVD + :: String + -> IO (Either String Device) +parseSVD = parseSVDOptions def diff --git a/src/Data/SVD/Lens.hs b/src/Data/SVD/Lens.hs new file mode 100644 --- /dev/null +++ b/src/Data/SVD/Lens.hs @@ -0,0 +1,19 @@ +{-# LANGUAGE FlexibleInstances #-} +{-# LANGUAGE FunctionalDependencies #-} +{-# LANGUAGE MultiParamTypeClasses #-} +{-# LANGUAGE TemplateHaskell #-} +{-# LANGUAGE TypeSynonymInstances #-} + +module Data.SVD.Lens where + +import Control.Lens +import Data.SVD.Types + +makeFields ''Device +makeLensesWith abbreviatedFields ''Peripheral +makeLensesWith abbreviatedFields ''Register +makeFields ''Field +makeFields ''Cluster +makeFields ''Dimension +makeFields ''Interrupt +makeFields ''AddressBlock diff --git a/src/Data/SVD/Parse.hs b/src/Data/SVD/Parse.hs new file mode 100644 --- /dev/null +++ b/src/Data/SVD/Parse.hs @@ -0,0 +1,226 @@ +{-# LANGUAGE Arrows #-} +{-# LANGUAGE NoMonomorphismRestriction #-} +{-# LANGUAGE RecordWildCards #-} + +module Data.SVD.Parse where + +import Safe + +import Control.Arrow.ArrowList +import qualified Data.Char as Char +import qualified Data.Maybe +import Data.Tree.NTree.TypeDefs +import Text.XML.HXT.Core + +import Data.SVD.Types + +-- atTag doesn't uses deep here +atTag :: ArrowXml cat => String -> cat (NTree XNode) XmlTree +atTag tag = getChildren >>> hasName tag + +text :: ArrowXml cat => cat (NTree XNode) String +text = getChildren >>> getText + +textAtTag :: ArrowXml cat => String -> cat (NTree XNode) String +textAtTag tag = text <<< atTag tag + +textAtTagOrEmpty :: ArrowXml cat => String -> cat (NTree XNode) String +textAtTagOrEmpty tag = withDefault (text <<< atTag tag) "" + +att :: ArrowXml cat => String -> cat XmlTree String +att = getAttrValue + +-- nonempty attr value +attNE :: ArrowXml cat => String -> cat XmlTree String +attNE x = getAttrValue x >>> isA (/= "") + +attMaybe :: ArrowXml cat => String -> String -> cat (NTree XNode) (Maybe String) +attMaybe attname tagname = + withDefault + (arr Just <<< attNE attname <<< atTag tagname) + Nothing + +filterCrap :: String -> String +filterCrap = + unwords + . words + . filter (\c -> Char.ord c < 127) + . filter ( not . (`elem` ['\n', '\t', '\r'])) + +-- svd parser +svd :: ArrowXml cat => cat (NTree XNode) Device +svd = atTag "device" >>> + proc x -> do + --name <- text <<< hasName "name" <<< getChildren -< x + deviceName <- textAtTag "name" -< x + deviceVersion <- textAtTag "version" -< x + desc <- textAtTag "description" -< x + addressUnitBits' <- textAtTag "addressUnitBits" -< x + width' <- textAtTag "width" -< x + size' <- textAtTag "size" -< x + resetValue' <- textAtTag "resetValue" -< x + resetMask' <- textAtTag "resetMask" -< x + + let deviceAddressUnitBits = read addressUnitBits' + deviceWidth = read width' + deviceSize = read size' + deviceResetValue = read resetValue' + deviceResetMask = read resetMask' + deviceDescription = filterCrap desc + + devicePeripherals <- listA parsePeripheral <<< atTag "peripherals" -< x + + returnA -< Device{..} + +-- loose version of svd that doesn't require device properties +svdPeripherals :: ArrowXml cat => cat (NTree XNode) [Peripheral] +svdPeripherals = atTag "device" >>> + proc x -> do + devicePeripherals <- listA parsePeripheral <<< atTag "peripherals" -< x + returnA -< devicePeripherals + +parsePeripheral :: ArrowXml cat => cat (NTree XNode) Peripheral +parsePeripheral = atTag "peripheral" >>> + proc x -> do + -- only these three avail for derived peripherals + periphName <- textAtTag "name" -< x + periphDerivedFrom <- withDefault (arr Just <<< isA (/= "") <<< att "derivedFrom") Nothing -< x + baseAddress' <- textAtTag "baseAddress" -< x + + desc <- withDefault (textAtTag "description") "" -< x + periphGroupName <- withDefault (textAtTag "groupName") "" -< x + periphAddressBlock <- withDefault (arr Just <<< parseAddressBlock) Nothing -< x + + periphInterrupts <- listA parseInterrupt -< x + + periphRegisters <- withDefault (listA parseRegister <<< atTag "registers") mempty -< x + periphClusters <- withDefault (listA parseCluster <<< atTag "registers") mempty -< x + + let periphBaseAddress = read baseAddress' + periphDescription = filterCrap desc + + returnA -< Peripheral{..} + +parseAddressBlock + :: ArrowXml cat + => cat (NTree XNode) AddressBlock +parseAddressBlock = atTag "addressBlock" >>> + proc x -> do + offset <- textAtTag "offset" -< x + size <- textAtTag "size" -< x + addressBlockUsage <- textAtTag "usage" -< x + + let addressBlockOffset = read offset + addressBlockSize = read size + + returnA -< AddressBlock{..} + +parseInterrupt + :: ArrowXml cat + => cat (NTree XNode) Interrupt +parseInterrupt = atTag "interrupt" >>> + proc x -> do + name <- textAtTag "name" -< x + desc <- textAtTag "description" -< x + val <- textAtTag "value" -< x + + let interruptName = map Char.toUpper name + interruptValue = read val + interruptDescription = filterCrap desc + + returnA -< Interrupt{..} + +parseCluster + :: ArrowXml cat + => cat (NTree XNode) Cluster +parseCluster = atTag "cluster" >>> + proc x -> do + clusterName <- textAtTag "name" -< x + clusterDescription <- textAtTag "description" -< x + clusterDimension <- withDefault (arr Just <<< parseDimension) Nothing -< x + offset <- textAtTag "addressOffset" -< x + clusterRegisters <- listA parseRegister -< x + clusterNested <- listA parseCluster -< x + + let clusterAddressOffset = read offset + returnA -< Cluster{..} + +parseDimension + :: ArrowXml cat + => cat (NTree XNode) Dimension +parseDimension = + proc x -> do + dim <- textAtTag "dim" -< x + dimIncr <- textAtTag "dimIncrement" -< x + dimIdx <- textAtTag "dimIndex" -< x + + let + dimensionSize = read dim + dimensionIncrement = read dimIncr + dimensionIndex = case dimIdx of + i | '-' `elem` i -> case words [ if c == '-' then ' ' else c | c <- i ] of + [from, to] -> DimensionIndex_FromTo (read from) (read to) + _ -> error $ "Don't know how to handle ranged dimIndex: " <> i + i | ',' `elem` i -> DimensionIndex_List $ words [ if c == ',' then ' ' else c | c <- i ] + i | otherwise -> error $ "Don't know how to handle dimIndex: " <> i + returnA -< Dimension{..} + +parseRegister + :: ArrowXml cat + => cat (NTree XNode) Register +parseRegister = atTag "register" >>> + proc x -> do + regName <- textAtTag "name" -< x + regDisplayName <- textAtTagOrEmpty "displayName" -< x + desc <- textAtTagOrEmpty "description" -< x + + offset <- textAtTag "addressOffset" -< x + size <- textAtTag "size" -< x + access <- withDefault (textAtTag "access") "read-write" -< x + + regResetValue <- withDefault (arr (Just . read) <<< textAtTag "resetValue") Nothing -< x + regFields <- withDefault (listA parseField <<< atTag "fields") [] -< x + + regDimension <- withDefault (arr Just <<< parseDimension) Nothing -< x + + let regAddressOffset = read offset + regSize = read size + regAccess = toAccessType access + regDescription = filterCrap desc + + returnA -< Register{..} + +parseField + :: ArrowXml cat + => cat (NTree XNode) Field +parseField = atTag "field" >>> + proc x -> do + fieldName <- textAtTag "name" -< x + fieldDimension <- withDefault (arr Just <<< parseDimension) Nothing -< x + desc <- textAtTagOrEmpty "description" -< x + + bitOffsetMay <- withDefault (arr (Just . read) <<< textAtTag "bitOffset") Nothing -< x + bitWidthMay <- withDefault (arr (Just . read) <<< textAtTag "bitWidth") Nothing -< x + + -- bitRange [MSB:LSB] + bitRange <- withDefault (arr (Just . splitRange) <<< textAtTag "bitRange") Nothing -< x + + -- XXX: TODO: one more possibility is lsb msb tags format, handle if needed + + let errmsg = error "Neither bitRange nor bitOffset + bitWidth defined" + (fieldBitOffset, fieldBitWidth) = case bitRange of + Nothing -> ( Data.Maybe.fromMaybe errmsg bitOffsetMay + , Data.Maybe.fromMaybe errmsg bitWidthMay) + Just (msb, lsb) -> (lsb, msb - lsb + 1) + + fieldDescription = filterCrap desc + fieldReserved = False + fieldRegType = Nothing + + returnA -< Field{..} + where + splitRange :: String -> (Int, Int) + splitRange r = (readNote "splitRange" $ takeWhile (/=':') raw, + readNote "splitRange" $ drop 1 $ dropWhile (/=':') raw) + where + raw = drop 1 $ init r diff --git a/src/Data/SVD/Pretty.hs b/src/Data/SVD/Pretty.hs new file mode 100644 --- /dev/null +++ b/src/Data/SVD/Pretty.hs @@ -0,0 +1,259 @@ +{-# LANGUAGE OverloadedStrings #-} +{-# LANGUAGE RecordWildCards #-} + +module Data.SVD.Pretty + ( + -- * Helpers + ppList + , displayPretty + , displayCompact + -- * Shorthand + , displayDevice + , displayDeviceInfo + , displayPeripheral + , displayRegister + , displayMemMap + , displayMemMapCompact + , displayDevISR + , displayISRs + -- * Pretty printers + , ppDevice + , ppPeriph + , ppReg + , ppHex + -- ** Interrupts + , ppDevISR + , ppISR + -- ** Terse output + , ppDeviceInfo + , ppPeriphName + , shortField + -- ** MemMap + , ppMem + -- * Who knows + , printSetFields + , printSetField + , showField + , fieldRange + , hexFieldVal + ) + where + +import Data.Char (toLower) +import Data.SVD.Types +import Data.Word +import Prettyprinter +import Prettyprinter.Render.String +import Prettyprinter.Render.Terminal (AnsiStyle, Color(..), color) + +import qualified Data.Bits.Pretty +import qualified Data.SVD.Util +import qualified Data.Text +import qualified Prettyprinter.Render.Terminal + +-- * Helpers + +ppList :: (a -> Doc AnsiStyle) -> [a] -> Doc AnsiStyle +ppList pp x = vcat $ map pp x + +displayPretty :: Doc AnsiStyle -> String +displayPretty = + Data.Text.unpack + . Prettyprinter.Render.Terminal.renderStrict + . layoutPretty defaultLayoutOptions + +displayCompact :: Doc AnsiStyle -> String +displayCompact = + renderString + . layoutCompact + +-- * Shorthand + +displayDevice :: Device -> String +displayDevice = displayPretty . ppDevice + +displayDeviceInfo :: Device -> String +displayDeviceInfo = displayPretty . ppDeviceInfo + +displayPeripheral :: Peripheral -> String +displayPeripheral = displayPretty . ppPeriph + +displayRegister :: Register -> String +displayRegister = displayPretty . ppReg + +displayMemMap :: [(String, String)] -> String +displayMemMap = displayPretty . ppList ppMem + +displayMemMapCompact :: [(String, String)] -> String +displayMemMapCompact = displayCompact . ppList ppMem + +displayDevISR :: Device -> String +displayDevISR = displayPretty . ppDevISR + +displayISRs :: [Interrupt] -> String +displayISRs = displayPretty . ppList ppISR + +-- * Pretty printers + +ppDevice :: Device -> Doc AnsiStyle +ppDevice Device{..} = + (annotate (color Red) $ pretty deviceName) + <> line + <> indent 2 (ppList ppPeriph devicePeripherals) + +ppPeriph :: Peripheral -> Doc AnsiStyle +ppPeriph Peripheral{..} = + hardline + <> annotate (color Yellow) + (pretty periphName) + <+> annotate (color White) + (ppHex periphBaseAddress) + <+> annotate (color Magenta) + (pretty periphDescription) + <> line + <> indent 2 (ppList ppReg periphRegisters) + <> maybe + mempty + (\x -> + indent 2 + $ line + <> pretty ("Derived from" :: String) + <+> pretty x + ) + periphDerivedFrom + +ppReg :: Register -> Doc AnsiStyle +ppReg Register{..} = + hardline + <> annotate (color Blue) + (pretty regName) + <+> annotate (color White) + (ppHex regAddressOffset) + <+> annotate (color Cyan) + (pretty '-' <+> (pretty regDescription)) + <> line + <> indent 2 + (ppList ppField regFields) + +ppHex :: Int -> Doc AnsiStyle +ppHex = pretty . Data.Bits.Pretty.formatHex + +rpad :: Int -> String -> String +rpad m xs = take m $ xs ++ repeat ' ' + +ppField :: Field -> Doc AnsiStyle +ppField Field{..} = + annotate (color Green) + (pretty $ rpad 25 fieldName) + <+> pretty ("::" :: String) + <+> ppWidthPad 7 fieldBitWidth + <+> annotate + (color Cyan) + (pretty $ " -- " ++ fieldDescription) + +ppWidthPad + :: Int + -> Int + -> Doc AnsiStyle +ppWidthPad m 1 = pretty $ rpad m "Bit" +ppWidthPad m x = pretty $ rpad m $ "Bits " ++ show x + +-- ** Interrupts + +ppDevISR :: Device -> Doc AnsiStyle +ppDevISR Device{..} = ppList ppPeriphISR devicePeripherals + +ppPeriphISR :: Peripheral -> Doc AnsiStyle +ppPeriphISR Peripheral{..} = + indent 2 (ppList ppISR periphInterrupts) +-- (maybe empty (\x -> string "Derived from" <+> string x) periphDerivedFrom) + +ppISR :: Interrupt -> Doc AnsiStyle +ppISR Interrupt{..} = + indent 2 + ( + "|" + <+> pretty interruptName + <> " -- " <> pretty interruptValue <+> pretty interruptDescription + ) + +-- ** Terse output + +ppDeviceInfo :: Device -> Doc AnsiStyle +ppDeviceInfo Device{..} = + annotate (color Red) + (pretty deviceName) + <> line + <> indent 2 + (ppList ppPeriphName devicePeripherals) + +ppPeriphName :: Peripheral -> Doc AnsiStyle +ppPeriphName Peripheral{..} = + annotate (color Yellow) + (pretty periphName) + +shortField :: Field -> String +shortField Field{..} = unwords [ + fieldName + , "offset" + , show fieldBitOffset + , "width" + , show fieldBitWidth ] + +-- ** MemMap + +ppMem :: (String, String) -> Doc AnsiStyle +ppMem (addr, periph) = + name <> " :: Integer" + <> line + <> name + <> " = " + <> pretty addr + where + name = pretty (map toLower periph) <> "_periph_base" + +-- | Print currently set (non-zero) fields +printSetFields :: (Show a, Eq a, Num a) => [(a, Field)] -> String +printSetFields = + unlines + . map printSetField + . Data.SVD.Util.filterSet + +printSetField :: (Show a, Eq a, Num a) => (a, Field) -> String +printSetField (_, f) | fieldBitWidth f == 1 = concat ["Bit ", show (fieldBitOffset f), " ", fieldName f] +printSetField (v, f) | otherwise = concat [ + "Bits [" + , show (fieldBitOffset f) + , ":" + , show (fieldBitOffset f + fieldBitWidth f - 1) + , "]" + , " " + , fieldName f + , " value ", show v] + +-- | Show `Field` with its range, e.g BRR[15:0] (16 bit wide) +showField :: Field -> String +showField f@Field{..} | fieldReserved = "◦" ++ (fieldRange f) +showField f@Field{..} | otherwise = fieldName ++ (fieldRange f) + +-- | Datasheeeet like +fieldRange :: Field -> String +fieldRange Field{..} | fieldBitWidth == 1 = "" +fieldRange Field{..} | otherwise = concat ["[", show $ fieldBitWidth - 1, ":0]"] + +-- | Format field value in hex, padded according to `fieldBitWidth` +hexFieldVal :: (Integral x, Show x) => Field -> x -> String +hexFieldVal _ 0 = "0" +hexFieldVal f x | fieldBitWidth f == 1 = showBit x + where + showBit 0 = "0" + showBit 1 = "1" + showBit y = error $ "Not a bit: " ++ show y +hexFieldVal f x | fieldBitWidth f <= 8 = + Data.Bits.Pretty.showHex (fromIntegral x :: Word8) +hexFieldVal f x | fieldBitWidth f <= 16 = + Data.Bits.Pretty.showHex (fromIntegral x :: Word16) +hexFieldVal f x | fieldBitWidth f <= 32 = + Data.Bits.Pretty.showHex (fromIntegral x :: Word32) +hexFieldVal _ x | otherwise = + Data.Bits.Pretty.showHex (fromIntegral x :: Word64) diff --git a/src/Data/SVD/Types.hs b/src/Data/SVD/Types.hs new file mode 100644 --- /dev/null +++ b/src/Data/SVD/Types.hs @@ -0,0 +1,207 @@ +{-# LANGUAGE DeriveGeneric #-} + +module Data.SVD.Types + ( AccessType(..) + , toAccessType + , showAccessType + , AddressBlock(..) + , Cluster(..) + , Device(..) + , Dimension(..) + , DimensionIndex(..) + , Interrupt(..) + , Peripheral(..) + , Register(..) + , Field(..) + ) where + +import Data.Default.Class (Default(def)) +import Data.Serialize (Serialize) +import GHC.Generics (Generic) + +data Device = Device { + deviceName :: String + , deviceVersion :: String + , deviceDescription :: String + , deviceAddressUnitBits :: Int + , deviceWidth :: Int + , deviceSize :: Int + , deviceResetValue :: Int + , deviceResetMask :: Int + , devicePeripherals :: [Peripheral] + } deriving (Generic, Eq, Ord, Show) + +instance Default Device where + def = Device + { deviceName = "defaultDev" + , deviceVersion = mempty + , deviceDescription = mempty + , deviceAddressUnitBits = 0 + , deviceWidth = 0 + , deviceSize = 0 + , deviceResetValue = 0 + , deviceResetMask = 0 + , devicePeripherals = [] + } + +instance Serialize Device + +data Peripheral = Peripheral { + periphName :: String + , periphDescription :: String + , periphDerivedFrom :: Maybe String + , periphGroupName :: String + , periphBaseAddress :: Int + , periphAddressBlock :: Maybe AddressBlock + , periphInterrupts :: [Interrupt] + , periphRegisters :: [Register] + , periphClusters :: [Cluster] + } deriving (Generic, Eq, Ord, Show) + +instance Default Peripheral where + def = Peripheral + { periphName = "defaultPeriph" + , periphDescription = mempty + , periphDerivedFrom = Nothing + , periphGroupName = mempty + , periphBaseAddress = 0 + , periphAddressBlock = Nothing + , periphInterrupts = [] + , periphRegisters = [] + , periphClusters = [] + } + +instance Serialize Peripheral + +data AddressBlock = AddressBlock { + addressBlockOffset :: Int + , addressBlockSize :: Int + , addressBlockUsage :: String + } deriving (Generic, Eq, Ord, Show) + +instance Serialize AddressBlock + +data Interrupt = Interrupt { + interruptName :: String + , interruptDescription :: String + , interruptValue :: Int + } deriving (Generic, Eq, Ord, Show) + +instance Serialize Interrupt + +data DimensionIndex + = DimensionIndex_FromTo Int Int + | DimensionIndex_List [String] + deriving (Generic, Eq, Ord, Show) + +instance Serialize DimensionIndex + +data Dimension = Dimension { + dimensionSize :: Int + , dimensionIncrement :: Int + , dimensionIndex :: DimensionIndex + } deriving (Generic, Eq, Ord, Show) + +instance Serialize Dimension + +-- | Cluster describes a sequence of neighboring registers within a peripheral. +-- A specifies the addressOffset relative to the baseAddress of the grouping element. +-- All elements within a specify their addressOffset relative to the cluster base address +-- ( + ). +data Cluster = Cluster { + clusterName :: String + , clusterDimension :: Maybe Dimension + , clusterDescription :: String + , clusterAddressOffset :: Int + , clusterRegisters :: [Register] + -- unused, expansion not yet implemented + -- but also not quite present in any SVD we've seen + , clusterNested :: [Cluster] + } deriving (Generic, Eq, Ord, Show) + +instance Default Cluster where + def = Cluster + { clusterName = "defaultCluster" + , clusterDescription = mempty + , clusterDimension = Nothing + , clusterAddressOffset = 0 + , clusterRegisters = [] + , clusterNested = [] + } + +instance Serialize Cluster + +data Register = Register { + regName :: String + , regDisplayName :: String + , regDimension :: Maybe Dimension + , regDescription :: String + , regAddressOffset :: Int + , regSize :: Int + , regAccess :: AccessType + , regResetValue :: Maybe Int + , regFields :: [Field] + } deriving (Generic, Eq, Ord, Show) + +instance Default Register where + def = Register + { regName = "defaultRegister" + , regDisplayName = mempty + , regDimension = Nothing + , regDescription = mempty + , regAddressOffset = 0 + , regSize = 0 + , regAccess = ReadOnly + , regResetValue = Nothing + , regFields = [] + } + +instance Serialize Register + +data AccessType + = ReadOnly + | WriteOnly + | ReadWrite + | WriteOnce + | ReadWriteOnce + deriving (Generic, Eq, Ord, Show) + +instance Serialize AccessType + +data Field = Field { + fieldName :: String + , fieldDescription :: String + , fieldDimension :: Maybe Dimension + , fieldBitOffset :: Int + , fieldBitWidth :: Int + , fieldReserved :: Bool -- so we can add reserved fields to the list + , fieldRegType :: Maybe String -- ivory register type + } deriving (Generic, Eq, Ord, Show) + +instance Default Field where + def = Field + { fieldName = "defaultField" + , fieldDescription = mempty + , fieldDimension = Nothing + , fieldBitOffset = 0 + , fieldBitWidth = 0 + , fieldReserved = False + , fieldRegType = Nothing + } + +instance Serialize Field + +toAccessType :: String -> AccessType +toAccessType "read-only" = ReadOnly +toAccessType "write-only" = WriteOnly +toAccessType "read-write" = ReadWrite +toAccessType "writeOnce" = WriteOnce +toAccessType "read-writeOnce" = ReadWriteOnce +toAccessType x = error $ "Unable to read AccessType" ++ x + +showAccessType :: AccessType -> String +showAccessType ReadOnly = "read-only" +showAccessType WriteOnly = "write-only" +showAccessType ReadWrite = "read-write" +showAccessType WriteOnce = "writeOnce" +showAccessType ReadWriteOnce = "read-writeOnce" diff --git a/src/Data/SVD/Util.hs b/src/Data/SVD/Util.hs new file mode 100644 --- /dev/null +++ b/src/Data/SVD/Util.hs @@ -0,0 +1,425 @@ +{-# LANGUAGE RecordWildCards #-} + +module Data.SVD.Util + ( addReservedFields + , procFields + , continuityCheck + , checkDeviceRegisterContinuity + , mapPeriphs + , mapRegs + , mapFields + , mapDevFields + , getPeriphByGroup + , getPeriph + , getPeriphMay + , getPeriphRegMay + , getPeriphFollow + , getPeriphRegs + , getPeriphReg + , getPeriphRegAddr + , getPeriphRegFields + , getRegFields + , getFieldVal + , getFieldValues + , getProcdFieldValues + , anyReservedSet + , filterSet + , getDevMemMap + , registerNames + , fieldNames + -- * Sorting + , sortDeviceByAddresses + , sortDeviceByNames + -- * Interrupts + , fillMissingInterrupts + ) where + +import Control.Lens ((^.), over, set, view) +import Control.Monad (liftM2) +import Data.Bits (Bits, shiftR, (.&.)) +import Data.SVD.Lens +import Data.SVD.Types + +import qualified Data.Char +import qualified Data.Bits.Pretty +import qualified Data.Either +import qualified Data.List +import qualified Data.Maybe +import qualified Data.Set +import qualified Safe + +-- | Find holes in registers and create corresponding reserved fields for these +-- +-- First finds missing bits and then merges them to single reserved field +procFields :: Register -> [Field] +procFields Register{..} = + dataIfSingleReserved + $ reverse + $ sortByOffset (regFields ++ missingAsReserved) + where + missingAsReserved = + mkReserved + $ conts + $ Data.Set.toList missing + + mkReserved = + map + $ \(offset', width') -> + Field + { fieldName = "_" + , fieldDescription = "(Reserved)" + , fieldDimension = Nothing + , fieldBitOffset = offset' + , fieldBitWidth = width' + , fieldReserved = True + , fieldRegType = Nothing + } + + conts x = case cont x of + [] -> [] + s -> (head s, length s) : conts (drop (length s) x) + + -- find longest increasing sequence + cont :: (Eq a, Num a) => [a] -> [a] + cont (x:y:xs) | x + 1 == y = x : cont (y:xs) + cont (x:_) = [x] + cont [] = [] + + missing = allRegs `Data.Set.difference` existing + + allRegs = Data.Set.fromList [0..(regSize - 1)] + + existing = + Data.Set.fromList + $ flip concatMap (sortByOffset regFields) + $ \Field{..} -> [fieldBitOffset .. (fieldBitOffset + fieldBitWidth - 1)] + + sortByOffset = Data.List.sortOn fieldBitOffset + + -- this handles a case when there are no fields and code above + -- creates a single full-sized reserved field + -- which we turn into non-reserved "data" field + dataIfSingleReserved [f] | fieldReserved f = + [ f { + fieldName = "DATA" + , fieldReserved = False + } + ] + dataIfSingleReserved fs = fs + +-- | Fill in reserved fields for whole @Device@ +addReservedFields :: Device -> Device +addReservedFields = + over + (peripherals . traverse . registers . traverse) + procRegister + where + procRegister r = set fields (procFields r) r + +-- | Walk processed register fields top to bottom +-- checking that the register is exactly n bits long +continuityCheck :: Register -> Bool +continuityCheck Register{..} = go regFields regSize + where + go [] 0 = True + go (x:xs) remainingBits + | fieldBitOffset x + fieldBitWidth x == remainingBits + = go xs (remainingBits - fieldBitWidth x) + go _ _ = False + +-- | Walk processed register fields top to bottom +-- checking that the register is exactly n bits long +continuityCheckReg + :: Device + -> Peripheral + -> Register + -> Either String Register + +-- Some ignores +-- TIM5.CNT is 32 bit but has an aliased UIFCPY field +continuityCheckReg d p r + | d ^. name `elem` [ "STM32F730", "STM32F745", "STM32F750", "STM32F765" + , "STM32F7x2", "STM32F7x3", "STM32F7x6", "STM32F7x7", "STM32F7x9" ] + && p ^. name == "TIM5" && r ^. name == "CNT" = pure r +-- G4 TIM2.CCR5, might be a bug in stm32-rs +continuityCheckReg d p r + | d ^. name `elem` [ "STM32G431xx", "STM32G441xx", "STM32G471xx", "STM32G473xx" + , "STM32G474xx", "STM32G483xx", "STM32G484xx", "STM32G491xx", "STM32G4A1xx" ] + && p ^. name == "TIM2" && r ^. name == "CCR5" = pure r +continuityCheckReg d p r + | d ^. name == "STM32H73x" + && p ^. name == "CRYP" && r ^. name == "K2LR" = pure r +continuityCheckReg d p r + | (d ^. name == "STM32L0x2" || d ^. name == "STM32L0x3") + && p ^.name == "PWR" && r ^. name == "CR" = pure r +continuityCheckReg d p r + | d ^. name == "STM32L4P5" + && p ^.name == "TIM15" && r ^. name == "SR" = pure r +continuityCheckReg d p r + | d ^. name == "STM32L4P5" + && p ^.name == "SAI1" && r ^. name == "CR1" = pure r +continuityCheckReg d p r + | d ^. name == "STM32L4P5" + && p ^.name == "FLASH" && r ^. name == "ECCR" = pure r +continuityCheckReg d p r + | d ^. name == "STM32WB55" + && p ^.name == "TIM2" && r ^. name == "CNT" = pure r +continuityCheckReg d p r = + go + ( reverse + $ Data.List.sortOn + (view bitOffset) + (r ^. fields) + ) + (r ^. size) + where + go [] 0 = pure r + + go (x:xs) remainingBits + | x ^. bitOffset + x ^. bitWidth == remainingBits + = go xs (remainingBits - (x ^. bitWidth)) + + go _xs remainingBits = + Left + $ "Continuity check failed with remaining bits: " + <> show remainingBits + <> " for device " + <> d ^. name + <> " for " + <> p ^. name + <> "." + <> r ^. name + +-- | Check all devices registers for continuity +checkDeviceRegisterContinuity + :: Device + -> Either String Device +checkDeviceRegisterContinuity d = + let + res = + concatMap + (\p -> + map + (continuityCheckReg d p) + (p ^. registers) + ) + (devicePeripherals d) + in + case res of + _ | all Data.Either.isRight res -> pure d + _ | otherwise -> Left $ unlines $ Data.Either.lefts res + +mapPeriphs :: (Peripheral -> b) -> Device -> [b] +mapPeriphs f Device{..} = map f devicePeripherals + +mapRegs :: (Register -> b) -> Peripheral -> [b] +mapRegs f Peripheral{..} = map f periphRegisters + +mapFields :: (Field -> b) -> Register -> [b] +mapFields f Register{..} = map f regFields + +mapDevFields :: (Field -> b) -> Device -> [b] +mapDevFields f d = + concat + $ concat + $ flip mapPeriphs d + $ mapRegs + $ mapFields f + +-- | Get peripheral by groupName +getPeriphByGroup :: String -> Device -> Peripheral +getPeriphByGroup name' dev = + case filterLowerBy name' periphGroupName (devicePeripherals dev) of + [] -> error $ "getPeriphByGroup, peripheral " ++ name' ++ " not found" + [p] -> p + ps -> case filter (Data.Maybe.isNothing . periphDerivedFrom) ps of + [] -> error $ "getPeriphByGroup: No non-derived peripheral found for " ++ name' + [p] -> p + (p:_xs) -> p + -- TODO: warn? + -- error $ "getPeriphByGroup: Multiple non-derived peripheral found for " ++ name + +-- | Get peripheral by name +getPeriph :: String -> Device -> Peripheral +getPeriph name' dev = + Safe.headNote ("getPeriph " ++ name') + . filterLowerBy name' periphName $ devicePeripherals dev + +-- | Get peripheral by name iff found, Nothing otherwise +getPeriphMay :: String -> Device -> Maybe Peripheral +getPeriphMay name' dev = + Safe.headMay + . filterLowerBy name' periphName $ devicePeripherals dev + +-- | Get register of the peripheral by their names iff found, Nothing otherwise +getPeriphRegMay :: String -> Peripheral -> Maybe Register +getPeriphRegMay rName = + Safe.headMay + . filterLowerBy rName regName . periphRegisters + +-- | Filter elements matching lowercased `eqTo` after applying `by` +filterLowerBy :: String -> (a -> String) -> [a] -> [a] +filterLowerBy eqTo by = + filter + $ (== map Data.Char.toLower eqTo) + . map Data.Char.toLower + . by + +-- | Get peripheral by name or its parent peripheral if it's +-- a derived peripheral (for example USART2 is typically derived from USART1) +getPeriphFollow :: String -> Device -> Either String Peripheral +getPeriphFollow pName dev = case getPeriphMay pName dev of + Nothing -> Left $ "No peripheral found: " ++ pName + Just p -> case periphDerivedFrom p of + Nothing -> Right p + Just fromName -> case getPeriphMay fromName dev of + Nothing -> Left $ "Parent peripheral not found: " ++ fromName ++ " for peripheral " ++ pName + Just parentPeriph -> Right parentPeriph + +-- | Get registers of the peripheral +getPeriphRegs :: String -> Device -> Either String [Register] +getPeriphRegs pName dev = periphRegisters <$> getPeriphFollow pName dev + +-- | Get specific register of the peripheral +-- Follows derived from. +getPeriphReg :: String -> String -> Device -> Either String Register +getPeriphReg pName rName dev = + either + Left + (maybeToEither errMsg . getPeriphRegMay rName) + $ getPeriphFollow pName dev + where + errMsg = "No register found: " ++ rName ++ " for peripheral " ++ pName + +maybeToEither :: a -> Maybe b -> Either a b +maybeToEither msg m = case m of + Just x -> Right x + Nothing -> Left msg + +-- | Get address of the specific register of the peripheral with `pName` +getPeriphRegAddr :: String -> String -> Device -> Either String Int +getPeriphRegAddr pName rName dev = + (\p r -> periphBaseAddress p + regAddressOffset r) + <$> maybeToEither errMsg (getPeriphMay pName dev) + <*> getPeriphReg pName rName dev + where + errMsg = "No peripheral found " ++ pName + +-- | Get fields of the specific register of the peripheral with `pName` +getPeriphRegFields + :: String -- ^ Peripheral name + -> String -- ^ Register name + -> Device + -> Either String [Field] +getPeriphRegFields pName rName dev = + regFields <$> getPeriphReg pName rName dev + +getReg + :: String -- ^ Peripheral name + -> String -- ^ Register name + -> Device + -> Register +getReg pName rName dev = + Safe.headNote "getReg" + . filter((==rName) . regName) + . periphRegisters + $ getPeriph pName dev + +getRegFields + :: String -- ^ Peripheral name + -> String -- ^ Register name + -> Device + -> [Field] +getRegFields pName rName dev = + regFields + $ getReg pName rName dev + +-- | Get value of specific @Field@ according to input `x` +getFieldVal :: (Bits a, Num a) => a -> Field -> a +getFieldVal x f = (x `shiftR` fieldBitOffset f) .&. (2 ^ fieldBitWidth f - 1) + +-- | Decode integer `x` according to Fields `fs` +getFieldValues :: (Bits a, Num a) => a -> [Field] -> [(a, Field)] +getFieldValues x fs = zip (map (getFieldVal x) fs) fs + +-- | Same as `getFieldValues` but with processed fields (reserved fields included) +getProcdFieldValues :: (Bits a, Num a) => a -> Register -> [(a, Field)] +getProcdFieldValues x fs = getFieldValues x $ procFields fs + +-- | Check if any reserved field has value other than 0 +anyReservedSet :: (Eq a, Num a) => [(a, Field)] -> Bool +anyReservedSet = any (\(val, f) -> val /= 0 && fieldReserved f) + +-- | Filter fields with non zero value +filterSet :: (Eq a, Num a) => [(a, Field)] -> [(a, Field)] +filterSet = filter ((/= 0) . fst) + +-- | Get memory map of the device according to its perhiperal addresses +getDevMemMap :: Device -> [(String, String)] +getDevMemMap Device{..} = + map + (liftM2 (,) (Data.Bits.Pretty.formatHex . periphBaseAddress) periphName) + devicePeripherals + +registerNames :: String -> Device -> [String] +registerNames pName dev = + map + regName . periphRegisters + $ getPeriph pName dev + +fieldNames :: String -> String -> Device -> [String] +fieldNames rName pName dev = + map + fieldName + $ getRegFields pName rName dev + +-- * Sorting + +-- | Sort everything by memory address +sortDeviceByAddresses :: Device -> Device +sortDeviceByAddresses = + over + peripherals + (Data.List.sortOn (view baseAddress)) + . over + (peripherals . traverse . registers) + (Data.List.sortOn (view addressOffset)) + . over + (peripherals . traverse . registers . traverse . fields) + (reverse . Data.List.sortOn (view bitOffset)) + +-- | Sort everything by name +sortDeviceByNames :: Device -> Device +sortDeviceByNames = + over + peripherals + (Data.List.sortOn (view name)) + . over + (peripherals . traverse . registers) + (Data.List.sortOn (view name)) + . over + (peripherals . traverse . registers . traverse . fields) + (Data.List.sortOn (view name)) + +-- * Interrupts + +fillMissingInterrupts + :: [Interrupt] + -> [Interrupt] +fillMissingInterrupts isrs = + isrs + ++ (map filler $ missingInterrupts) + where + filler x = Interrupt { + interruptName = "Undefined" ++ show x + , interruptValue = x + , interruptDescription = "Undefined interrupt (padding only)" + } + missingInterrupts = + let + vals = map interruptValue isrs + in + Data.Set.toList + $ Data.Set.difference + (Data.Set.fromList [0 .. maximum vals]) + (Data.Set.fromList vals) diff --git a/test/DimSpec.hs b/test/DimSpec.hs new file mode 100644 --- /dev/null +++ b/test/DimSpec.hs @@ -0,0 +1,183 @@ +module DimSpec where + +import Control.Lens +import Data.Default.Class +import Data.SVD +import Test.Hspec (Spec, describe, it, shouldBe) + +spec :: Spec +spec = describe "Data.SVD.Dim" $ do + describe "expandField" $ do + it "no dim" $ + expandField def `shouldBe` pure def + + it "sampleField0" $ + expandField sampleField0 `shouldBe` resultField0 + + it "sampleField1" $ + expandField sampleField1 `shouldBe` resultField1 + + describe "expandRegister" $ do + it "sampleReg0" $ + expandRegister sampleReg0 `shouldBe` resultReg0 + + it "sampleReg1" $ + expandRegister sampleReg1 `shouldBe` resultReg1 + + describe "expandDevice" $ do + it "sampleDev0" $ + expandDevice sampleDev0 `shouldBe` resultDev0 + + it "sampleDev1" $ + expandDevice sampleDev1 `shouldBe` resultDev1 + +sampleDim0 = + Dimension + { dimensionSize = 3 + , dimensionIndex = DimensionIndex_FromTo 0 2 + , dimensionIncrement = 0x2 + } + +sampleField0 = def + { fieldName = "FX%s" + , fieldDimension = pure sampleDim0 + , fieldDescription = "Desc %s foo" + , fieldBitOffset = 0x2 + } + +resultField0 = + [ def + { fieldName = "FX0" + , fieldDescription = "Desc 0 foo" + , fieldBitOffset = 0x2 + } + , def + { fieldName = "FX1" + , fieldDescription = "Desc 1 foo" + , fieldBitOffset = 0x4 + } + , def + { fieldName = "FX2" + , fieldDescription = "Desc 2 foo" + , fieldBitOffset = 0x6 + } + ] + +sampleDim1 = + Dimension + { dimensionSize = 2 + , dimensionIndex = DimensionIndex_FromTo 1 2 + , dimensionIncrement = 0x2 + } + +sampleField1 = def + { fieldName = "FY%s" + , fieldDimension = pure sampleDim1 + , fieldDescription = "Desc %s foo" + , fieldBitOffset = 0x2 + } + +resultField1 = + [ def + { fieldName = "FY1" + , fieldDescription = "Desc 1 foo" + , fieldBitOffset = 0x2 + } + , def + { fieldName = "FY2" + , fieldDescription = "Desc 2 foo" + , fieldBitOffset = 0x4 + } + ] + +-- * Register + +sampleRegDim0 = + Dimension + { dimensionSize = 1 + , dimensionIndex = DimensionIndex_FromTo 1 1 + , dimensionIncrement = 0x4 + } + +sampleReg0 = def + { regName = "CCR%s" + , regDimension = pure sampleRegDim0 + , regDescription = "Desc %s" + , regAddressOffset = 0x34 + } + +resultReg0 = + [ def + { regName = "CCR1" + , regDescription = "Desc 1" + , regAddressOffset = 0x34 + } + ] + +sampleRegDim1 = + Dimension + { dimensionSize = 2 + , dimensionIndex = DimensionIndex_List ["AB", "CD"] + , dimensionIncrement = 0x4 + } + +sampleReg1 = def + { regName = "TEST%s" + , regDimension = pure sampleRegDim1 + , regDescription = "Desc %s foo" + , regAddressOffset = 0x34 + } + +resultReg1 = + [ def + { regName = "TESTAB" + , regDescription = "Desc AB foo" + , regAddressOffset = 0x34 + } + , def + { regName = "TESTCD" + , regDescription = "Desc CD foo" + , regAddressOffset = 0x38 + } + ] + +-- * Device + +samplePeriph0 = + def + { periphRegisters = pure $ sampleReg0 { regFields = pure sampleField0 } + } + +resultPeriph0 = + def + { periphRegisters = over (traverse . fields) (pure resultField0) resultReg0 + } + +sampleDev0 = def { devicePeripherals = pure samplePeriph0 } +resultDev0 = def { devicePeripherals = pure resultPeriph0 } + +-- ** With clusters + +sampleCluster0 = + def + { clusterRegisters = pure $ sampleReg1 { regFields = pure sampleField1 } + , clusterAddressOffset = 0x10 + } + +samplePeriph1 = + def + { periphRegisters = pure $ sampleReg0 { regFields = pure sampleField0 } + , periphClusters = pure $ sampleCluster0 + } + +resultPeriph1 = + def + { periphRegisters = + over (traverse . fields) (pure resultField0) resultReg0 + ++ map + (over addressOffset (+0x10)) + (over (traverse . fields) (pure resultField1) resultReg1) + } + +sampleDev1 = def { devicePeripherals = pure samplePeriph1 } +resultDev1 = def { devicePeripherals = pure resultPeriph1 } diff --git a/test/PrettyBitsSpec.hs b/test/PrettyBitsSpec.hs new file mode 100644 --- /dev/null +++ b/test/PrettyBitsSpec.hs @@ -0,0 +1,34 @@ +{-# LANGUAGE TypeApplications #-} +module PrettyBitsSpec where + +import Data.Word (Word8, Word16, Word32) +import Data.Bits.Pretty +import Test.Hspec (Spec, describe, it, shouldBe) + +spec :: Spec +spec = describe "Data.Bits.Pretty" $ do + it "showBin Word8" $ showBin @Word8 123 `shouldBe` "0b01111011" + it "showBin Word16" $ showBin @Word16 123 `shouldBe` "0b0000000001111011" + it "showDec Word8" $ showDec @Word8 123 `shouldBe` "123" + it "showDec Word16" $ showDec @Word16 123 `shouldBe` "00123" + it "showHex Word8" $ showHex @Word8 123 `shouldBe` "0x7B" + it "showHex Word16" $ showHex @Word16 123 `shouldBe` "0x007B" + it "showHex8" $ showHex8 123 `shouldBe` "0x7B" + it "showHex16" $ showHex16 123 `shouldBe` "0x007B" + it "showHex32" $ showHex32 123 `shouldBe` "0x0000007B" + + it "formatHex Word8" $ formatHex @Word8 123 `shouldBe` "0x7b" + it "formatHex Word16" $ formatHex @Word16 123 `shouldBe` "0x7b" + + it "showBinGroups 4 Word8" + $ showBinGroups @Word8 4 123 + `shouldBe` "0111 1011" + it "showBinGroups 4 Word16" + $ showBinGroups @Word16 4 maxBound + `shouldBe` "1111 1111 1111 1111" + it "showBinGroups 8 Word16" + $ showBinGroups @Word16 8 maxBound + `shouldBe` "11111111 11111111" + it "showBinGroups 4 Word32" + $ showBinGroups @Word32 4 maxBound + `shouldBe` "1111 1111 1111 1111 1111 1111 1111 1111" diff --git a/test/SamplesSpec.hs b/test/SamplesSpec.hs new file mode 100644 --- /dev/null +++ b/test/SamplesSpec.hs @@ -0,0 +1,71 @@ +{-# LANGUAGE LambdaCase #-} +module SamplesSpec where + +import Control.Lens +import Data.Default.Class +import Data.Either +import Data.SVD +import Test.Hspec (Spec, describe, it, shouldBe, shouldSatisfy) +import Test.Hspec.Golden (defaultGolden) +import Prettyprinter (unAnnotate) + +import qualified Data.List + +spec :: Spec +spec = describe "Golden" $ do + describe "stm32f405.svd" $ do + it "isRight" $ do + res <- parseSVD "./test/samples/stm32f405.svd" + res `shouldSatisfy` isRight + + it "has right number of peripherals" $ do + res <- + fmap + (length . view peripherals) + <$> parseSVD "./test/samples/stm32f405.svd" + res `shouldBe` (Right 85) + + it "matches golden pretty printed device" $ do + pretty <- + parseSVD "./test/samples/stm32f405.svd" + >>= \case + Left e -> error "Failed parsing" + Right x -> + pure + $ displayPretty + $ unAnnotate + $ ppDevice x + pure $ defaultGolden "stm32f405" pretty + + it "matches golden pretty printed device isrs" $ do + pretty <- + parseSVD "./test/samples/stm32f405.svd" + >>= \case + Left e -> error "Failed parsing" + Right x -> + pure + $ displayPretty + $ unAnnotate + $ ppList ppISR + $ Data.List.sortOn + interruptValue + $ fillMissingInterrupts + $ Data.List.nubBy + (\x y -> interruptValue x == interruptValue y) + $ concatMap + periphInterrupts + (devicePeripherals x) + pure $ defaultGolden "stm32f405-isrs" pretty + + it "matches golden pretty printed device memory map" $ do + pretty <- + parseSVD "./test/samples/stm32f405.svd" + >>= \case + Left e -> error "Failed parsing" + Right x -> + pure + $ displayPretty + $ unAnnotate + $ ppList ppMem + $ getDevMemMap x + pure $ defaultGolden "stm32f405-memmap" pretty diff --git a/test/Spec.hs b/test/Spec.hs new file mode 100644 --- /dev/null +++ b/test/Spec.hs @@ -0,0 +1,1 @@ +{-# OPTIONS_GHC -F -pgmF hspec-discover #-} diff --git a/test/samples/stm32f405.svd b/test/samples/stm32f405.svd new file mode 100644 --- /dev/null +++ b/test/samples/stm32f405.svd @@ -0,0 +1,44526 @@ + + + STM32F405 + 1.2 + STM32F405 + + CM4 + r1p0 + little + false + false + 4 + false + + 8 + 32 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RNG + Random number generator + RNG + 0x50060800 + + 0x0 + 0x400 + registers + + + FPU + FPU interrupt + 81 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IE + Interrupt enable + 3 + 1 + + IE + read-write + + Disabled + RNG interrupt is disabled + 0 + + + Enabled + RNG interrupt is enabled + 1 + + + + + RNGEN + Random number generator + enable + 2 + 1 + + RNGEN + read-write + + Disabled + Random number generator is disabled + 0 + + + Enabled + Random number generator is enabled + 1 + + + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt + status + 6 + 1 + read-write + + + CEIS + Clock error interrupt + status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + DCMI + Digital camera interface + DCMI + 0x50050000 + + 0x0 + 0x400 + registers + + + DCMI + DCMI global interrupt + 78 + + + + CR + CR + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + ENABLE + DCMI enable + 14 + 1 + + + EDM + Extended data mode + 10 + 2 + + + FCRC + Frame capture rate control + 8 + 2 + + + VSPOL + Vertical synchronization + polarity + 7 + 1 + + + HSPOL + Horizontal synchronization + polarity + 6 + 1 + + + PCKPOL + Pixel clock polarity + 5 + 1 + + + ESS + Embedded synchronization + select + 4 + 1 + + + JPEG + JPEG format + 3 + 1 + + + CROP + Crop feature + 2 + 1 + + + CM + Capture mode + 1 + 1 + + + CAPTURE + Capture enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + FNE + FIFO not empty + 2 + 1 + + + VSYNC + VSYNC + 1 + 1 + + + HSYNC + HSYNC + 0 + 1 + + + + + RIS + RIS + raw interrupt status register + 0x8 + 0x20 + read-only + 0x00000000 + + + LINE_RIS + Line raw interrupt status + 4 + 1 + + + VSYNC_RIS + VSYNC raw interrupt status + 3 + 1 + + + ERR_RIS + Synchronization error raw interrupt + status + 2 + 1 + + + OVR_RIS + Overrun raw interrupt + status + 1 + 1 + + + FRAME_RIS + Capture complete raw interrupt + status + 0 + 1 + + + + + IER + IER + interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + LINE_IE + Line interrupt enable + 4 + 1 + + + VSYNC_IE + VSYNC interrupt enable + 3 + 1 + + + ERR_IE + Synchronization error interrupt + enable + 2 + 1 + + + OVR_IE + Overrun interrupt enable + 1 + 1 + + + FRAME_IE + Capture complete interrupt + enable + 0 + 1 + + + + + MIS + MIS + masked interrupt status + register + 0x10 + 0x20 + read-only + 0x00000000 + + + LINE_MIS + Line masked interrupt + status + 4 + 1 + + + VSYNC_MIS + VSYNC masked interrupt + status + 3 + 1 + + + ERR_MIS + Synchronization error masked interrupt + status + 2 + 1 + + + OVR_MIS + Overrun masked interrupt + status + 1 + 1 + + + FRAME_MIS + Capture complete masked interrupt + status + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x14 + 0x20 + write-only + 0x00000000 + + + LINE_ISC + line interrupt status + clear + 4 + 1 + + + VSYNC_ISC + Vertical synch interrupt status + clear + 3 + 1 + + + ERR_ISC + Synchronization error interrupt status + clear + 2 + 1 + + + OVR_ISC + Overrun interrupt status + clear + 1 + 1 + + + FRAME_ISC + Capture complete interrupt status + clear + 0 + 1 + + + + + ESCR + ESCR + embedded synchronization code + register + 0x18 + 0x20 + read-write + 0x00000000 + + + FEC + Frame end delimiter code + 24 + 8 + + + LEC + Line end delimiter code + 16 + 8 + + + LSC + Line start delimiter code + 8 + 8 + + + FSC + Frame start delimiter code + 0 + 8 + + + + + ESUR + ESUR + embedded synchronization unmask + register + 0x1C + 0x20 + read-write + 0x00000000 + + + FEU + Frame end delimiter unmask + 24 + 8 + + + LEU + Line end delimiter unmask + 16 + 8 + + + LSU + Line start delimiter + unmask + 8 + 8 + + + FSU + Frame start delimiter + unmask + 0 + 8 + + + + + CWSTRT + CWSTRT + crop window start + 0x20 + 0x20 + read-write + 0x00000000 + + + VST + Vertical start line count + 16 + 13 + + + HOFFCNT + Horizontal offset count + 0 + 14 + + + + + CWSIZE + CWSIZE + crop window size + 0x24 + 0x20 + read-write + 0x00000000 + + + VLINE + Vertical line count + 16 + 14 + + + CAPCNT + Capture count + 0 + 14 + + + + + DR + DR + data register + 0x28 + 0x20 + read-only + 0x00000000 + + + Byte3 + Data byte 3 + 24 + 8 + + + Byte2 + Data byte 2 + 16 + 8 + + + Byte1 + Data byte 1 + 8 + 8 + + + Byte0 + Data byte 0 + 0 + 8 + + + + + + + FSMC + Flexible static memory controller + FSMC + 0xA0000000 + + 0x0 + 0x400 + registers + + + FSMC + FSMC global interrupt + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + CBURSTRW + read-write + + Disabled + Write operations are always performed in asynchronous mode + 0 + + + Enabled + Write operations are performed in synchronous mode + 1 + + + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + ASYNCWAIT + read-write + + Disabled + Wait signal not used in asynchronous mode + 0 + + + Enabled + Wait signal used even in asynchronous mode + 1 + + + + + EXTMOD + EXTMOD + 14 + 1 + + EXTMOD + read-write + + Disabled + Values inside the FMC_BWTR are not taken into account + 0 + + + Enabled + Values inside the FMC_BWTR are taken into account + 1 + + + + + WAITEN + WAITEN + 13 + 1 + + WAITEN + read-write + + Disabled + Values inside the FMC_BWTR are taken into account + 0 + + + Enabled + NWAIT signal enabled + 1 + + + + + WREN + WREN + 12 + 1 + + WREN + read-write + + Disabled + Write operations disabled for the bank by the FMC + 0 + + + Enabled + Write operations enabled for the bank by the FMC + 1 + + + + + WAITCFG + WAITCFG + 11 + 1 + + WAITCFG + read-write + + BeforeWaitState + NWAIT signal is active one data cycle before wait state + 0 + + + DuringWaitState + NWAIT signal is active during wait state + 1 + + + + + WAITPOL + WAITPOL + 9 + 1 + + WAITPOL + read-write + + ActiveLow + NWAIT active low + 0 + + + ActiveHigh + NWAIT active high + 1 + + + + + BURSTEN + BURSTEN + 8 + 1 + + BURSTEN + read-write + + Disabled + Burst mode disabled + 0 + + + Enabled + Burst mode enabled + 1 + + + + + FACCEN + FACCEN + 6 + 1 + + FACCEN + read-write + + Disabled + Corresponding NOR Flash memory access is disabled + 0 + + + Enabled + Corresponding NOR Flash memory access is enabled + 1 + + + + + MWID + MWID + 4 + 2 + + MWID + read-write + + Bits8 + Memory data bus width 8 bits + 0 + + + Bits16 + Memory data bus width 16 bits + 1 + + + Bits32 + Memory data bus width 32 bits + 2 + + + + + MTYP + MTYP + 2 + 2 + + MTYP + read-write + + SRAM + SRAM memory type + 0 + + + PSRAM + PSRAM (CRAM) memory type + 1 + + + Flash + NOR Flash/OneNAND Flash + 2 + + + + + MUXEN + MUXEN + 1 + 1 + + MUXEN + read-write + + Disabled + Address/Data non-multiplexed + 0 + + + Enabled + Address/Data multiplexed on databus + 1 + + + + + MBKEN + MBKEN + 0 + 1 + + MBKEN + read-write + + Disabled + Corresponding memory bank is disabled + 0 + + + Enabled + Corresponding memory bank is enabled + 1 + + + + + WRAPMOD + WRAPMOD + 10 + 1 + + + CPSIZE + CRAM page size + 16 + 3 + read-write + + CPSIZE + read-write + + NoBurstSplit + No burst split when crossing page boundary + 0 + + + Bytes128 + 128 bytes CRAM page size + 1 + + + Bytes256 + 256 bytes CRAM page size + 2 + + + Bytes512 + 512 bytes CRAM page size + 3 + + + Bytes1024 + 1024 bytes CRAM page size + 4 + + + + + + + 4 + 0x8 + 1-4 + BTR%s + BTR1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + ACCMOD + read-write + + A + Access mode A + 0 + + + B + Access mode B + 1 + + + C + Access mode C + 2 + + + D + Access mode D + 3 + + + + + DATLAT + DATLAT + 24 + 4 + + + 0 + 15 + + + + + CLKDIV + CLKDIV + 20 + 4 + + + 1 + 15 + + + + + BUSTURN + BUSTURN + 16 + 4 + + + 0 + 15 + + + + + DATAST + DATAST + 8 + 8 + + + 1 + 255 + + + + + ADDHLD + ADDHLD + 4 + 4 + + + 1 + 15 + + + + + ADDSET + ADDSET + 0 + 4 + + + 0 + 15 + + + + + + + 3 + 0x8 + 2-4 + BCR%s + BCR2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + CBURSTRW + read-write + + Disabled + Write operations are always performed in asynchronous mode + 0 + + + Enabled + Write operations are performed in synchronous mode + 1 + + + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + ASYNCWAIT + read-write + + Disabled + Wait signal not used in asynchronous mode + 0 + + + Enabled + Wait signal used even in asynchronous mode + 1 + + + + + EXTMOD + EXTMOD + 14 + 1 + + EXTMOD + read-write + + Disabled + Values inside the FMC_BWTR are not taken into account + 0 + + + Enabled + Values inside the FMC_BWTR are taken into account + 1 + + + + + WAITEN + WAITEN + 13 + 1 + + WAITEN + read-write + + Disabled + Values inside the FMC_BWTR are taken into account + 0 + + + Enabled + NWAIT signal enabled + 1 + + + + + WREN + WREN + 12 + 1 + + WREN + read-write + + Disabled + Write operations disabled for the bank by the FMC + 0 + + + Enabled + Write operations enabled for the bank by the FMC + 1 + + + + + WAITCFG + WAITCFG + 11 + 1 + + WAITCFG + read-write + + BeforeWaitState + NWAIT signal is active one data cycle before wait state + 0 + + + DuringWaitState + NWAIT signal is active during wait state + 1 + + + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + WAITPOL + read-write + + ActiveLow + NWAIT active low + 0 + + + ActiveHigh + NWAIT active high + 1 + + + + + BURSTEN + BURSTEN + 8 + 1 + + BURSTEN + read-write + + Disabled + Burst mode disabled + 0 + + + Enabled + Burst mode enabled + 1 + + + + + FACCEN + FACCEN + 6 + 1 + + FACCEN + read-write + + Disabled + Corresponding NOR Flash memory access is disabled + 0 + + + Enabled + Corresponding NOR Flash memory access is enabled + 1 + + + + + MWID + MWID + 4 + 2 + + MWID + read-write + + Bits8 + Memory data bus width 8 bits + 0 + + + Bits16 + Memory data bus width 16 bits + 1 + + + Bits32 + Memory data bus width 32 bits + 2 + + + + + MTYP + MTYP + 2 + 2 + + MTYP + read-write + + SRAM + SRAM memory type + 0 + + + PSRAM + PSRAM (CRAM) memory type + 1 + + + Flash + NOR Flash/OneNAND Flash + 2 + + + + + MUXEN + MUXEN + 1 + 1 + + MUXEN + read-write + + Disabled + Address/Data non-multiplexed + 0 + + + Enabled + Address/Data multiplexed on databus + 1 + + + + + MBKEN + MBKEN + 0 + 1 + + MBKEN + read-write + + Disabled + Corresponding memory bank is disabled + 0 + + + Enabled + Corresponding memory bank is enabled + 1 + + + + + CPSIZE + CRAM page size + 16 + 3 + read-write + + CPSIZE + read-write + + NoBurstSplit + No burst split when crossing page boundary + 0 + + + Bytes128 + 128 bytes CRAM page size + 1 + + + Bytes256 + 256 bytes CRAM page size + 2 + + + Bytes512 + 512 bytes CRAM page size + 3 + + + Bytes1024 + 1024 bytes CRAM page size + 4 + + + + + + + 3 + 0x20 + 2-4 + PCR%s + PCR2 + PC Card/NAND Flash control register + 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + ECCPS + read-write + + Bytes256 + ECC page size 256 bytes + 0 + + + Bytes512 + ECC page size 512 bytes + 1 + + + Bytes1024 + ECC page size 1024 bytes + 2 + + + Bytes2048 + ECC page size 2048 bytes + 3 + + + Bytes4096 + ECC page size 4096 bytes + 4 + + + Bytes8192 + ECC page size 8192 bytes + 5 + + + + + TAR + TAR + 13 + 4 + + + 0 + 15 + + + + + TCLR + TCLR + 9 + 4 + + + 0 + 15 + + + + + ECCEN + ECCEN + 6 + 1 + + ECCEN + read-write + + Disabled + ECC logic is disabled and reset + 0 + + + Enabled + ECC logic is enabled + 1 + + + + + PWID + PWID + 4 + 2 + + PWID + read-write + + Bits8 + External memory device width 8 bits + 0 + + + Bits16 + External memory device width 16 bits + 1 + + + + + PTYP + PTYP + 3 + 1 + + PTYP + read-write + + NANDFlash + NAND Flash + 1 + + + + + PBKEN + PBKEN + 2 + 1 + + PBKEN + read-write + + Disabled + Corresponding memory bank is disabled + 0 + + + Enabled + Corresponding memory bank is enabled + 1 + + + + + PWAITEN + PWAITEN + 1 + 1 + + PWAITEN + read-write + + Disabled + Wait feature disabled + 0 + + + Enabled + Wait feature enabled + 1 + + + + + + + 3 + 0x20 + 2-4 + SR%s + SR2 + FIFO status and interrupt register + 2 + 0x64 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + FEMPT + read + + NotEmpty + FIFO not empty + 0 + + + Empty + FIFO empty + 1 + + + + + IFEN + IFEN + 5 + 1 + read-write + + IFEN + read-write + + Disabled + Interrupt falling edge detection request disabled + 0 + + + Enabled + Interrupt falling edge detection request enabled + 1 + + + + + ILEN + ILEN + 4 + 1 + read-write + + ILEN + read-write + + Disabled + Interrupt high-level detection request disabled + 0 + + + Enabled + Interrupt high-level detection request enabled + 1 + + + + + IREN + IREN + 3 + 1 + read-write + + IREN + read-write + + Disabled + Interrupt rising edge detection request disabled + 0 + + + Enabled + Interrupt rising edge detection request enabled + 1 + + + + + IFS + IFS + 2 + 1 + read-write + + IFS + read-write + + DidNotOccur + Interrupt falling edge did not occur + 0 + + + Occurred + Interrupt falling edge occurred + 1 + + + + + ILS + ILS + 1 + 1 + read-write + + ILS + read-write + + DidNotOccur + Interrupt high-level did not occur + 0 + + + Occurred + Interrupt high-level occurred + 1 + + + + + IRS + IRS + 0 + 1 + read-write + + IRS + read-write + + DidNotOccur + Interrupt rising edge did not occur + 0 + + + Occurred + Interrupt rising edge occurred + 1 + + + + + + + PMEM2 + PMEM2 + Common memory space timing register + 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZ + MEMHIZx + 24 + 8 + + + 0 + 254 + + + + + MEMHOLD + MEMHOLDx + 16 + 8 + + + 1 + 254 + + + + + MEMWAIT + MEMWAITx + 8 + 8 + + + 1 + 254 + + + + + MEMSET + MEMSETx + 0 + 8 + + + 0 + 254 + + + + + + + PATT2 + PATT2 + Attribute memory space timing register + 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZ + ATTHIZx + 24 + 8 + + + 0 + 254 + + + + + ATTHOLD + ATTHOLDx + 16 + 8 + + + 1 + 254 + + + + + ATTWAIT + ATTWAITx + 8 + 8 + + + 1 + 254 + + + + + ATTSET + ATTSETx + 0 + 8 + + + 0 + 254 + + + + + + + ECCR2 + ECCR2 + ECC result register 2 + 0x74 + 0x20 + read-only + 0x00000000 + + + ECC + ECCx + 0 + 32 + + + 0 + 4294967295 + + + + + + + PMEM3 + PMEM3 + Common memory space timing register + 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZ + MEMHIZx + 24 + 8 + + + 0 + 254 + + + + + MEMHOLD + MEMHOLDx + 16 + 8 + + + 1 + 254 + + + + + MEMWAIT + MEMWAITx + 8 + 8 + + + 1 + 254 + + + + + MEMSET + MEMSETx + 0 + 8 + + + 0 + 254 + + + + + + + PATT3 + PATT3 + Attribute memory space timing register + 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZ + ATTHIZx + 24 + 8 + + + 0 + 254 + + + + + ATTHOLD + ATTHOLDx + 16 + 8 + + + 1 + 254 + + + + + ATTWAIT + ATTWAITx + 8 + 8 + + + 1 + 254 + + + + + ATTSET + ATTSETx + 0 + 8 + + + 0 + 254 + + + + + + + ECCR3 + ECCR3 + ECC result register 3 + 0x94 + 0x20 + read-only + 0x00000000 + + + ECC + ECCx + 0 + 32 + + + 0 + 4294967295 + + + + + + + PMEM4 + PMEM4 + Common memory space timing register + 4 + 0xA8 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZ + MEMHIZx + 24 + 8 + + + 0 + 254 + + + + + MEMHOLD + MEMHOLDx + 16 + 8 + + + 1 + 254 + + + + + MEMWAIT + MEMWAITx + 8 + 8 + + + 1 + 254 + + + + + MEMSET + MEMSETx + 0 + 8 + + + 0 + 254 + + + + + + + PATT4 + PATT4 + Attribute memory space timing register + 4 + 0xAC + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZ + ATTHIZx + 24 + 8 + + + 0 + 254 + + + + + ATTHOLD + ATTHOLDx + 16 + 8 + + + 1 + 254 + + + + + ATTWAIT + ATTWAITx + 8 + 8 + + + 1 + 254 + + + + + ATTSET + ATTSETx + 0 + 8 + + + 0 + 254 + + + + + + + PIO4 + PIO4 + I/O space timing register 4 + 0xB0 + 0x20 + read-write + 0xFCFCFCFC + + + IOHIZx + IOHIZx + 24 + 8 + + + IOHOLDx + IOHOLDx + 16 + 8 + + + IOWAITx + IOWAITx + 8 + 8 + + + IOSETx + IOSETx + 0 + 8 + + + + + 4 + 0x8 + 1-4 + BWTR%s + BWTR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + ACCMOD + read-write + + A + Access mode A + 0 + + + B + Access mode B + 1 + + + C + Access mode C + 2 + + + D + Access mode D + 3 + + + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + 1 + 255 + + + + + ADDHLD + ADDHLD + 4 + 4 + + + 1 + 15 + + + + + ADDSET + ADDSET + 0 + 4 + + + 0 + 15 + + + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + read-write + + + 0 + 15 + + + + + + + + + DBGMCU + Debug support + DBG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + IDCODE + 0x0 + 0x20 + read-only + 0x10006411 + + + DEV_ID + DEV_ID + 0 + 12 + + + REV_ID + REV_ID + 16 + 16 + + + + + CR + CR + Control Register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBG_SLEEP + DBG_SLEEP + 0 + 1 + + + DBG_STOP + DBG_STOP + 1 + 1 + + + DBG_STANDBY + DBG_STANDBY + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT + 16 + 1 + + + DBG_TIM8_STOP + DBG_TIM8_STOP + 17 + 1 + + + DBG_TIM5_STOP + DBG_TIM5_STOP + 18 + 1 + + + DBG_TIM6_STOP + DBG_TIM6_STOP + 19 + 1 + + + DBG_TIM7_STOP + DBG_TIM7_STOP + 20 + 1 + + + + + APB1_FZ + APB1_FZ + Debug MCU APB1 Freeze registe + 0x8 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2_STOP + DBG_TIM2_STOP + 0 + 1 + + + DBG_TIM3_STOP + DBG_TIM3 _STOP + 1 + 1 + + + DBG_TIM4_STOP + DBG_TIM4_STOP + 2 + 1 + + + DBG_TIM5_STOP + DBG_TIM5_STOP + 3 + 1 + + + DBG_TIM6_STOP + DBG_TIM6_STOP + 4 + 1 + + + DBG_TIM7_STOP + DBG_TIM7_STOP + 5 + 1 + + + DBG_TIM12_STOP + DBG_TIM12_STOP + 6 + 1 + + + DBG_TIM13_STOP + DBG_TIM13_STOP + 7 + 1 + + + DBG_TIM14_STOP + DBG_TIM14_STOP + 8 + 1 + + + DBG_WWDG_STOP + DBG_WWDG_STOP + 11 + 1 + + + DBG_IWDG_STOP + DBG_IWDEG_STOP + 12 + 1 + + + DBG_J2C1_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT + 21 + 1 + + + DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT + 22 + 1 + + + DBG_J2C3SMBUS_TIMEOUT + DBG_J2C3SMBUS_TIMEOUT + 23 + 1 + + + DBG_CAN1_STOP + DBG_CAN1_STOP + 25 + 1 + + + DBG_CAN2_STOP + DBG_CAN2_STOP + 26 + 1 + + + + + APB2_FZ + APB2_FZ + Debug MCU APB2 Freeze registe + 0xC + 0x20 + read-write + 0x00000000 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is + halted + 0 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is + halted + 1 + 1 + + + DBG_TIM9_STOP + TIM9 counter stopped when core is + halted + 16 + 1 + + + DBG_TIM10_STOP + TIM10 counter stopped when core is + halted + 17 + 1 + + + DBG_TIM11_STOP + TIM11 counter stopped when core is + halted + 18 + 1 + + + + + + + DMA2 + DMA controller + DMA + 0x40026400 + + 0x0 + 0x400 + registers + + + DMA2_Stream0 + DMA2 Stream0 global interrupt + 56 + + + DMA2_Stream1 + DMA2 Stream1 global interrupt + 57 + + + DMA2_Stream2 + DMA2 Stream2 global interrupt + 58 + + + DMA2_Stream3 + DMA2 Stream3 global interrupt + 59 + + + DMA2_Stream4 + DMA2 Stream4 global interrupt + 60 + + + DMA2_Stream5 + DMA2 Stream5 global interrupt + 68 + + + DMA2_Stream6 + DMA2 Stream6 global interrupt + 69 + + + DMA2_Stream7 + DMA2 Stream7 global interrupt + 70 + + + + LISR + LISR + low interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TCIF3 + Stream x transfer complete interrupt + flag (x = 3..0) + 27 + 1 + + + + HTIF3 + Stream x half transfer interrupt flag + (x=3..0) + 26 + 1 + + + + TEIF3 + Stream x transfer error interrupt flag + (x=3..0) + 25 + 1 + + + + DMEIF3 + Stream x direct mode error interrupt + flag (x=3..0) + 24 + 1 + + + + FEIF3 + Stream x FIFO error interrupt flag + (x=3..0) + 22 + 1 + + + + TCIF2 + Stream x transfer complete interrupt + flag (x = 3..0) + 21 + 1 + + + + HTIF2 + Stream x half transfer interrupt flag + (x=3..0) + 20 + 1 + + + + TEIF2 + Stream x transfer error interrupt flag + (x=3..0) + 19 + 1 + + + + DMEIF2 + Stream x direct mode error interrupt + flag (x=3..0) + 18 + 1 + + + + FEIF2 + Stream x FIFO error interrupt flag + (x=3..0) + 16 + 1 + + + + TCIF1 + Stream x transfer complete interrupt + flag (x = 3..0) + 11 + 1 + + + + HTIF1 + Stream x half transfer interrupt flag + (x=3..0) + 10 + 1 + + + + TEIF1 + Stream x transfer error interrupt flag + (x=3..0) + 9 + 1 + + + + DMEIF1 + Stream x direct mode error interrupt + flag (x=3..0) + 8 + 1 + + + + FEIF1 + Stream x FIFO error interrupt flag + (x=3..0) + 6 + 1 + + + + TCIF0 + Stream x transfer complete interrupt + flag (x = 3..0) + 5 + 1 + + TCIF0 + read + + NotComplete + No transfer complete event on stream x + 0 + + + Complete + A transfer complete event occurred on stream x + 1 + + + + + HTIF0 + Stream x half transfer interrupt flag + (x=3..0) + 4 + 1 + + HTIF0 + read + + NotHalf + No half transfer event on stream x + 0 + + + Half + A half transfer event occurred on stream x + 1 + + + + + TEIF0 + Stream x transfer error interrupt flag + (x=3..0) + 3 + 1 + + TEIF0 + read + + NoError + No transfer error on stream x + 0 + + + Error + A transfer error occurred on stream x + 1 + + + + + DMEIF0 + Stream x direct mode error interrupt + flag (x=3..0) + 2 + 1 + + DMEIF0 + read + + NoError + No Direct Mode error on stream x + 0 + + + Error + A Direct Mode error occurred on stream x + 1 + + + + + FEIF0 + Stream x FIFO error interrupt flag + (x=3..0) + 0 + 1 + + FEIF0 + read + + NoError + No FIFO error event on stream x + 0 + + + Error + A FIFO error event occurred on stream x + 1 + + + + + + + HISR + HISR + high interrupt status register + 0x4 + 0x20 + read-only + 0x00000000 + + + TCIF7 + Stream x transfer complete interrupt + flag (x=7..4) + 27 + 1 + + + + HTIF7 + Stream x half transfer interrupt flag + (x=7..4) + 26 + 1 + + + + TEIF7 + Stream x transfer error interrupt flag + (x=7..4) + 25 + 1 + + + + DMEIF7 + Stream x direct mode error interrupt + flag (x=7..4) + 24 + 1 + + + + FEIF7 + Stream x FIFO error interrupt flag + (x=7..4) + 22 + 1 + + + + TCIF6 + Stream x transfer complete interrupt + flag (x=7..4) + 21 + 1 + + + + HTIF6 + Stream x half transfer interrupt flag + (x=7..4) + 20 + 1 + + + + TEIF6 + Stream x transfer error interrupt flag + (x=7..4) + 19 + 1 + + + + DMEIF6 + Stream x direct mode error interrupt + flag (x=7..4) + 18 + 1 + + + + FEIF6 + Stream x FIFO error interrupt flag + (x=7..4) + 16 + 1 + + + + TCIF5 + Stream x transfer complete interrupt + flag (x=7..4) + 11 + 1 + + + + HTIF5 + Stream x half transfer interrupt flag + (x=7..4) + 10 + 1 + + + + TEIF5 + Stream x transfer error interrupt flag + (x=7..4) + 9 + 1 + + + + DMEIF5 + Stream x direct mode error interrupt + flag (x=7..4) + 8 + 1 + + + + FEIF5 + Stream x FIFO error interrupt flag + (x=7..4) + 6 + 1 + + + + TCIF4 + Stream x transfer complete interrupt + flag (x=7..4) + 5 + 1 + + TCIF4 + read + + NotComplete + No transfer complete event on stream x + 0 + + + Complete + A transfer complete event occurred on stream x + 1 + + + + + HTIF4 + Stream x half transfer interrupt flag + (x=7..4) + 4 + 1 + + HTIF4 + read + + NotHalf + No half transfer event on stream x + 0 + + + Half + A half transfer event occurred on stream x + 1 + + + + + TEIF4 + Stream x transfer error interrupt flag + (x=7..4) + 3 + 1 + + TEIF4 + read + + NoError + No transfer error on stream x + 0 + + + Error + A transfer error occurred on stream x + 1 + + + + + DMEIF4 + Stream x direct mode error interrupt + flag (x=7..4) + 2 + 1 + + DMEIF4 + read + + NoError + No Direct Mode error on stream x + 0 + + + Error + A Direct Mode error occurred on stream x + 1 + + + + + FEIF4 + Stream x FIFO error interrupt flag + (x=7..4) + 0 + 1 + + FEIF4 + read + + NoError + No FIFO error event on stream x + 0 + + + Error + A FIFO error event occurred on stream x + 1 + + + + + + + LIFCR + LIFCR + low interrupt flag clear + register + 0x8 + 0x20 + write-only + 0x00000000 + + + CTCIF3 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 27 + 1 + + + + CHTIF3 + Stream x clear half transfer interrupt + flag (x = 3..0) + 26 + 1 + + + + CTEIF3 + Stream x clear transfer error interrupt + flag (x = 3..0) + 25 + 1 + + + + CDMEIF3 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 24 + 1 + + + + CFEIF3 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 22 + 1 + + + + CTCIF2 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 21 + 1 + + + + CHTIF2 + Stream x clear half transfer interrupt + flag (x = 3..0) + 20 + 1 + + + + CTEIF2 + Stream x clear transfer error interrupt + flag (x = 3..0) + 19 + 1 + + + + CDMEIF2 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 18 + 1 + + + + CFEIF2 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 16 + 1 + + + + CTCIF1 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 11 + 1 + + + + CHTIF1 + Stream x clear half transfer interrupt + flag (x = 3..0) + 10 + 1 + + + + CTEIF1 + Stream x clear transfer error interrupt + flag (x = 3..0) + 9 + 1 + + + + CDMEIF1 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 8 + 1 + + + + CFEIF1 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 6 + 1 + + + + CTCIF0 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 5 + 1 + + CTCIF0 + write + + Clear + Clear the corresponding TCIFx flag + 1 + + + + + CHTIF0 + Stream x clear half transfer interrupt + flag (x = 3..0) + 4 + 1 + + CHTIF0 + write + + Clear + Clear the corresponding HTIFx flag + 1 + + + + + CTEIF0 + Stream x clear transfer error interrupt + flag (x = 3..0) + 3 + 1 + + CTEIF0 + write + + Clear + Clear the corresponding TEIFx flag + 1 + + + + + CDMEIF0 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 2 + 1 + + CDMEIF0 + write + + Clear + Clear the corresponding DMEIFx flag + 1 + + + + + CFEIF0 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 0 + 1 + + CFEIF0 + write + + Clear + Clear the corresponding CFEIFx flag + 1 + + + + + + + HIFCR + HIFCR + high interrupt flag clear + register + 0xC + 0x20 + write-only + 0x00000000 + + + CTCIF7 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 27 + 1 + + + + CHTIF7 + Stream x clear half transfer interrupt + flag (x = 7..4) + 26 + 1 + + + + CTEIF7 + Stream x clear transfer error interrupt + flag (x = 7..4) + 25 + 1 + + + + CDMEIF7 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 24 + 1 + + + + CFEIF7 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 22 + 1 + + + + CTCIF6 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 21 + 1 + + + + CHTIF6 + Stream x clear half transfer interrupt + flag (x = 7..4) + 20 + 1 + + + + CTEIF6 + Stream x clear transfer error interrupt + flag (x = 7..4) + 19 + 1 + + + + CDMEIF6 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 18 + 1 + + + + CFEIF6 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 16 + 1 + + + + CTCIF5 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 11 + 1 + + + + CHTIF5 + Stream x clear half transfer interrupt + flag (x = 7..4) + 10 + 1 + + + + CTEIF5 + Stream x clear transfer error interrupt + flag (x = 7..4) + 9 + 1 + + + + CDMEIF5 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 8 + 1 + + + + CFEIF5 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 6 + 1 + + + + CTCIF4 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 5 + 1 + + CTCIF4 + write + + Clear + Clear the corresponding TCIFx flag + 1 + + + + + CHTIF4 + Stream x clear half transfer interrupt + flag (x = 7..4) + 4 + 1 + + CHTIF4 + write + + Clear + Clear the corresponding HTIFx flag + 1 + + + + + CTEIF4 + Stream x clear transfer error interrupt + flag (x = 7..4) + 3 + 1 + + CTEIF4 + write + + Clear + Clear the corresponding TEIFx flag + 1 + + + + + CDMEIF4 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 2 + 1 + + CDMEIF4 + write + + Clear + Clear the corresponding DMEIFx flag + 1 + + + + + CFEIF4 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 0 + 1 + + CFEIF4 + write + + Clear + Clear the corresponding CFEIFx flag + 1 + + + + + + + 8 + 0x18 + 0-7 + ST%s + Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers + 0x10 + + CR + S0CR + stream x configuration + register + 0x0 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + 0 + 7 + + + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + PBURST + read-write + + Single + Single transfer + 0 + + + INCR4 + Incremental burst of 4 beats + 1 + + + INCR8 + Incremental burst of 8 beats + 2 + + + INCR16 + Incremental burst of 16 beats + 3 + + + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + CT + read-write + + Memory0 + The current target memory is Memory 0 + 0 + + + Memory1 + The current target memory is Memory 1 + 1 + + + + + DBM + Double buffer mode + 18 + 1 + + DBM + read-write + + Disabled + No buffer switching at the end of transfer + 0 + + + Enabled + Memory target switched at the end of the DMA transfer + 1 + + + + + PL + Priority level + 16 + 2 + + PL + read-write + + Low + Low + 0 + + + Medium + Medium + 1 + + + High + High + 2 + + + VeryHigh + Very high + 3 + + + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + PINCOS + read-write + + PSIZE + The offset size for the peripheral address calculation is linked to the PSIZE + 0 + + + Fixed4 + The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) + 1 + + + + + MSIZE + Memory data size + 13 + 2 + + + + PSIZE + Peripheral data size + 11 + 2 + + PSIZE + read-write + + Bits8 + Byte (8-bit) + 0 + + + Bits16 + Half-word (16-bit) + 1 + + + Bits32 + Word (32-bit) + 2 + + + + + MINC + Memory increment mode + 10 + 1 + + + + PINC + Peripheral increment mode + 9 + 1 + + PINC + read-write + + Fixed + Address pointer is fixed + 0 + + + Incremented + Address pointer is incremented after each data transfer + 1 + + + + + CIRC + Circular mode + 8 + 1 + + CIRC + read-write + + Disabled + Circular mode disabled + 0 + + + Enabled + Circular mode enabled + 1 + + + + + DIR + Data transfer direction + 6 + 2 + + DIR + read-write + + PeripheralToMemory + Peripheral-to-memory + 0 + + + MemoryToPeripheral + Memory-to-peripheral + 1 + + + MemoryToMemory + Memory-to-memory + 2 + + + + + PFCTRL + Peripheral flow controller + 5 + 1 + + PFCTRL + read-write + + DMA + The DMA is the flow controller + 0 + + + Peripheral + The peripheral is the flow controller + 1 + + + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + TCIE + read-write + + Disabled + TC interrupt disabled + 0 + + + Enabled + TC interrupt enabled + 1 + + + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + HTIE + read-write + + Disabled + HT interrupt disabled + 0 + + + Enabled + HT interrupt enabled + 1 + + + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + TEIE + read-write + + Disabled + TE interrupt disabled + 0 + + + Enabled + TE interrupt enabled + 1 + + + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + DMEIE + read-write + + Disabled + DME interrupt disabled + 0 + + + Enabled + DME interrupt enabled + 1 + + + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + EN + read-write + + Disabled + Stream disabled + 0 + + + Enabled + Stream enabled + 1 + + + + + + + NDTR + S0NDTR + stream x number of data + register + 0x4 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + 0 + 65535 + + + + + + + PAR + S0PAR + stream x peripheral address + register + 0x8 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + M0AR + S0M0AR + stream x memory 0 address + register + 0xC + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + M1AR + S0M1AR + stream x memory 1 address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + FCR + S0FCR + stream x FIFO control register + 0x14 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + FEIE + read-write + + Disabled + FE interrupt disabled + 0 + + + Enabled + FE interrupt enabled + 1 + + + + + FS + FIFO status + 3 + 3 + read-only + + FS + read + + Quarter1 + 0 < fifo_level < 1/4 + 0 + + + Quarter2 + 1/4 <= fifo_level < 1/2 + 1 + + + Quarter3 + 1/2 <= fifo_level < 3/4 + 2 + + + Quarter4 + 3/4 <= fifo_level < full + 3 + + + Empty + FIFO is empty + 4 + + + Full + FIFO is full + 5 + + + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + DMDIS + read-write + + Enabled + Direct mode is enabled + 0 + + + Disabled + Direct mode is disabled + 1 + + + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + FTH + read-write + + Quarter + 1/4 full FIFO + 0 + + + Half + 1/2 full FIFO + 1 + + + ThreeQuarters + 3/4 full FIFO + 2 + + + Full + Full FIFO + 3 + + + + + + + + + + DMA1 + 0x40026000 + + DMA1_Stream0 + DMA1 Stream0 global interrupt + 11 + + + DMA1_Stream1 + DMA1 Stream1 global interrupt + 12 + + + DMA1_Stream2 + DMA1 Stream2 global interrupt + 13 + + + DMA1_Stream3 + DMA1 Stream3 global interrupt + 14 + + + DMA1_Stream4 + DMA1 Stream4 global interrupt + 15 + + + DMA1_Stream5 + DMA1 Stream5 global interrupt + 16 + + + DMA1_Stream6 + DMA1 Stream6 global interrupt + 17 + + + DMA1_Stream7 + DMA1 Stream7 global interrupt + 47 + + + + RCC + Reset and clock control + RCC + 0x40023800 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + clock control register + 0x0 + 0x20 + 0x00000083 + + + PLLI2SRDY + PLLI2S clock ready flag + 27 + 1 + read-only + + + + PLLI2SON + PLLI2S enable + 26 + 1 + read-write + + + + PLLRDY + Main PLL (PLL) clock ready + flag + 25 + 1 + read-only + + + + PLLON + Main PLL (PLL) enable + 24 + 1 + read-write + + + + CSSON + Clock security system + enable + 19 + 1 + read-write + + CSSON + read-write + + Off + Clock security system disabled (clock detector OFF) + 0 + + + On + Clock security system enable (clock detector ON if the HSE is ready, OFF if not) + 1 + + + + + HSEBYP + HSE clock bypass + 18 + 1 + read-write + + HSEBYP + read-write + + NotBypassed + HSE crystal oscillator not bypassed + 0 + + + Bypassed + HSE crystal oscillator bypassed with external clock + 1 + + + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + + HSEON + HSE clock enable + 16 + 1 + read-write + + + + HSICAL + Internal high-speed clock + calibration + 8 + 8 + read-only + + + 0 + 255 + + + + + HSITRIM + Internal high-speed clock + trimming + 3 + 5 + read-write + + + 0 + 31 + + + + + HSIRDY + Internal high-speed clock ready + flag + 1 + 1 + read-only + + HSIRDYR + read + + NotReady + Clock not ready + 0 + + + Ready + Clock ready + 1 + + + + + HSION + Internal high-speed clock + enable + 0 + 1 + read-write + + HSION + read-write + + Off + Clock Off + 0 + + + On + Clock On + 1 + + + + + + + PLLCFGR + PLLCFGR + PLL configuration register + 0x4 + 0x20 + read-write + 0x24003010 + + + PLLSRC + Main PLL(PLL) and audio PLL (PLLI2S) + entry clock source + 22 + 1 + + PLLSRC + read-write + + HSI + HSI clock selected as PLL and PLLI2S clock entry + 0 + + + HSE + HSE oscillator clock selected as PLL and PLLI2S clock entry + 1 + + + + + PLLM + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 0 + 6 + + + 2 + 63 + + + + + PLLN + Main PLL (PLL) multiplication factor for + VCO + 6 + 9 + + + 50 + 432 + + + + + PLLP + Main PLL (PLL) division factor for main + system clock + 16 + 2 + + PLLP + read-write + + Div2 + PLLP=2 + 0 + + + Div4 + PLLP=4 + 1 + + + Div6 + PLLP=6 + 2 + + + Div8 + PLLP=8 + 3 + + + + + PLLQ + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 24 + 4 + + + 2 + 15 + + + + + + + CFGR + CFGR + clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCO2 + Microcontroller clock output + 2 + 30 + 2 + read-write + + MCO2 + read-write + + SYSCLK + System clock (SYSCLK) selected + 0 + + + PLLI2S + PLLI2S clock selected + 1 + + + HSE + HSE oscillator clock selected + 2 + + + PLL + PLL clock selected + 3 + + + + + MCO2PRE + MCO2 prescaler + 27 + 3 + read-write + + + + MCO1PRE + MCO1 prescaler + 24 + 3 + read-write + + MCO1PRE + read-write + + Div1 + No division + 0 + + + Div2 + Division by 2 + 4 + + + Div3 + Division by 3 + 5 + + + Div4 + Division by 4 + 6 + + + Div5 + Division by 5 + 7 + + + + + I2SSRC + I2S clock selection + 23 + 1 + read-write + + I2SSRC + read-write + + PLLI2S + PLLI2S clock used as I2S clock source + 0 + + + CKIN + External clock mapped on the I2S_CKIN pin used as I2S clock source + 1 + + + + + MCO1 + Microcontroller clock output + 1 + 21 + 2 + read-write + + MCO1 + read-write + + HSI + HSI clock selected + 0 + + + LSE + LSE oscillator selected + 1 + + + HSE + HSE oscillator clock selected + 2 + + + PLL + PLL clock selected + 3 + + + + + RTCPRE + HSE division factor for RTC + clock + 16 + 5 + read-write + + + 0 + 31 + + + + + PPRE2 + APB high-speed prescaler + (APB2) + 13 + 3 + read-write + + + + PPRE1 + APB Low speed prescaler + (APB1) + 10 + 3 + read-write + + PPRE1 + read-write + + Div1 + HCLK not divided + 0 + + + Div2 + HCLK divided by 2 + 4 + + + Div4 + HCLK divided by 4 + 5 + + + Div8 + HCLK divided by 8 + 6 + + + Div16 + HCLK divided by 16 + 7 + + + + + HPRE + AHB prescaler + 4 + 4 + read-write + + HPRE + read-write + + Div1 + SYSCLK not divided + 0 + + + Div2 + SYSCLK divided by 2 + 8 + + + Div4 + SYSCLK divided by 4 + 9 + + + Div8 + SYSCLK divided by 8 + 10 + + + Div16 + SYSCLK divided by 16 + 11 + + + Div64 + SYSCLK divided by 64 + 12 + + + Div128 + SYSCLK divided by 128 + 13 + + + Div256 + SYSCLK divided by 256 + 14 + + + Div512 + SYSCLK divided by 512 + 15 + + + + + SW + System clock switch + 0 + 2 + + SW + read-write + + HSI + HSI selected as system clock + 0 + + + HSE + HSE selected as system clock + 1 + + + PLL + PLL selected as system clock + 2 + + + + + SWS + System clock switch status + 2 + 2 + + SWSR + read + + HSI + HSI oscillator used as system clock + 0 + + + HSE + HSE oscillator used as system clock + 1 + + + PLL + PLL used as system clock + 2 + + + + + + + CIR + CIR + clock interrupt register + 0xC + 0x20 + 0x00000000 + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + CSSCW + write + + Clear + Clear CSSF flag + 1 + + + + + PLLI2SRDYC + PLLI2S ready interrupt + clear + 21 + 1 + write-only + + + + PLLRDYC + Main PLL(PLL) ready interrupt + clear + 20 + 1 + write-only + + + + HSERDYC + HSE ready interrupt clear + 19 + 1 + write-only + + + + HSIRDYC + HSI ready interrupt clear + 18 + 1 + write-only + + + + LSERDYC + LSE ready interrupt clear + 17 + 1 + write-only + + + + LSIRDYC + LSI ready interrupt clear + 16 + 1 + write-only + + LSIRDYCW + write + + Clear + Clear interrupt flag + 1 + + + + + PLLI2SRDYIE + PLLI2S ready interrupt + enable + 13 + 1 + read-write + + + + PLLRDYIE + Main PLL (PLL) ready interrupt + enable + 12 + 1 + read-write + + + + HSERDYIE + HSE ready interrupt enable + 11 + 1 + read-write + + + + HSIRDYIE + HSI ready interrupt enable + 10 + 1 + read-write + + + + LSERDYIE + LSE ready interrupt enable + 9 + 1 + read-write + + + + LSIRDYIE + LSI ready interrupt enable + 8 + 1 + read-write + + LSIRDYIE + read-write + + Disabled + Interrupt disabled + 0 + + + Enabled + Interrupt enabled + 1 + + + + + CSSF + Clock security system interrupt + flag + 7 + 1 + read-only + + CSSFR + read + + NotInterrupted + No clock security interrupt caused by HSE clock failure + 0 + + + Interrupted + Clock security interrupt caused by HSE clock failure + 1 + + + + + PLLI2SRDYF + PLLI2S ready interrupt + flag + 5 + 1 + read-only + + + + PLLRDYF + Main PLL (PLL) ready interrupt + flag + 4 + 1 + read-only + + + + HSERDYF + HSE ready interrupt flag + 3 + 1 + read-only + + + + HSIRDYF + HSI ready interrupt flag + 2 + 1 + read-only + + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + read-only + + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + read-only + + LSIRDYFR + read + + NotInterrupted + No clock ready interrupt + 0 + + + Interrupted + Clock ready interrupt + 1 + + + + + + + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x10 + 0x20 + read-write + 0x00000000 + + + OTGHSRST + USB OTG HS module reset + 29 + 1 + + + + DMA2RST + DMA2 reset + 22 + 1 + + + + DMA1RST + DMA2 reset + 21 + 1 + + + + CRCRST + CRC reset + 12 + 1 + + + + GPIOIRST + IO port I reset + 8 + 1 + + + + GPIOHRST + IO port H reset + 7 + 1 + + + + GPIOGRST + IO port G reset + 6 + 1 + + + + GPIOFRST + IO port F reset + 5 + 1 + + + + GPIOERST + IO port E reset + 4 + 1 + + + + GPIODRST + IO port D reset + 3 + 1 + + + + GPIOCRST + IO port C reset + 2 + 1 + + + + GPIOBRST + IO port B reset + 1 + 1 + + + + GPIOARST + IO port A reset + 0 + 1 + + GPIOARST + read-write + + Reset + Reset the selected module + 1 + + + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFSRST + USB OTG FS module reset + 7 + 1 + + + + RNGRST + Random number generator module + reset + 6 + 1 + + + + DCMIRST + Camera interface reset + 0 + 1 + + DCMIRST + read-write + + Reset + Reset the selected module + 1 + + + + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x18 + 0x20 + read-write + 0x00000000 + + + FSMCRST + Flexible static memory controller module + reset + 0 + 1 + + FSMCRST + read-write + + Reset + Reset the selected module + 1 + + + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACRST + DAC reset + 29 + 1 + + + + PWRRST + Power interface reset + 28 + 1 + + + + CAN2RST + CAN2 reset + 26 + 1 + + + + CAN1RST + CAN1 reset + 25 + 1 + + + + I2C3RST + I2C3 reset + 23 + 1 + + + + I2C2RST + I2C 2 reset + 22 + 1 + + + + I2C1RST + I2C 1 reset + 21 + 1 + + + + UART5RST + USART 5 reset + 20 + 1 + + + + UART4RST + USART 4 reset + 19 + 1 + + + + USART3RST + USART 3 reset + 18 + 1 + + + + USART2RST + USART 2 reset + 17 + 1 + + + + SPI3RST + SPI 3 reset + 15 + 1 + + + + SPI2RST + SPI 2 reset + 14 + 1 + + + + WWDGRST + Window watchdog reset + 11 + 1 + + + + TIM14RST + TIM14 reset + 8 + 1 + + + + TIM13RST + TIM13 reset + 7 + 1 + + + + TIM12RST + TIM12 reset + 6 + 1 + + + + TIM7RST + TIM7 reset + 5 + 1 + + + + TIM6RST + TIM6 reset + 4 + 1 + + + + TIM5RST + TIM5 reset + 3 + 1 + + + + TIM4RST + TIM4 reset + 2 + 1 + + + + TIM3RST + TIM3 reset + 1 + 1 + + + + TIM2RST + TIM2 reset + 0 + 1 + + TIM2RST + read-write + + Reset + Reset the selected module + 1 + + + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x24 + 0x20 + read-write + 0x00000000 + + + TIM11RST + TIM11 reset + 18 + 1 + + + + TIM10RST + TIM10 reset + 17 + 1 + + + + TIM9RST + TIM9 reset + 16 + 1 + + + + SYSCFGRST + System configuration controller + reset + 14 + 1 + + + + SPI1RST + SPI 1 reset + 12 + 1 + + + + SDIORST + SDIO reset + 11 + 1 + + + + ADCRST + ADC interface reset (common to all + ADCs) + 8 + 1 + + + + USART6RST + USART6 reset + 5 + 1 + + + + USART1RST + USART1 reset + 4 + 1 + + + + TIM8RST + TIM8 reset + 1 + 1 + + + + TIM1RST + TIM1 reset + 0 + 1 + + TIM1RST + read-write + + Reset + Reset the selected module + 1 + + + + + + + AHB1ENR + AHB1ENR + AHB1 peripheral clock register + 0x30 + 0x20 + read-write + 0x00100000 + + + OTGHSULPIEN + USB OTG HSULPI clock + enable + 30 + 1 + + + + OTGHSEN + USB OTG HS clock enable + 29 + 1 + + + + DMA2EN + DMA2 clock enable + 22 + 1 + + + + DMA1EN + DMA1 clock enable + 21 + 1 + + + + BKPSRAMEN + Backup SRAM interface clock + enable + 18 + 1 + + + + CRCEN + CRC clock enable + 12 + 1 + + + + GPIOIEN + IO port I clock enable + 8 + 1 + + + + GPIOHEN + IO port H clock enable + 7 + 1 + + + + GPIOGEN + IO port G clock enable + 6 + 1 + + + + GPIOFEN + IO port F clock enable + 5 + 1 + + + + GPIOEEN + IO port E clock enable + 4 + 1 + + + + GPIODEN + IO port D clock enable + 3 + 1 + + + + GPIOCEN + IO port C clock enable + 2 + 1 + + + + GPIOBEN + IO port B clock enable + 1 + 1 + + + + GPIOAEN + IO port A clock enable + 0 + 1 + + GPIOAEN + read-write + + Disabled + The selected clock is disabled + 0 + + + Enabled + The selected clock is enabled + 1 + + + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable + register + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFSEN + USB OTG FS clock enable + 7 + 1 + + + + RNGEN + Random number generator clock + enable + 6 + 1 + + + + DCMIEN + Camera interface enable + 0 + 1 + + DCMIEN + read-write + + Disabled + The selected clock is disabled + 0 + + + Enabled + The selected clock is enabled + 1 + + + + + + + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + FSMCEN + Flexible static memory controller module + clock enable + 0 + 1 + + FSMCEN + read-write + + Disabled + The selected clock is disabled + 0 + + + Enabled + The selected clock is enabled + 1 + + + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable + register + 0x40 + 0x20 + read-write + 0x00000000 + + + DACEN + DAC interface clock enable + 29 + 1 + + + + PWREN + Power interface clock + enable + 28 + 1 + + + + CAN2EN + CAN 2 clock enable + 26 + 1 + + + + CAN1EN + CAN 1 clock enable + 25 + 1 + + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + + UART5EN + UART5 clock enable + 20 + 1 + + + + UART4EN + UART4 clock enable + 19 + 1 + + + + USART3EN + USART3 clock enable + 18 + 1 + + + + USART2EN + USART 2 clock enable + 17 + 1 + + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + + TIM14EN + TIM14 clock enable + 8 + 1 + + + + TIM13EN + TIM13 clock enable + 7 + 1 + + + + TIM12EN + TIM12 clock enable + 6 + 1 + + + + TIM7EN + TIM7 clock enable + 5 + 1 + + + + TIM6EN + TIM6 clock enable + 4 + 1 + + + + TIM5EN + TIM5 clock enable + 3 + 1 + + + + TIM4EN + TIM4 clock enable + 2 + 1 + + + + TIM3EN + TIM3 clock enable + 1 + 1 + + + + TIM2EN + TIM2 clock enable + 0 + 1 + + TIM2EN + read-write + + Disabled + The selected clock is disabled + 0 + + + Enabled + The selected clock is enabled + 1 + + + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable + register + 0x44 + 0x20 + read-write + 0x00000000 + + + TIM11EN + TIM11 clock enable + 18 + 1 + + + + TIM10EN + TIM10 clock enable + 17 + 1 + + + + TIM9EN + TIM9 clock enable + 16 + 1 + + + + SYSCFGEN + System configuration controller clock + enable + 14 + 1 + + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + + SDIOEN + SDIO clock enable + 11 + 1 + + + + ADC3EN + ADC3 clock enable + 10 + 1 + + + + ADC2EN + ADC2 clock enable + 9 + 1 + + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + + USART6EN + USART6 clock enable + 5 + 1 + + + + USART1EN + USART1 clock enable + 4 + 1 + + + + TIM8EN + TIM8 clock enable + 1 + 1 + + + + TIM1EN + TIM1 clock enable + 0 + 1 + + TIM1EN + read-write + + Disabled + The selected clock is disabled + 0 + + + Enabled + The selected clock is enabled + 1 + + + + + + + AHB1LPENR + AHB1LPENR + AHB1 peripheral clock enable in low power + mode register + 0x50 + 0x20 + read-write + 0x7E6791FF + + + OTGHSULPILPEN + USB OTG HS ULPI clock enable during + Sleep mode + 30 + 1 + + + + OTGHSLPEN + USB OTG HS clock enable during Sleep + mode + 29 + 1 + + + + DMA2LPEN + DMA2 clock enable during Sleep + mode + 22 + 1 + + + + DMA1LPEN + DMA1 clock enable during Sleep + mode + 21 + 1 + + + + BKPSRAMLPEN + Backup SRAM interface clock enable + during Sleep mode + 18 + 1 + + + + SRAM2LPEN + SRAM 2 interface clock enable during + Sleep mode + 17 + 1 + + + + SRAM1LPEN + SRAM 1interface clock enable during + Sleep mode + 16 + 1 + + + + FLITFLPEN + Flash interface clock enable during + Sleep mode + 15 + 1 + + + + CRCLPEN + CRC clock enable during Sleep + mode + 12 + 1 + + + + GPIOILPEN + IO port I clock enable during Sleep + mode + 8 + 1 + + + + GPIOHLPEN + IO port H clock enable during Sleep + mode + 7 + 1 + + + + GPIOGLPEN + IO port G clock enable during Sleep + mode + 6 + 1 + + + + GPIOFLPEN + IO port F clock enable during Sleep + mode + 5 + 1 + + + + GPIOELPEN + IO port E clock enable during Sleep + mode + 4 + 1 + + + + GPIODLPEN + IO port D clock enable during Sleep + mode + 3 + 1 + + + + GPIOCLPEN + IO port C clock enable during Sleep + mode + 2 + 1 + + + + GPIOBLPEN + IO port B clock enable during Sleep + mode + 1 + 1 + + + + GPIOALPEN + IO port A clock enable during sleep + mode + 0 + 1 + + GPIOALPEN + read-write + + DisabledInSleep + Selected module is disabled during Sleep mode + 0 + + + EnabledInSleep + Selected module is enabled during Sleep mode + 1 + + + + + + + AHB2LPENR + AHB2LPENR + AHB2 peripheral clock enable in low power + mode register + 0x54 + 0x20 + read-write + 0x000000F1 + + + OTGFSLPEN + USB OTG FS clock enable during Sleep + mode + 7 + 1 + + + + RNGLPEN + Random number generator clock enable + during Sleep mode + 6 + 1 + + + + DCMILPEN + Camera interface enable during Sleep + mode + 0 + 1 + + DCMILPEN + read-write + + DisabledInSleep + Selected module is disabled during Sleep mode + 0 + + + EnabledInSleep + Selected module is enabled during Sleep mode + 1 + + + + + + + AHB3LPENR + AHB3LPENR + AHB3 peripheral clock enable in low power + mode register + 0x58 + 0x20 + read-write + 0x00000001 + + + FSMCLPEN + Flexible static memory controller module + clock enable during Sleep mode + 0 + 1 + + FSMCLPEN + read-write + + DisabledInSleep + Selected module is disabled during Sleep mode + 0 + + + EnabledInSleep + Selected module is enabled during Sleep mode + 1 + + + + + + + APB1LPENR + APB1LPENR + APB1 peripheral clock enable in low power + mode register + 0x60 + 0x20 + read-write + 0x36FEC9FF + + + DACLPEN + DAC interface clock enable during Sleep + mode + 29 + 1 + + + + PWRLPEN + Power interface clock enable during + Sleep mode + 28 + 1 + + + + CAN2LPEN + CAN 2 clock enable during Sleep + mode + 26 + 1 + + + + CAN1LPEN + CAN 1 clock enable during Sleep + mode + 25 + 1 + + + + I2C3LPEN + I2C3 clock enable during Sleep + mode + 23 + 1 + + + + I2C2LPEN + I2C2 clock enable during Sleep + mode + 22 + 1 + + + + I2C1LPEN + I2C1 clock enable during Sleep + mode + 21 + 1 + + + + UART5LPEN + UART5 clock enable during Sleep + mode + 20 + 1 + + + + UART4LPEN + UART4 clock enable during Sleep + mode + 19 + 1 + + + + USART3LPEN + USART3 clock enable during Sleep + mode + 18 + 1 + + + + USART2LPEN + USART2 clock enable during Sleep + mode + 17 + 1 + + + + SPI3LPEN + SPI3 clock enable during Sleep + mode + 15 + 1 + + + + SPI2LPEN + SPI2 clock enable during Sleep + mode + 14 + 1 + + + + WWDGLPEN + Window watchdog clock enable during + Sleep mode + 11 + 1 + + + + TIM14LPEN + TIM14 clock enable during Sleep + mode + 8 + 1 + + + + TIM13LPEN + TIM13 clock enable during Sleep + mode + 7 + 1 + + + + TIM12LPEN + TIM12 clock enable during Sleep + mode + 6 + 1 + + + + TIM7LPEN + TIM7 clock enable during Sleep + mode + 5 + 1 + + + + TIM6LPEN + TIM6 clock enable during Sleep + mode + 4 + 1 + + + + TIM5LPEN + TIM5 clock enable during Sleep + mode + 3 + 1 + + + + TIM4LPEN + TIM4 clock enable during Sleep + mode + 2 + 1 + + + + TIM3LPEN + TIM3 clock enable during Sleep + mode + 1 + 1 + + + + TIM2LPEN + TIM2 clock enable during Sleep + mode + 0 + 1 + + TIM2LPEN + read-write + + DisabledInSleep + Selected module is disabled during Sleep mode + 0 + + + EnabledInSleep + Selected module is enabled during Sleep mode + 1 + + + + + + + APB2LPENR + APB2LPENR + APB2 peripheral clock enabled in low power + mode register + 0x64 + 0x20 + read-write + 0x00075F33 + + + TIM11LPEN + TIM11 clock enable during Sleep + mode + 18 + 1 + + + + TIM10LPEN + TIM10 clock enable during Sleep + mode + 17 + 1 + + + + TIM9LPEN + TIM9 clock enable during sleep + mode + 16 + 1 + + + + SYSCFGLPEN + System configuration controller clock + enable during Sleep mode + 14 + 1 + + + + SPI1LPEN + SPI 1 clock enable during Sleep + mode + 12 + 1 + + + + SDIOLPEN + SDIO clock enable during Sleep + mode + 11 + 1 + + + + ADC3LPEN + ADC 3 clock enable during Sleep + mode + 10 + 1 + + + + ADC2LPEN + ADC2 clock enable during Sleep + mode + 9 + 1 + + + + ADC1LPEN + ADC1 clock enable during Sleep + mode + 8 + 1 + + + + USART6LPEN + USART6 clock enable during Sleep + mode + 5 + 1 + + + + USART1LPEN + USART1 clock enable during Sleep + mode + 4 + 1 + + + + TIM8LPEN + TIM8 clock enable during Sleep + mode + 1 + 1 + + + + TIM1LPEN + TIM1 clock enable during Sleep + mode + 0 + 1 + + TIM1LPEN + read-write + + DisabledInSleep + Selected module is disabled during Sleep mode + 0 + + + EnabledInSleep + Selected module is enabled during Sleep mode + 1 + + + + + + + BDCR + BDCR + Backup domain control register + 0x70 + 0x20 + 0x00000000 + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + BDRST + read-write + + Disabled + Reset not activated + 0 + + + Enabled + Reset the entire RTC domain + 1 + + + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + RTCEN + read-write + + Disabled + RTC clock disabled + 0 + + + Enabled + RTC clock enabled + 1 + + + + + LSEBYP + External low-speed oscillator + bypass + 2 + 1 + read-write + + LSEBYP + read-write + + NotBypassed + LSE crystal oscillator not bypassed + 0 + + + Bypassed + LSE crystal oscillator bypassed with external clock + 1 + + + + + LSERDY + External low-speed oscillator + ready + 1 + 1 + read-only + + LSERDYR + read + + NotReady + LSE oscillator not ready + 0 + + + Ready + LSE oscillator ready + 1 + + + + + LSEON + External low-speed oscillator + enable + 0 + 1 + read-write + + LSEON + read-write + + Off + LSE oscillator Off + 0 + + + On + LSE oscillator On + 1 + + + + + RTCSEL + RTC clock source selection + 8 + 2 + + RTCSEL + read-write + + NoClock + No clock + 0 + + + LSE + LSE oscillator clock used as RTC clock + 1 + + + LSI + LSI oscillator clock used as RTC clock + 2 + + + HSE + HSE oscillator clock divided by a prescaler used as RTC clock + 3 + + + + + + + CSR + CSR + clock control & status + register + 0x74 + 0x20 + 0x0E000000 + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + + WDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + + PADRSTF + PIN reset flag + 26 + 1 + read-write + + + + BORRSTF + BOR reset flag + 25 + 1 + read-write + + BORRSTFR + read + + NoReset + No reset has occured + 0 + + + Reset + A reset has occured + 1 + + + + + RMVF + Remove reset flag + 24 + 1 + read-write + + RMVFW + write + + Clear + Clears the reset flag + 1 + + + + + LSIRDY + Internal low-speed oscillator + ready + 1 + 1 + read-only + + LSIRDYR + read + + NotReady + LSI oscillator not ready + 0 + + + Ready + LSI oscillator ready + 1 + + + + + LSION + Internal low-speed oscillator + enable + 0 + 1 + read-write + + LSION + read-write + + Off + LSI oscillator Off + 0 + + + On + LSI oscillator On + 1 + + + + + + + SSCGR + SSCGR + spread spectrum clock generation + register + 0x80 + 0x20 + read-write + 0x00000000 + + + SSCGEN + Spread spectrum modulation + enable + 31 + 1 + + SSCGEN + read-write + + Disabled + Spread spectrum modulation disabled + 0 + + + Enabled + Spread spectrum modulation enabled + 1 + + + + + SPREADSEL + Spread Select + 30 + 1 + + SPREADSEL + read-write + + Center + Center spread + 0 + + + Down + Down spread + 1 + + + + + INCSTEP + Incrementation step + 13 + 15 + + + 0 + 32767 + + + + + MODPER + Modulation period + 0 + 13 + + + 0 + 8191 + + + + + + + PLLI2SCFGR + PLLI2SCFGR + PLLI2S configuration register + 0x84 + 0x20 + read-write + 0x20003000 + + + PLLI2SR + PLLI2S division factor for I2S + clocks + 28 + 3 + + + 2 + 7 + + + + + PLLI2SN + PLLI2S multiplication factor for + VCO + 6 + 9 + + + 50 + 432 + + + + + + + + + GPIOI + General-purpose I/Os + GPIO + 0x40022000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x00000000 + + + 16 + 0x2 + 0-15 + MODER%s + Port x configuration pin %s + 0 + 2 + + MODER0 + read-write + + Input + Input mode (reset state) + 0 + + + Output + General purpose output mode + 1 + + + Alternate + Alternate function mode + 2 + + + Analog + Analog mode + 3 + + + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + 16 + 0x1 + 0-15 + OT%s + Port x configuration pin %s + 0 + 1 + + OT0 + read-write + + PushPull + Output push-pull (reset state) + 0 + + + OpenDrain + Output open-drain + 1 + + + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + 16 + 0x2 + 0-15 + OSPEEDR%s + Port x configuration pin %s + 0 + 2 + + OSPEEDR0 + read-write + + LowSpeed + Low speed + 0 + + + MediumSpeed + Medium speed + 1 + + + HighSpeed + High speed + 2 + + + VeryHighSpeed + Very high speed + 3 + + + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000000 + + + 16 + 0x2 + 0-15 + PUPDR%s + Port x configuration pin %s + 0 + 2 + + PUPDR0 + read-write + + Floating + No pull-up, pull-down + 0 + + + PullUp + Pull-up + 1 + + + PullDown + Pull-down + 2 + + + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + 16 + 0x1 + 0-15 + IDR%s + Port input data pin %s + 0 + 1 + + IDR0 + read + + Low + Input is logic low + 0 + + + High + Input is logic high + 1 + + + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + 16 + 0x1 + 0-15 + ODR%s + Port output data pin %s + 0 + 1 + + ODR0 + read-write + + Low + Set output to logic low + 0 + + + High + Set output to logic high + 1 + + + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + 16 + 0x1 + 0-15 + BR%s + Port x reset pin %s + 16 + 1 + + BR0W + write + + Reset + Resets the corresponding ODRx bit + 1 + + + + + 16 + 0x1 + 0-15 + BS%s + Port x set pin %s + 0 + 1 + + BS0W + write + + Set + Sets the corresponding ODRx bit + 1 + + + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + LCKK + read-write + + NotActive + Port configuration lock key not active + 0 + + + Active + Port configuration lock key active + 1 + + + + + 16 + 0x1 + 0-15 + LCK%s + Port x lock pin %s + 0 + 1 + + LCK0 + read-write + + Unlocked + Port configuration not locked + 0 + + + Locked + Port configuration locked + 1 + + + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + 8 + 0x4 + L0,L1,L2,L3,L4,L5,L6,L7 + AFR%s + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + AFRL0 + read-write + + AF0 + AF0 + 0 + + + AF1 + AF1 + 1 + + + AF2 + AF2 + 2 + + + AF3 + AF3 + 3 + + + AF4 + AF4 + 4 + + + AF5 + AF5 + 5 + + + AF6 + AF6 + 6 + + + AF7 + AF7 + 7 + + + AF8 + AF8 + 8 + + + AF9 + AF9 + 9 + + + AF10 + AF10 + 10 + + + AF11 + AF11 + 11 + + + AF12 + AF12 + 12 + + + AF13 + AF13 + 13 + + + AF14 + AF14 + 14 + + + AF15 + AF15 + 15 + + + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + 8 + 0x4 + H8,H9,H10,H11,H12,H13,H14,H15 + AFR%s + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + AFRH8 + read-write + + AF0 + AF0 + 0 + + + AF1 + AF1 + 1 + + + AF2 + AF2 + 2 + + + AF3 + AF3 + 3 + + + AF4 + AF4 + 4 + + + AF5 + AF5 + 5 + + + AF6 + AF6 + 6 + + + AF7 + AF7 + 7 + + + AF8 + AF8 + 8 + + + AF9 + AF9 + 9 + + + AF10 + AF10 + 10 + + + AF11 + AF11 + 11 + + + AF12 + AF12 + 12 + + + AF13 + AF13 + 13 + + + AF14 + AF14 + 14 + + + AF15 + AF15 + 15 + + + + + + + + + GPIOH + 0x40021C00 + + + GPIOG + 0x40021800 + + + GPIOF + 0x40021400 + + + GPIOE + 0x40021000 + + + GPIOD + 0x40020C00 + + + GPIOC + 0x40020800 + + + GPIOJ + 0x40022400 + + + GPIOK + 0x40022800 + + + GPIOB + General-purpose I/Os + GPIO + 0x40020400 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x00000280 + + + 16 + 0x2 + 0-15 + MODER%s + Port x configuration pin %s + 0 + 2 + + MODER0 + read-write + + Input + Input mode (reset state) + 0 + + + Output + General purpose output mode + 1 + + + Alternate + Alternate function mode + 2 + + + Analog + Analog mode + 3 + + + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + 16 + 0x1 + 0-15 + OT%s + Port x configuration pin %s + 0 + 1 + + OT0 + read-write + + PushPull + Output push-pull (reset state) + 0 + + + OpenDrain + Output open-drain + 1 + + + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x000000C0 + + + 16 + 0x2 + 0-15 + OSPEEDR%s + Port x configuration pin %s + 0 + 2 + + OSPEEDR0 + read-write + + LowSpeed + Low speed + 0 + + + MediumSpeed + Medium speed + 1 + + + HighSpeed + High speed + 2 + + + VeryHighSpeed + Very high speed + 3 + + + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000100 + + + 16 + 0x2 + 0-15 + PUPDR%s + Port x configuration pin %s + 0 + 2 + + PUPDR0 + read-write + + Floating + No pull-up, pull-down + 0 + + + PullUp + Pull-up + 1 + + + PullDown + Pull-down + 2 + + + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + 16 + 0x1 + 0-15 + IDR%s + Port input data pin %s + 0 + 1 + + IDR0 + read + + Low + Input is logic low + 0 + + + High + Input is logic high + 1 + + + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + 16 + 0x1 + 0-15 + ODR%s + Port output data pin %s + 0 + 1 + + ODR0 + read-write + + Low + Set output to logic low + 0 + + + High + Set output to logic high + 1 + + + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + 16 + 0x1 + 0-15 + BR%s + Port x reset pin %s + 16 + 1 + + BR0W + write + + Reset + Resets the corresponding ODRx bit + 1 + + + + + 16 + 0x1 + 0-15 + BS%s + Port x set pin %s + 0 + 1 + + BS0W + write + + Set + Sets the corresponding ODRx bit + 1 + + + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + LCKK + read-write + + NotActive + Port configuration lock key not active + 0 + + + Active + Port configuration lock key active + 1 + + + + + 16 + 0x1 + 0-15 + LCK%s + Port x lock pin %s + 0 + 1 + + LCK0 + read-write + + Unlocked + Port configuration not locked + 0 + + + Locked + Port configuration locked + 1 + + + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + 8 + 0x4 + L0,L1,L2,L3,L4,L5,L6,L7 + AFR%s + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + AFRL0 + read-write + + AF0 + AF0 + 0 + + + AF1 + AF1 + 1 + + + AF2 + AF2 + 2 + + + AF3 + AF3 + 3 + + + AF4 + AF4 + 4 + + + AF5 + AF5 + 5 + + + AF6 + AF6 + 6 + + + AF7 + AF7 + 7 + + + AF8 + AF8 + 8 + + + AF9 + AF9 + 9 + + + AF10 + AF10 + 10 + + + AF11 + AF11 + 11 + + + AF12 + AF12 + 12 + + + AF13 + AF13 + 13 + + + AF14 + AF14 + 14 + + + AF15 + AF15 + 15 + + + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + 8 + 0x4 + H8,H9,H10,H11,H12,H13,H14,H15 + AFR%s + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + AFRH8 + read-write + + AF0 + AF0 + 0 + + + AF1 + AF1 + 1 + + + AF2 + AF2 + 2 + + + AF3 + AF3 + 3 + + + AF4 + AF4 + 4 + + + AF5 + AF5 + 5 + + + AF6 + AF6 + 6 + + + AF7 + AF7 + 7 + + + AF8 + AF8 + 8 + + + AF9 + AF9 + 9 + + + AF10 + AF10 + 10 + + + AF11 + AF11 + 11 + + + AF12 + AF12 + 12 + + + AF13 + AF13 + 13 + + + AF14 + AF14 + 14 + + + AF15 + AF15 + 15 + + + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xA8000000 + + + 16 + 0x2 + 0-15 + MODER%s + Port x configuration pin %s + 0 + 2 + + MODER0 + read-write + + Input + Input mode (reset state) + 0 + + + Output + General purpose output mode + 1 + + + Alternate + Alternate function mode + 2 + + + Analog + Analog mode + 3 + + + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + 16 + 0x1 + 0-15 + OT%s + Port x configuration pin %s + 0 + 1 + + OT0 + read-write + + PushPull + Output push-pull (reset state) + 0 + + + OpenDrain + Output open-drain + 1 + + + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + 16 + 0x2 + 0-15 + OSPEEDR%s + Port x configuration pin %s + 0 + 2 + + OSPEEDR0 + read-write + + LowSpeed + Low speed + 0 + + + MediumSpeed + Medium speed + 1 + + + HighSpeed + High speed + 2 + + + VeryHighSpeed + Very high speed + 3 + + + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x64000000 + + + 16 + 0x2 + 0-15 + PUPDR%s + Port x configuration pin %s + 0 + 2 + + PUPDR0 + read-write + + Floating + No pull-up, pull-down + 0 + + + PullUp + Pull-up + 1 + + + PullDown + Pull-down + 2 + + + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + 16 + 0x1 + 0-15 + IDR%s + Port input data pin %s + 0 + 1 + + IDR0 + read + + Low + Input is logic low + 0 + + + High + Input is logic high + 1 + + + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + 16 + 0x1 + 0-15 + ODR%s + Port output data pin %s + 0 + 1 + + ODR0 + read-write + + Low + Set output to logic low + 0 + + + High + Set output to logic high + 1 + + + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + 16 + 0x1 + 0-15 + BR%s + Port x reset pin %s + 16 + 1 + + BR0W + write + + Reset + Resets the corresponding ODRx bit + 1 + + + + + 16 + 0x1 + 0-15 + BS%s + Port x set pin %s + 0 + 1 + + BS0W + write + + Set + Sets the corresponding ODRx bit + 1 + + + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + LCKK + read-write + + NotActive + Port configuration lock key not active + 0 + + + Active + Port configuration lock key active + 1 + + + + + 16 + 0x1 + 0-15 + LCK%s + Port x lock pin %s + 0 + 1 + + LCK0 + read-write + + Unlocked + Port configuration not locked + 0 + + + Locked + Port configuration locked + 1 + + + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + 8 + 0x4 + L0,L1,L2,L3,L4,L5,L6,L7 + AFR%s + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + AFRL0 + read-write + + AF0 + AF0 + 0 + + + AF1 + AF1 + 1 + + + AF2 + AF2 + 2 + + + AF3 + AF3 + 3 + + + AF4 + AF4 + 4 + + + AF5 + AF5 + 5 + + + AF6 + AF6 + 6 + + + AF7 + AF7 + 7 + + + AF8 + AF8 + 8 + + + AF9 + AF9 + 9 + + + AF10 + AF10 + 10 + + + AF11 + AF11 + 11 + + + AF12 + AF12 + 12 + + + AF13 + AF13 + 13 + + + AF14 + AF14 + 14 + + + AF15 + AF15 + 15 + + + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + 8 + 0x4 + H8,H9,H10,H11,H12,H13,H14,H15 + AFR%s + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + AFRH8 + read-write + + AF0 + AF0 + 0 + + + AF1 + AF1 + 1 + + + AF2 + AF2 + 2 + + + AF3 + AF3 + 3 + + + AF4 + AF4 + 4 + + + AF5 + AF5 + 5 + + + AF6 + AF6 + 6 + + + AF7 + AF7 + 7 + + + AF8 + AF8 + 8 + + + AF9 + AF9 + 9 + + + AF10 + AF10 + 10 + + + AF11 + AF11 + 11 + + + AF12 + AF12 + 12 + + + AF13 + AF13 + 13 + + + AF14 + AF14 + 14 + + + AF15 + AF15 + 15 + + + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + MEMRM + MEMRM + memory remap register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + MEM_MODE + 0 + 2 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x00000000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x00000000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x00000000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to + 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to + 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to + 15) + 0 + 4 + + + + + CMPCR + CMPCR + Compensation cell control + register + 0x20 + 0x20 + read-only + 0x00000000 + + + READY + READY + 8 + 1 + + + CMP_PD + Compensation cell + power-down + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + BIDIMODE + read-write + + Unidirectional + 2-line unidirectional data mode selected + 0 + + + Bidirectional + 1-line bidirectional data mode selected + 1 + + + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + BIDIOE + read-write + + OutputDisabled + Output disabled (receive-only mode) + 0 + + + OutputEnabled + Output enabled (transmit-only mode) + 1 + + + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + CRCEN + read-write + + Disabled + CRC calculation disabled + 0 + + + Enabled + CRC calculation enabled + 1 + + + + + CRCNEXT + CRC transfer next + 12 + 1 + + CRCNEXT + read-write + + TxBuffer + Next transmit value is from Tx buffer + 0 + + + CRC + Next transmit value is from Tx CRC register + 1 + + + + + DFF + Data frame format + 11 + 1 + + DFF + read-write + + EightBit + 8-bit data frame format is selected for transmission/reception + 0 + + + SixteenBit + 16-bit data frame format is selected for transmission/reception + 1 + + + + + RXONLY + Receive only + 10 + 1 + + RXONLY + read-write + + FullDuplex + Full duplex (Transmit and receive) + 0 + + + OutputDisabled + Output disabled (Receive-only mode) + 1 + + + + + SSM + Software slave management + 9 + 1 + + SSM + read-write + + Disabled + Software slave management disabled + 0 + + + Enabled + Software slave management enabled + 1 + + + + + SSI + Internal slave select + 8 + 1 + + SSI + read-write + + SlaveSelected + 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored + 0 + + + SlaveNotSelected + 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored + 1 + + + + + LSBFIRST + Frame format + 7 + 1 + + LSBFIRST + read-write + + MSBFirst + Data is transmitted/received with the MSB first + 0 + + + LSBFirst + Data is transmitted/received with the LSB first + 1 + + + + + SPE + SPI enable + 6 + 1 + + SPE + read-write + + Disabled + Peripheral disabled + 0 + + + Enabled + Peripheral enabled + 1 + + + + + BR + Baud rate control + 3 + 3 + + BR + read-write + + Div2 + f_PCLK / 2 + 0 + + + Div4 + f_PCLK / 4 + 1 + + + Div8 + f_PCLK / 8 + 2 + + + Div16 + f_PCLK / 16 + 3 + + + Div32 + f_PCLK / 32 + 4 + + + Div64 + f_PCLK / 64 + 5 + + + Div128 + f_PCLK / 128 + 6 + + + Div256 + f_PCLK / 256 + 7 + + + + + MSTR + Master selection + 2 + 1 + + MSTR + read-write + + Slave + Slave configuration + 0 + + + Master + Master configuration + 1 + + + + + CPOL + Clock polarity + 1 + 1 + + CPOL + read-write + + IdleLow + CK to 0 when idle + 0 + + + IdleHigh + CK to 1 when idle + 1 + + + + + CPHA + Clock phase + 0 + 1 + + CPHA + read-write + + FirstEdge + The first clock transition is the first data capture edge + 0 + + + SecondEdge + The second clock transition is the first data capture edge + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + TXEIE + read-write + + Masked + TXE interrupt masked + 0 + + + NotMasked + TXE interrupt not masked + 1 + + + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + RXNEIE + read-write + + Masked + RXE interrupt masked + 0 + + + NotMasked + RXE interrupt not masked + 1 + + + + + ERRIE + Error interrupt enable + 5 + 1 + + ERRIE + read-write + + Masked + Error interrupt masked + 0 + + + NotMasked + Error interrupt not masked + 1 + + + + + FRF + Frame format + 4 + 1 + + FRF + read-write + + Motorola + SPI Motorola mode + 0 + + + TI + SPI TI mode + 1 + + + + + SSOE + SS output enable + 2 + 1 + + SSOE + read-write + + Disabled + SS output is disabled in master mode + 0 + + + Enabled + SS output is enabled in master mode + 1 + + + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + TXDMAEN + read-write + + Disabled + Tx buffer DMA disabled + 0 + + + Enabled + Tx buffer DMA enabled + 1 + + + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + RXDMAEN + read-write + + Disabled + Rx buffer DMA disabled + 0 + + + Enabled + Rx buffer DMA enabled + 1 + + + + + + + SR + SR + status register + 0x8 + 0x20 + 0x00000002 + + + FRE + TI frame format error + 8 + 1 + read-only + + FRER + read + + NoError + No frame format error + 0 + + + Error + A frame format error occurred + 1 + + + + + BSY + Busy flag + 7 + 1 + read-only + + BSYR + read + + NotBusy + SPI not busy + 0 + + + Busy + SPI busy + 1 + + + + + OVR + Overrun flag + 6 + 1 + read-only + + OVRR + read + + NoOverrun + No overrun occurred + 0 + + + Overrun + Overrun occurred + 1 + + + + + MODF + Mode fault + 5 + 1 + read-only + + MODFR + read + + NoFault + No mode fault occurred + 0 + + + Fault + Mode fault occurred + 1 + + + + + CRCERR + CRC error flag + 4 + 1 + read-write + zeroToClear + + CRCERRR + read + + Match + CRC value received matches the SPIx_RXCRCR value + 0 + + + NoMatch + CRC value received does not match the SPIx_RXCRCR value + 1 + + + + CRCERRW + write + + Clear + Clear flag + 0 + + + + + UDR + Underrun flag + 3 + 1 + read-only + + UDRR + read + + NoUnderrun + No underrun occurred + 0 + + + Underrun + Underrun occurred + 1 + + + + + CHSIDE + Channel side + 2 + 1 + read-only + + CHSIDE + read + + Left + Channel left has to be transmitted or has been received + 0 + + + Right + Channel right has to be transmitted or has been received + 1 + + + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + TXE + read + + NotEmpty + Tx buffer not empty + 0 + + + Empty + Tx buffer empty + 1 + + + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + RXNE + read + + Empty + Rx buffer empty + 0 + + + NotEmpty + Rx buffer not empty + 1 + + + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x00000000 + + + DR + Data register + 0 + 16 + + + 0 + 65535 + + + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + 0 + 65535 + + + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x00000000 + + + RxCRC + Rx CRC register + 0 + 16 + + + 0 + 65535 + + + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x00000000 + + + TxCRC + Tx CRC register + 0 + 16 + + + 0 + 65535 + + + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + I2SMOD + I2S mode selection + 11 + 1 + + I2SMOD + read-write + + SPIMode + SPI mode is selected + 0 + + + I2SMode + I2S mode is selected + 1 + + + + + I2SE + I2S Enable + 10 + 1 + + I2SE + read-write + + Disabled + I2S peripheral is disabled + 0 + + + Enabled + I2S peripheral is enabled + 1 + + + + + I2SCFG + I2S configuration mode + 8 + 2 + + I2SCFG + read-write + + SlaveTx + Slave - transmit + 0 + + + SlaveRx + Slave - receive + 1 + + + MasterTx + Master - transmit + 2 + + + MasterRx + Master - receive + 3 + + + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + PCMSYNC + read-write + + Short + Short frame synchronisation + 0 + + + Long + Long frame synchronisation + 1 + + + + + I2SSTD + I2S standard selection + 4 + 2 + + I2SSTD + read-write + + Philips + I2S Philips standard + 0 + + + MSB + MSB justified standard + 1 + + + LSB + LSB justified standard + 2 + + + PCM + PCM standard + 3 + + + + + CKPOL + Steady state clock + polarity + 3 + 1 + + CKPOL + read-write + + IdleLow + I2S clock inactive state is low level + 0 + + + IdleHigh + I2S clock inactive state is high level + 1 + + + + + DATLEN + Data length to be + transferred + 1 + 2 + + DATLEN + read-write + + SixteenBit + 16-bit data length + 0 + + + TwentyFourBit + 24-bit data length + 1 + + + ThirtyTwoBit + 32-bit data length + 2 + + + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + CHLEN + read-write + + SixteenBit + 16-bit wide + 0 + + + ThirtyTwoBit + 32-bit wide + 1 + + + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 0x0000000A + + + MCKOE + Master clock output enable + 9 + 1 + + MCKOE + read-write + + Disabled + Master clock output is disabled + 0 + + + Enabled + Master clock output is enabled + 1 + + + + + ODD + Odd factor for the + prescaler + 8 + 1 + + ODD + read-write + + Even + Real divider value is I2SDIV * 2 + 0 + + + Odd + Real divider value is (I2SDIV * 2) + 1 + 1 + + + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + 2 + 255 + + + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + I2S2ext + 0x40003400 + + + I2S3ext + 0x40004000 + + + SPI4 + 0x40013400 + + SPI1 + SPI1 global interrupt + 35 + + + + SPI5 + 0x40015000 + + SPI1 + SPI1 global interrupt + 35 + + + + SPI6 + 0x40015400 + + SPI3 + SPI3 global interrupt + 51 + + + + SDIO + Secure digital input/output + interface + SDIO + 0x40012C00 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 49 + + + + POWER + POWER + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + PWRCTRL + read-write + + PowerOff + Power off + 0 + + + PowerOn + Power on + 3 + + + + + + + CLKCR + CLKCR + SDI clock control register + 0x4 + 0x20 + read-write + 0x00000000 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + HWFC_EN + read-write + + Disabled + HW Flow Control is disabled + 0 + + + Enabled + HW Flow Control is enabled + 1 + + + + + NEGEDGE + SDIO_CK dephasing selection + bit + 13 + 1 + + NEGEDGE + read-write + + Rising + SDIO_CK generated on the rising edge + 0 + + + Falling + SDIO_CK generated on the falling edge + 1 + + + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + WIDBUS + read-write + + BusWidth1 + 1 lane wide bus + 0 + + + BusWidth4 + 4 lane wide bus + 1 + + + BusWidth8 + 8 lane wide bus + 2 + + + + + BYPASS + Clock divider bypass enable + bit + 10 + 1 + + BYPASS + read-write + + Disabled + SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal. + 0 + + + Enabled + SDIOCLK directly drives the SDIO_CK output signal + 1 + + + + + PWRSAV + Power saving configuration + bit + 9 + 1 + + PWRSAV + read-write + + Enabled + SDIO_CK clock is always enabled + 0 + + + Disabled + SDIO_CK is only enabled when the bus is active + 1 + + + + + CLKEN + Clock enable bit + 8 + 1 + + CLKEN + read-write + + Disabled + Disable clock + 0 + + + Enabled + Enable clock + 1 + + + + + CLKDIV + Clock divide factor + 0 + 8 + + + 0 + 255 + + + + + + + ARG + ARG + argument register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + 0 + 4294967295 + + + + + + + CMD + CMD + command register + 0xC + 0x20 + read-write + 0x00000000 + + + CE_ATACMD + CE-ATA command + 14 + 1 + + CE_ATACMD + read-write + + Disabled + CE-ATA command disabled + 0 + + + Enabled + CE-ATA command enabled + 1 + + + + + nIEN + not Interrupt Enable + 13 + 1 + + nIEN + read-write + + Disabled + Interrupts to the CE-ATA not disabled + 0 + + + Enabled + Interrupt to the CE-ATA are disabled + 1 + + + + + ENCMDcompl + Enable CMD completion + 12 + 1 + + ENCMDcompl + read-write + + Disabled + Command complete signal disabled + 0 + + + Enabled + Command complete signal enabled + 1 + + + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + SDIOSuspend + read-write + + Disabled + Next command is not a SDIO suspend command + 0 + + + Enabled + Next command send is a SDIO suspend command + 1 + + + + + CPSMEN + Command path state machine (CPSM) Enable + bit + 10 + 1 + + CPSMEN + read-write + + Disabled + Command path state machine disabled + 0 + + + Enabled + Command path state machine enabled + 1 + + + + + WAITPEND + CPSM Waits for ends of data transfer + (CmdPend internal signal). + 9 + 1 + + WAITPEND + read-write + + Disabled + Don't wait for data end + 0 + + + Enabled + Wait for end of data transfer signal before sending command + 1 + + + + + WAITINT + CPSM waits for interrupt + request + 8 + 1 + + WAITINT + read-write + + Disabled + Don't wait for interrupt request + 0 + + + Enabled + Wait for interrupt request + 1 + + + + + WAITRESP + Wait for response bits + 6 + 2 + + WAITRESP + read-write + + NoResponse + No response + 0 + + + ShortResponse + Short response + 1 + + + NoResponse2 + No reponse + 2 + + + LongResponse + Long reponse + 3 + + + + + CMDINDEX + Command index + 0 + 6 + + + 0 + 63 + + + + + + + RESPCMD + RESPCMD + command response register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + 0 + 63 + + + + + + + 4 + 0x4 + 1-4 + RESP%s + RESP1 + SDIO response %s register + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS + Status of a card, which is part of the received response + 0 + 32 + + + 0 + 4294967295 + + + + + + + DTIMER + DTIMER + data timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + 0 + 4294967295 + + + + + + + DLEN + DLEN + data length register + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + 0 + 33554431 + + + + + + + DCTRL + DCTRL + data control register + 0x2C + 0x20 + read-write + 0x00000000 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + SDIOEN + read-write + + Disabled + SDIO operations disabled + 0 + + + Enabled + SDIO operations enabled + 1 + + + + + RWMOD + Read wait mode + 10 + 1 + + RWMOD + read-write + + D2 + Read wait control stopping using SDIO_D2 + 0 + + + Ck + Read wait control using SDIO_CK + 1 + + + + + RWSTOP + Read wait stop + 9 + 1 + + RWSTOP + read-write + + Disabled + Read wait in progress if RWSTART is enabled + 0 + + + Enabled + Enable for read wait stop if RWSTART is enabled + 1 + + + + + RWSTART + Read wait start + 8 + 1 + + RWSTART + read-write + + Disabled + Don't start read wait operation + 0 + + + Enabled + Read wait operation starts + 1 + + + + + DBLOCKSIZE + Data block size + 4 + 4 + + + 0 + 15 + + + + + DMAEN + DMA enable bit + 3 + 1 + + DMAEN + read-write + + Disabled + Dma disabled + 0 + + + Enabled + Dma enabled + 1 + + + + + DTMODE + Data transfer mode selection 1: Stream + or SDIO multibyte data transfer. + 2 + 1 + + DTMODE + read-write + + BlockMode + Bloack data transfer + 0 + + + StreamMode + Stream or SDIO multibyte data transfer + 1 + + + + + DTDIR + Data transfer direction + selection + 1 + 1 + + DTDIR + read-write + + ControllerToCard + From controller to card + 0 + + + CardToController + From card to controller + 1 + + + + + DTEN + DTEN + 0 + 1 + + DTEN + read-write + + Disabled + Disabled + 0 + + + Enabled + Start transfer + 1 + + + + + + + DCOUNT + DCOUNT + data counter register + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + 0 + 33554431 + + + + + + + STA + STA + status register + 0x34 + 0x20 + read-only + 0x00000000 + + + CEATAEND + CE-ATA command completion signal + received for CMD61 + 23 + 1 + + CEATAEND + read + + NotReceived + Completion signal not received + 0 + + + Received + CE-ATA command completion signal received for CMD61 + 1 + + + + + SDIOIT + SDIO interrupt received + 22 + 1 + + SDIOIT + read + + NotReceived + SDIO interrupt not receieved + 0 + + + Received + SDIO interrupt received + 1 + + + + + RXDAVL + Data available in receive + FIFO + 21 + 1 + + RXDAVL + read + + NotAvailable + Data not available in receive FIFO + 0 + + + Available + Data available in receive FIFO + 1 + + + + + TXDAVL + Data available in transmit + FIFO + 20 + 1 + + TXDAVL + read + + NotAvailable + Data not available in transmit FIFO + 0 + + + Available + Data available in transmit FIFO + 1 + + + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + RXFIFOE + read + + NotEmpty + Receive FIFO not empty + 0 + + + Empty + Receive FIFO empty + 1 + + + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + TXFIFOE + read + + NotEmpty + Transmit FIFO not empty + 0 + + + Empty + Transmit FIFO empty. When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words. + 1 + + + + + RXFIFOF + Receive FIFO full + 17 + 1 + + RXFIFOF + read + + NotFull + Transmit FIFO not full + 0 + + + Full + Receive FIFO full. When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full. + 1 + + + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + TXFIFOF + read + + NotFull + Transmit FIFO not full + 0 + + + Full + Transmit FIFO full + 1 + + + + + RXFIFOHF + Receive FIFO half full: there are at + least 8 words in the FIFO + 15 + 1 + + RXFIFOHF + read + + NotHalfFull + Receive FIFO not half full + 0 + + + HalfFull + Receive FIFO half full. At least 8 words in the FIFO + 1 + + + + + TXFIFOHE + Transmit FIFO half empty: at least 8 + words can be written into the FIFO + 14 + 1 + + TXFIFOHE + read + + NotHalfEmpty + Transmit FIFO not half empty + 0 + + + HalfEmpty + Transmit FIFO half empty. At least 8 words can be written into the FIFO + 1 + + + + + RXACT + Data receive in progress + 13 + 1 + + RXACT + read + + NotInProgress + Data receive not in progress + 0 + + + InProgress + Data receive in progress + 1 + + + + + TXACT + Data transmit in progress + 12 + 1 + + TXACT + read + + NotInProgress + Data transmit is not in progress + 0 + + + InProgress + Data transmit in progress + 1 + + + + + CMDACT + Command transfer in + progress + 11 + 1 + + CMDACT + read + + NotInProgress + Command transfer not in progress + 0 + + + InProgress + Command tranfer in progress + 1 + + + + + DBCKEND + Data block sent/received (CRC check + passed) + 10 + 1 + + DBCKEND + read + + NotTransferred + Data block not sent/received (CRC check failed) + 0 + + + Transferred + Data block sent/received (CRC check passed) + 1 + + + + + STBITERR + Start bit not detected on all data + signals in wide bus mode + 9 + 1 + + STBITERR + read + + Detected + No start bit detected error + 0 + + + NotDetected + Start bit not detected error + 1 + + + + + DATAEND + Data end (data counter, SDIDCOUNT, is + zero) + 8 + 1 + + DATAEND + read + + NotDone + Not done + 0 + + + Done + Data end (DCOUNT, is zero) + 1 + + + + + CMDSENT + Command sent (no response + required) + 7 + 1 + + CMDSENT + read + + NotSent + Command not sent + 0 + + + Sent + Command sent (no response required) + 1 + + + + + CMDREND + Command response received (CRC check + passed) + 6 + 1 + + CMDREND + read + + NotDone + Command not done + 0 + + + Done + Command response received (CRC check passed) + 1 + + + + + RXOVERR + Received FIFO overrun + error + 5 + 1 + + RXOVERR + read + + NoOverrun + No FIFO overrun error + 0 + + + Overrun + Receive FIFO overrun error + 1 + + + + + TXUNDERR + Transmit FIFO underrun + error + 4 + 1 + + TXUNDERR + read + + NoUnderrun + No transmit FIFO underrun error + 0 + + + Underrun + Transmit FIFO underrun error + 1 + + + + + DTIMEOUT + Data timeout + 3 + 1 + + DTIMEOUT + read + + NoTimeout + No data timeout + 0 + + + Timeout + Data timeout + 1 + + + + + CTIMEOUT + Command response timeout + 2 + 1 + + CTIMEOUT + read + + NoTimeout + No Command timeout + 0 + + + Timeout + Command timeout + 1 + + + + + DCRCFAIL + Data block sent/received (CRC check + failed) + 1 + 1 + + DCRCFAIL + read + + NotFailed + No Data block sent/received crc check fail + 0 + + + Failed + Data block sent/received crc failed + 1 + + + + + CCRCFAIL + Command response received (CRC check + failed) + 0 + 1 + + CCRCFAIL + read + + NotFailed + Command response received, crc check passed + 0 + + + Failed + Command response received, crc check failed + 1 + + + + + + + ICR + ICR + interrupt clear register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEATAENDC + CEATAEND flag clear bit + 23 + 1 + + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + + STBITERRC + STBITERR flag clear bit + 9 + 1 + + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + CCRCFAILCW + write + + Clear + Clear flag + 1 + + + + + + + MASK + MASK + mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + CEATAENDIE + CE-ATA command completion signal + received interrupt enable + 23 + 1 + + + + SDIOITIE + SDIO mode interrupt received interrupt + enable + 22 + 1 + + + + RXDAVLIE + Data available in Rx FIFO interrupt + enable + 21 + 1 + + + + TXDAVLIE + Data available in Tx FIFO interrupt + enable + 20 + 1 + + + + RXFIFOEIE + Rx FIFO empty interrupt + enable + 19 + 1 + + + + TXFIFOEIE + Tx FIFO empty interrupt + enable + 18 + 1 + + + + RXFIFOFIE + Rx FIFO full interrupt + enable + 17 + 1 + + + + TXFIFOFIE + Tx FIFO full interrupt + enable + 16 + 1 + + + + RXFIFOHFIE + Rx FIFO half full interrupt + enable + 15 + 1 + + + + TXFIFOHEIE + Tx FIFO half empty interrupt + enable + 14 + 1 + + + + RXACTIE + Data receive acting interrupt + enable + 13 + 1 + + + + TXACTIE + Data transmit acting interrupt + enable + 12 + 1 + + + + CMDACTIE + Command acting interrupt + enable + 11 + 1 + + + + DBCKENDIE + Data block end interrupt + enable + 10 + 1 + + + + STBITERRIE + Start bit error interrupt + enable + 9 + 1 + + + + DATAENDIE + Data end interrupt enable + 8 + 1 + + + + CMDSENTIE + Command sent interrupt + enable + 7 + 1 + + + + CMDRENDIE + Command response received interrupt + enable + 6 + 1 + + + + RXOVERRIE + Rx FIFO overrun error interrupt + enable + 5 + 1 + + + + TXUNDERRIE + Tx FIFO underrun error interrupt + enable + 4 + 1 + + + + DTIMEOUTIE + Data timeout interrupt + enable + 3 + 1 + + + + CTIMEOUTIE + Command timeout interrupt + enable + 2 + 1 + + + + DCRCFAILIE + Data CRC fail interrupt + enable + 1 + 1 + + + + CCRCFAILIE + Command CRC fail interrupt + enable + 0 + 1 + + CCRCFAILIE + read-write + + Disabled + Interrupt disabled + 0 + + + Enabled + Interrupt enabled + 1 + + + + + + + FIFOCNT + FIFOCNT + FIFO counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + FIFOCOUNT + Remaining number of words to be written + to or read from the FIFO. + 0 + 24 + + + 0 + 16777215 + + + + + + + FIFO + FIFO + data FIFO register + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + Receive and transmit FIFO + data + 0 + 32 + + + 0 + 4294967295 + + + + + + + + + ADC1 + Analog-to-digital converter + ADC + 0x40012000 + + 0x0 + 0x51 + registers + + + ADC + ADC1 global interrupt + 18 + + + + SR + SR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OVR + Overrun + 5 + 1 + zeroToClear + + OVRR + read + + NoOverrun + No overrun occurred + 0 + + + Overrun + Overrun occurred + 1 + + + + OVRW + write + + Clear + Clear flag + 0 + + + + + STRT + Regular channel start flag + 4 + 1 + zeroToClear + + STRTR + read + + NotStarted + No regular channel conversion started + 0 + + + Started + Regular channel conversion has started + 1 + + + + STRTW + write + + Clear + Clear flag + 0 + + + + + JSTRT + Injected channel start + flag + 3 + 1 + zeroToClear + + JSTRTR + read + + NotStarted + No injected channel conversion started + 0 + + + Started + Injected channel conversion has started + 1 + + + + JSTRTW + write + + Clear + Clear flag + 0 + + + + + JEOC + Injected channel end of + conversion + 2 + 1 + zeroToClear + + JEOCR + read + + NotComplete + Conversion is not complete + 0 + + + Complete + Conversion complete + 1 + + + + JEOCW + write + + Clear + Clear flag + 0 + + + + + EOC + Regular channel end of + conversion + 1 + 1 + zeroToClear + + EOCR + read + + NotComplete + Conversion is not complete + 0 + + + Complete + Conversion complete + 1 + + + + EOCW + write + + Clear + Clear flag + 0 + + + + + AWD + Analog watchdog flag + 0 + 1 + zeroToClear + + AWDR + read + + NoEvent + No analog watchdog event occurred + 0 + + + Event + Analog watchdog event occurred + 1 + + + + AWDW + write + + Clear + Clear flag + 0 + + + + + + + CR1 + CR1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OVRIE + Overrun interrupt enable + 26 + 1 + + OVRIE + read-write + + Disabled + Overrun interrupt disabled + 0 + + + Enabled + Overrun interrupt enabled + 1 + + + + + RES + Resolution + 24 + 2 + + RES + read-write + + TwelveBit + 12-bit (15 ADCCLK cycles) + 0 + + + TenBit + 10-bit (13 ADCCLK cycles) + 1 + + + EightBit + 8-bit (11 ADCCLK cycles) + 2 + + + SixBit + 6-bit (9 ADCCLK cycles) + 3 + + + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + AWDEN + read-write + + Disabled + Analog watchdog disabled on regular channels + 0 + + + Enabled + Analog watchdog enabled on regular channels + 1 + + + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + JAWDEN + read-write + + Disabled + Analog watchdog disabled on injected channels + 0 + + + Enabled + Analog watchdog enabled on injected channels + 1 + + + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + 0 + 7 + + + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + JDISCEN + read-write + + Disabled + Discontinuous mode on injected channels disabled + 0 + + + Enabled + Discontinuous mode on injected channels enabled + 1 + + + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + DISCEN + read-write + + Disabled + Discontinuous mode on regular channels disabled + 0 + + + Enabled + Discontinuous mode on regular channels enabled + 1 + + + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + JAUTO + read-write + + Disabled + Automatic injected group conversion disabled + 0 + + + Enabled + Automatic injected group conversion enabled + 1 + + + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + AWDSGL + read-write + + AllChannels + Analog watchdog enabled on all channels + 0 + + + SingleChannel + Analog watchdog enabled on a single channel + 1 + + + + + SCAN + Scan mode + 8 + 1 + + SCAN + read-write + + Disabled + Scan mode disabled + 0 + + + Enabled + Scan mode enabled + 1 + + + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + JEOCIE + read-write + + Disabled + JEOC interrupt disabled + 0 + + + Enabled + JEOC interrupt enabled + 1 + + + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + AWDIE + read-write + + Disabled + Analogue watchdog interrupt disabled + 0 + + + Enabled + Analogue watchdog interrupt enabled + 1 + + + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + EOCIE + read-write + + Disabled + EOC interrupt disabled + 0 + + + Enabled + EOC interrupt enabled + 1 + + + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + 0 + 18 + + + + + + + CR2 + CR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + SWSTART + Start conversion of regular + channels + 30 + 1 + + SWSTARTW + write + + Start + Starts conversion of regular channels + 1 + + + + + EXTEN + External trigger enable for regular + channels + 28 + 2 + + EXTEN + read-write + + Disabled + Trigger detection disabled + 0 + + + RisingEdge + Trigger detection on the rising edge + 1 + + + FallingEdge + Trigger detection on the falling edge + 2 + + + BothEdges + Trigger detection on both the rising and falling edges + 3 + + + + + EXTSEL + External event select for regular + group + 24 + 4 + + EXTSEL + read-write + + TIM1CC1 + Timer 1 CC1 event + 0 + + + TIM1CC2 + Timer 1 CC2 event + 1 + + + TIM1CC3 + Timer 1 CC3 event + 2 + + + TIM2CC2 + Timer 2 CC2 event + 3 + + + TIM2CC3 + Timer 2 CC3 event + 4 + + + TIM2CC4 + Timer 2 CC4 event + 5 + + + TIM2TRGO + Timer 2 TRGO event + 6 + + + TIM3CC1 + Timer 3 CC1 event + 7 + + + TIM3TRGO + Timer 3 TRGO event + 8 + + + TIM4CC4 + Timer 4 CC4 event + 9 + + + TIM5CC1 + Timer 5 CC1 event + 10 + + + TIM5CC2 + Timer 5 CC2 event + 11 + + + TIM5CC3 + Timer 5 CC3 event + 12 + + + TIM8CC1 + Timer 8 CC1 event + 13 + + + TIM8TRGO + Timer 8 TRGO event + 14 + + + EXTI11 + EXTI line 11 + 15 + + + + + JSWSTART + Start conversion of injected + channels + 22 + 1 + + JSWSTARTW + write + + Start + Starts conversion of injected channels + 1 + + + + + JEXTEN + External trigger enable for injected + channels + 20 + 2 + + JEXTEN + read-write + + Disabled + Trigger detection disabled + 0 + + + RisingEdge + Trigger detection on the rising edge + 1 + + + FallingEdge + Trigger detection on the falling edge + 2 + + + BothEdges + Trigger detection on both the rising and falling edges + 3 + + + + + JEXTSEL + External event select for injected + group + 16 + 4 + + JEXTSEL + read-write + + TIM1CC4 + Timer 1 CC4 event + 0 + + + TIM1TRGO + Timer 1 TRGO event + 1 + + + TIM2CC1 + Timer 2 CC1 event + 2 + + + TIM2TRGO + Timer 2 TRGO event + 3 + + + TIM3CC2 + Timer 3 CC2 event + 4 + + + TIM3CC4 + Timer 3 CC4 event + 5 + + + TIM4CC1 + Timer 4 CC1 event + 6 + + + TIM4CC2 + Timer 4 CC2 event + 7 + + + TIM4CC3 + Timer 4 CC3 event + 8 + + + TIM4TRGO + Timer 4 TRGO event + 9 + + + TIM5CC4 + Timer 5 CC4 event + 10 + + + TIM5TRGO + Timer 5 TRGO event + 11 + + + TIM8CC2 + Timer 8 CC2 event + 12 + + + TIM8CC3 + Timer 8 CC3 event + 13 + + + TIM8CC4 + Timer 8 CC4 event + 14 + + + EXTI15 + EXTI line 15 + 15 + + + + + ALIGN + Data alignment + 11 + 1 + + ALIGN + read-write + + Right + Right alignment + 0 + + + Left + Left alignment + 1 + + + + + EOCS + End of conversion + selection + 10 + 1 + + EOCS + read-write + + EachSequence + The EOC bit is set at the end of each sequence of regular conversions + 0 + + + EachConversion + The EOC bit is set at the end of each regular conversion + 1 + + + + + DDS + DMA disable selection (for single ADC + mode) + 9 + 1 + + DDS + read-write + + Single + No new DMA request is issued after the last transfer + 0 + + + Continuous + DMA requests are issued as long as data are converted and DMA=1 + 1 + + + + + DMA + Direct memory access mode (for single + ADC mode) + 8 + 1 + + DMA + read-write + + Disabled + DMA mode disabled + 0 + + + Enabled + DMA mode enabled + 1 + + + + + CONT + Continuous conversion + 1 + 1 + + CONT + read-write + + Single + Single conversion mode + 0 + + + Continuous + Continuous conversion mode + 1 + + + + + ADON + A/D Converter ON / OFF + 0 + 1 + + ADON + read-write + + Disabled + Disable ADC conversion and go to power down mode + 0 + + + Enabled + Enable ADC + 1 + + + + + + + SMPR1 + SMPR1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMP18 + Channel 18 sampling time selection + 24 + 3 + + + + SMP17 + Channel 17 sampling time selection + 21 + 3 + + + + SMP16 + Channel 16 sampling time selection + 18 + 3 + + + + SMP15 + Channel 15 sampling time selection + 15 + 3 + + + + SMP14 + Channel 14 sampling time selection + 12 + 3 + + + + SMP13 + Channel 13 sampling time selection + 9 + 3 + + + + SMP12 + Channel 12 sampling time selection + 6 + 3 + + + + SMP11 + Channel 11 sampling time selection + 3 + 3 + + + + SMP10 + Channel 10 sampling time selection + 0 + 3 + + SMP10 + read-write + + Cycles3 + 3 cycles + 0 + + + Cycles15 + 15 cycles + 1 + + + Cycles28 + 28 cycles + 2 + + + Cycles56 + 56 cycles + 3 + + + Cycles84 + 84 cycles + 4 + + + Cycles112 + 112 cycles + 5 + + + Cycles144 + 144 cycles + 6 + + + Cycles480 + 480 cycles + 7 + + + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMP9 + Channel 9 sampling time selection + 27 + 3 + + + + SMP8 + Channel 8 sampling time selection + 24 + 3 + + + + SMP7 + Channel 7 sampling time selection + 21 + 3 + + + + SMP6 + Channel 6 sampling time selection + 18 + 3 + + + + SMP5 + Channel 5 sampling time selection + 15 + 3 + + + + SMP4 + Channel 4 sampling time selection + 12 + 3 + + + + SMP3 + Channel 3 sampling time selection + 9 + 3 + + + + SMP2 + Channel 2 sampling time selection + 6 + 3 + + + + SMP1 + Channel 1 sampling time selection + 3 + 3 + + + + SMP0 + Channel 0 sampling time selection + 0 + 3 + + SMP0 + read-write + + Cycles3 + 3 cycles + 0 + + + Cycles15 + 15 cycles + 1 + + + Cycles28 + 28 cycles + 2 + + + Cycles56 + 56 cycles + 3 + + + Cycles84 + 84 cycles + 4 + + + Cycles112 + 112 cycles + 5 + + + Cycles144 + 144 cycles + 6 + + + Cycles480 + 480 cycles + 7 + + + + + + + 4 + 0x4 + 1-4 + JOFR%s + JOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET + Data offset for injected channel + x + 0 + 12 + + + 0 + 4095 + + + + + + + HTR + HTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + HT + Analog watchdog higher + threshold + 0 + 12 + + + 0 + 4095 + + + + + + + LTR + LTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + 0 + 4095 + + + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + 0 + 15 + + + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + 0 + 18 + + + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + 0 + 18 + + + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + 0 + 18 + + + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + 0 + 18 + + + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + 0 + 18 + + + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + 0 + 18 + + + + + SQ10 + 10th conversion in regular + sequence + 15 + 5 + + + 0 + 18 + + + + + SQ9 + 9th conversion in regular + sequence + 10 + 5 + + + 0 + 18 + + + + + SQ8 + 8th conversion in regular + sequence + 5 + 5 + + + 0 + 18 + + + + + SQ7 + 7th conversion in regular + sequence + 0 + 5 + + + 0 + 18 + + + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular + sequence + 25 + 5 + + + 0 + 18 + + + + + SQ5 + 5th conversion in regular + sequence + 20 + 5 + + + 0 + 18 + + + + + SQ4 + 4th conversion in regular + sequence + 15 + 5 + + + 0 + 18 + + + + + SQ3 + 3rd conversion in regular + sequence + 10 + 5 + + + 0 + 18 + + + + + SQ2 + 2nd conversion in regular + sequence + 5 + 5 + + + 0 + 18 + + + + + SQ1 + 1st conversion in regular + sequence + 0 + 5 + + + 0 + 18 + + + + + + + JSQR + JSQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + 0 + 3 + + + + + JSQ4 + 4th conversion in injected + sequence + 15 + 5 + + + 0 + 18 + + + + + JSQ3 + 3rd conversion in injected + sequence + 10 + 5 + + + 0 + 18 + + + + + JSQ2 + 2nd conversion in injected + sequence + 5 + 5 + + + 0 + 18 + + + + + JSQ1 + 1st conversion in injected + sequence + 0 + 5 + + + 0 + 18 + + + + + + + 4 + 0x4 + 1-4 + JDR%s + JDR1 + injected data register x + 0x3C + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + DR + DR + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + DATA + Regular data + 0 + 16 + + + + + + + ADC2 + 0x40012100 + + ADC + ADC2 global interrupts + 18 + + + + ADC3 + 0x40012200 + + ADC + ADC3 global interrupts + 18 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C00000 + + + CTS + CTS flag + 9 + 1 + read-write + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NF + Noise detected flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + 0 + 511 + + + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + 0 + 4095 + + + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + 0 + 15 + + + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + OVER8 + Oversampling mode + 15 + 1 + + OVER8 + read-write + + Oversample16 + Oversampling by 16 + 0 + + + Oversample8 + Oversampling by 8 + 1 + + + + + UE + USART enable + 13 + 1 + + UE + read-write + + Disabled + USART prescaler and outputs disabled + 0 + + + Enabled + USART enabled + 1 + + + + + M + Word length + 12 + 1 + + M + read-write + + M8 + 8 data bits + 0 + + + M9 + 9 data bits + 1 + + + + + WAKE + Wakeup method + 11 + 1 + + WAKE + read-write + + IdleLine + USART wakeup on idle line + 0 + + + AddressMark + USART wakeup on address mark + 1 + + + + + PCE + Parity control enable + 10 + 1 + + PCE + read-write + + Disabled + Parity control disabled + 0 + + + Enabled + Parity control enabled + 1 + + + + + PS + Parity selection + 9 + 1 + + PS + read-write + + Even + Even parity + 0 + + + Odd + Odd parity + 1 + + + + + PEIE + PE interrupt enable + 8 + 1 + + PEIE + read-write + + Disabled + PE interrupt disabled + 0 + + + Enabled + PE interrupt enabled + 1 + + + + + TXEIE + TXE interrupt enable + 7 + 1 + + TXEIE + read-write + + Disabled + TXE interrupt disabled + 0 + + + Enabled + TXE interrupt enabled + 1 + + + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + TCIE + read-write + + Disabled + TC interrupt disabled + 0 + + + Enabled + TC interrupt enabled + 1 + + + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + RXNEIE + read-write + + Disabled + RXNE interrupt disabled + 0 + + + Enabled + RXNE interrupt enabled + 1 + + + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + IDLEIE + read-write + + Disabled + IDLE interrupt disabled + 0 + + + Enabled + IDLE interrupt enabled + 1 + + + + + TE + Transmitter enable + 3 + 1 + + TE + read-write + + Disabled + Transmitter disabled + 0 + + + Enabled + Transmitter enabled + 1 + + + + + RE + Receiver enable + 2 + 1 + + RE + read-write + + Disabled + Receiver disabled + 0 + + + Enabled + Receiver enabled + 1 + + + + + RWU + Receiver wakeup + 1 + 1 + + RWU + read-write + + Active + Receiver in active mode + 0 + + + Mute + Receiver in mute mode + 1 + + + + + SBK + Send break + 0 + 1 + + SBK + read-write + + NoBreak + No break character is transmitted + 0 + + + Break + Break character transmitted + 1 + + + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + LINEN + LIN mode enable + 14 + 1 + + LINEN + read-write + + Disabled + LIN mode disabled + 0 + + + Enabled + LIN mode enabled + 1 + + + + + STOP + STOP bits + 12 + 2 + + STOP + read-write + + Stop1 + 1 stop bit + 0 + + + Stop0p5 + 0.5 stop bits + 1 + + + Stop2 + 2 stop bits + 2 + + + Stop1p5 + 1.5 stop bits + 3 + + + + + CLKEN + Clock enable + 11 + 1 + + CLKEN + read-write + + Disabled + CK pin disabled + 0 + + + Enabled + CK pin enabled + 1 + + + + + CPOL + Clock polarity + 10 + 1 + + CPOL + read-write + + Low + Steady low value on CK pin outside transmission window + 0 + + + High + Steady high value on CK pin outside transmission window + 1 + + + + + CPHA + Clock phase + 9 + 1 + + CPHA + read-write + + First + The first clock transition is the first data capture edge + 0 + + + Second + The second clock transition is the first data capture edge + 1 + + + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + LBDIE + read-write + + Disabled + LIN break detection interrupt disabled + 0 + + + Enabled + LIN break detection interrupt enabled + 1 + + + + + LBDL + lin break detection length + 5 + 1 + + LBDL + read-write + + LBDL10 + 10-bit break detection + 0 + + + LBDL11 + 11-bit break detection + 1 + + + + + ADD + Address of the USART node + 0 + 4 + + + 0 + 15 + + + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x00000000 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + ONEBIT + read-write + + Sample3 + Three sample bit method + 0 + + + Sample1 + One sample bit method + 1 + + + + + CTSIE + CTS interrupt enable + 10 + 1 + + CTSIE + read-write + + Disabled + CTS interrupt disabled + 0 + + + Enabled + CTS interrupt enabled + 1 + + + + + CTSE + CTS enable + 9 + 1 + + CTSE + read-write + + Disabled + CTS hardware flow control disabled + 0 + + + Enabled + CTS hardware flow control enabled + 1 + + + + + RTSE + RTS enable + 8 + 1 + + RTSE + read-write + + Disabled + RTS hardware flow control disabled + 0 + + + Enabled + RTS hardware flow control enabled + 1 + + + + + DMAT + DMA enable transmitter + 7 + 1 + + DMAT + read-write + + Disabled + DMA mode is disabled for transmission + 0 + + + Enabled + DMA mode is enabled for transmission + 1 + + + + + DMAR + DMA enable receiver + 6 + 1 + + DMAR + read-write + + Disabled + DMA mode is disabled for reception + 0 + + + Enabled + DMA mode is enabled for reception + 1 + + + + + SCEN + Smartcard mode enable + 5 + 1 + + SCEN + read-write + + Disabled + Smartcard mode disabled + 0 + + + Enabled + Smartcard mode enabled + 1 + + + + + NACK + Smartcard NACK enable + 4 + 1 + + NACK + read-write + + Disabled + NACK transmission in case of parity error is disabled + 0 + + + Enabled + NACK transmission during parity error is enabled + 1 + + + + + HDSEL + Half-duplex selection + 3 + 1 + + HDSEL + read-write + + FullDuplex + Half duplex mode is not selected + 0 + + + HalfDuplex + Half duplex mode is selected + 1 + + + + + IRLP + IrDA low-power + 2 + 1 + + IRLP + read-write + + Normal + Normal mode + 0 + + + LowPower + Low-power mode + 1 + + + + + IREN + IrDA mode enable + 1 + 1 + + IREN + read-write + + Disabled + IrDA disabled + 0 + + + Enabled + IrDA enabled + 1 + + + + + EIE + Error interrupt enable + 0 + 1 + + EIE + read-write + + Disabled + Error interrupt disabled + 0 + + + Enabled + Error interrupt enabled + 1 + + + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt, DAC1 and DAC2 underrun + error interrupt + 54 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt + enable + 29 + 1 + + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + + MAMP2 + DAC channel2 mask/amplitude + selector + 24 + 4 + + + 0 + 15 + + + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable + 22 + 2 + + + + TSEL2 + DAC channel2 trigger + selection + 19 + 3 + + TSEL2 + read-write + + TIM6_TRGO + Timer 6 TRGO event + 0 + + + TIM8_TRGO + Timer 8 TRGO event + 1 + + + TIM7_TRGO + Timer 7 TRGO event + 2 + + + TIM5_TRGO + Timer 5 TRGO event + 3 + + + TIM2_TRGO + Timer 2 TRGO event + 4 + + + TIM4_TRGO + Timer 4 TRGO event + 5 + + + EXTI9 + EXTI line9 + 6 + + + SOFTWARE + Software trigger + 7 + + + + + TEN2 + DAC channel2 trigger + enable + 18 + 1 + + + + BOFF2 + DAC channel2 output buffer + disable + 17 + 1 + + + + EN2 + DAC channel2 enable + 16 + 1 + + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable + 13 + 1 + + DMAUDRIE1 + read-write + + Disabled + DAC channel X DMA Underrun Interrupt disabled + 0 + + + Enabled + DAC channel X DMA Underrun Interrupt enabled + 1 + + + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + DMAEN1 + read-write + + Disabled + DAC channel X DMA mode disabled + 0 + + + Enabled + DAC channel X DMA mode enabled + 1 + + + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + 0 + 15 + + + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + WAVE1 + read-write + + Disabled + Wave generation disabled + 0 + + + Noise + Noise wave generation enabled + 1 + + + Triangle + Triangle wave generation enabled + 2 + + + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + TSEL1 + read-write + + TIM6_TRGO + Timer 6 TRGO event + 0 + + + TIM3_TRGO + Timer 3 TRGO event + 1 + + + TIM7_TRGO + Timer 7 TRGO event + 2 + + + TIM15_TRGO + Timer 15 TRGO event + 3 + + + TIM2_TRGO + Timer 2 TRGO event + 4 + + + EXTI9 + EXTI line9 + 6 + + + SOFTWARE + Software trigger + 7 + + + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + TEN1 + read-write + + Disabled + DAC channel X trigger disabled + 0 + + + Enabled + DAC channel X trigger enabled + 1 + + + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + BOFF1 + read-write + + Enabled + DAC channel X output buffer enabled + 0 + + + Disabled + DAC channel X output buffer disabled + 1 + + + + + EN1 + DAC channel1 enable + 0 + 1 + + EN1 + read-write + + Disabled + DAC channel X disabled + 0 + + + Enabled + DAC channel X enabled + 1 + + + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + SWTRIG1 + write + + Disabled + DAC channel X software trigger disabled + 0 + + + Enabled + DAC channel X software trigger enabled + 1 + + + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding + register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + 0 + 4095 + + + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left aligned data holding + register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + 0 + 4095 + + + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right aligned data holding + register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + 0 + 255 + + + + + + + DHR12R2 + DHR12R2 + channel2 12-bit right aligned data holding + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + 0 + 4095 + + + + + + + DHR12L2 + DHR12L2 + channel2 12-bit left aligned data holding + register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + 0 + 4095 + + + + + + + DHR8R2 + DHR8R2 + channel2 8-bit right-aligned data holding + register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + 0 + 255 + + + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + 0 + 4095 + + + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + 0 + 4095 + + + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 20 + 12 + + + 0 + 4095 + + + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + 0 + 4095 + + + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + 0 + 255 + + + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + 0 + 255 + + + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR2 + DAC channel2 DMA underrun + flag + 29 + 1 + + + + DMAUDR1 + DAC channel1 DMA underrun + flag + 13 + 1 + + DMAUDR1 + read-write + + NoUnderrun + No DMA underrun error condition occurred for DAC channel X + 0 + + + Underrun + DMA underrun error condition occurred for DAC channel X + 1 + + + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + interrupt + 1 + + + + CR + CR + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + FPDS + Flash power down in Stop + mode + 9 + 1 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + PLS + PVD level selection + 5 + 3 + + + PVDE + Power voltage detector + enable + 4 + 1 + + + CSBF + Clear standby flag + 3 + 1 + + + CWUF + Clear wakeup flag + 2 + 1 + + + PDDS + Power down deepsleep + 1 + 1 + + + LPDS + Low-power deep sleep + 0 + 1 + + + + + CSR + CSR + power control/status register + 0x4 + 0x20 + 0x00000000 + + + WUF + Wakeup flag + 0 + 1 + read-only + + + SBF + Standby flag + 1 + 1 + read-only + + + PVDO + PVD output + 2 + 1 + read-only + + + BRR + Backup regulator ready + 3 + 1 + read-only + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + BRE + Backup regulator enable + 9 + 1 + read-write + + + VOSRDY + Regulator voltage scaling output + selection ready bit + 14 + 1 + read-write + + + + + + + I2C3 + 0x40005C00 + + I2C3_EV + I2C3 event interrupt + 72 + + + I2C3_ER + I2C3 error interrupt + 73 + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1 event interrupt + 31 + + + I2C1_ER + I2C1 error interrupt + 32 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + SWRST + Software reset + 15 + 1 + + SWRST + read-write + + NotReset + I2C peripheral not under reset + 0 + + + Reset + I2C peripheral under reset + 1 + + + + + ALERT + SMBus alert + 13 + 1 + + ALERT + read-write + + Release + SMBA pin released high + 0 + + + Drive + SMBA pin driven low + 1 + + + + + PEC + Packet error checking + 12 + 1 + + PEC + read-write + + Disabled + No PEC transfer + 0 + + + Enabled + PEC transfer + 1 + + + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + POS + read-write + + Current + ACK bit controls the (N)ACK of the current byte being received + 0 + + + Next + ACK bit controls the (N)ACK of the next byte to be received + 1 + + + + + ACK + Acknowledge enable + 10 + 1 + + ACK + read-write + + NAK + No acknowledge returned + 0 + + + ACK + Acknowledge returned after a byte is received + 1 + + + + + STOP + Stop generation + 9 + 1 + + STOP + read-write + + NoStop + No Stop generation + 0 + + + Stop + In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte + 1 + + + + + START + Start generation + 8 + 1 + + START + read-write + + NoStart + No Start generation + 0 + + + Start + In master mode: repeated start generation, in slave mode: start generation when bus is free + 1 + + + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + NOSTRETCH + read-write + + Enabled + Clock stretching enabled + 0 + + + Disabled + Clock stretching disabled + 1 + + + + + ENGC + General call enable + 6 + 1 + + ENGC + read-write + + Disabled + General call disabled + 0 + + + Enabled + General call enabled + 1 + + + + + ENPEC + PEC enable + 5 + 1 + + ENPEC + read-write + + Disabled + PEC calculation disabled + 0 + + + Enabled + PEC calculation enabled + 1 + + + + + ENARP + ARP enable + 4 + 1 + + ENARP + read-write + + Disabled + ARP disabled + 0 + + + Enabled + ARP enabled + 1 + + + + + SMBTYPE + SMBus type + 3 + 1 + + SMBTYPE + read-write + + Device + SMBus Device + 0 + + + Host + SMBus Host + 1 + + + + + SMBUS + SMBus mode + 1 + 1 + + SMBUS + read-write + + I2C + I2C Mode + 0 + + + SMBus + SMBus + 1 + + + + + PE + Peripheral enable + 0 + 1 + + PE + read-write + + Disabled + Peripheral disabled + 0 + + + Enabled + Peripheral enabled + 1 + + + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + LAST + DMA last transfer + 12 + 1 + + LAST + read-write + + NotLast + Next DMA EOT is not the last transfer + 0 + + + Last + Next DMA EOT is the last transfer + 1 + + + + + DMAEN + DMA requests enable + 11 + 1 + + DMAEN + read-write + + Disabled + DMA requests disabled + 0 + + + Enabled + DMA request enabled when TxE=1 or RxNE=1 + 1 + + + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + ITBUFEN + read-write + + Disabled + TxE=1 or RxNE=1 does not generate any interrupt + 0 + + + Enabled + TxE=1 or RxNE=1 generates Event interrupt + 1 + + + + + ITEVTEN + Event interrupt enable + 9 + 1 + + ITEVTEN + read-write + + Disabled + Event interrupt disabled + 0 + + + Enabled + Event interrupt enabled + 1 + + + + + ITERREN + Error interrupt enable + 8 + 1 + + ITERREN + read-write + + Disabled + Error interrupt disabled + 0 + + + Enabled + Error interrupt enabled + 1 + + + + + FREQ + Peripheral clock frequency + 0 + 6 + + + 2 + 50 + + + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDMODE + Addressing mode (slave + mode) + 15 + 1 + + ADDMODE + read-write + + ADD7 + 7-bit slave address + 0 + + + ADD10 + 10-bit slave address + 1 + + + + + ADD + Interface address + 0 + 10 + + + 0 + 1023 + + + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADD2 + Interface address + 1 + 7 + + + 0 + 127 + + + + + ENDUAL + Dual addressing mode + enable + 0 + 1 + + ENDUAL + read-write + + Single + Single addressing mode + 0 + + + Dual + Dual addressing mode + 1 + + + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x00000000 + + + DR + 8-bit data register + 0 + 8 + + + 0 + 255 + + + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x00000000 + + + SMBALERT + SMBus alert + 15 + 1 + read-write + zeroToClear + + SMBALERTR + read + + NoAlert + No SMBALERT occured + 0 + + + Alert + SMBALERT occurred + 1 + + + + SMBALERTW + write + + Clear + Clear flag + 0 + + + + + TIMEOUT + Timeout or Tlow error + 14 + 1 + read-write + zeroToClear + + TIMEOUTR + read + + NoTimeout + No Timeout error + 0 + + + Timeout + SCL remained LOW for 25 ms + 1 + + + + TIMEOUTW + write + + Clear + Clear flag + 0 + + + + + PECERR + PEC Error in reception + 12 + 1 + read-write + zeroToClear + + PECERRR + read + + NoError + no PEC error: receiver returns ACK after PEC reception (if ACK=1) + 0 + + + Error + PEC error: receiver returns NACK after PEC reception (whatever ACK) + 1 + + + + PECERRW + write + + Clear + Clear flag + 0 + + + + + OVR + Overrun/Underrun + 11 + 1 + read-write + zeroToClear + + OVRR + read + + NoOverrun + No overrun/underrun occured + 0 + + + Overrun + Overrun/underrun occured + 1 + + + + OVRW + write + + Clear + Clear flag + 0 + + + + + AF + Acknowledge failure + 10 + 1 + read-write + zeroToClear + + AFR + read + + NoFailure + No acknowledge failure + 0 + + + Failure + Acknowledge failure + 1 + + + + AFW + write + + Clear + Clear flag + 0 + + + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + zeroToClear + + ARLOR + read + + NoLost + No Arbitration Lost detected + 0 + + + Lost + Arbitration Lost detected + 1 + + + + ARLOW + write + + Clear + Clear flag + 0 + + + + + BERR + Bus error + 8 + 1 + read-write + zeroToClear + + BERRR + read + + NoError + No misplaced Start or Stop condition + 0 + + + Error + Misplaced Start or Stop condition + 1 + + + + BERRW + write + + Clear + Clear flag + 0 + + + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + TxE + read + + NotEmpty + Data register not empty + 0 + + + Empty + Data register empty + 1 + + + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + RxNE + read + + Empty + Data register empty + 0 + + + NotEmpty + Data register not empty + 1 + + + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + STOPF + read + + NoStop + No Stop condition detected + 0 + + + Stop + Stop condition detected + 1 + + + + + ADD10 + 10-bit header sent (Master + mode) + 3 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + BTF + read + + NotFinished + Data byte transfer not done + 0 + + + Finished + Data byte transfer successful + 1 + + + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + ADDR + read + + NotMatch + Adress mismatched or not received + 0 + + + Match + Received slave address matched with one of the enabled slave addresses + 1 + + + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + SB + read + + NoStart + No Start condition + 0 + + + Start + Start condition generated + 1 + + + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x00000000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + SMBHOST + SMBus host header (Slave + mode) + 6 + 1 + + + SMBDEFAULT + SMBus device default address (Slave + mode) + 5 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x00000000 + + + F_S + I2C master mode selection + 15 + 1 + + F_S + read-write + + Standard + Standard mode I2C + 0 + + + Fast + Fast mode I2C + 1 + + + + + DUTY + Fast mode duty cycle + 14 + 1 + + DUTY + read-write + + Duty2_1 + Duty cycle t_low/t_high = 2/1 + 0 + + + Duty16_9 + Duty cycle t_low/t_high = 16/9 + 1 + + + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + 1 + 4095 + + + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x00000002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + 0 + 63 + + + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read + 0000h) + 0 + 16 + + KEY + write + + Enable + Enable access to PR, RLR and WINR registers (0x5555) + 21845 + + + Reset + Reset the watchdog value (0xAAAA) + 43690 + + + Start + Start the watchdog (0xCCCC) + 52428 + + + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + PR + read-write + + DivideBy4 + Divider /4 + 0 + + + DivideBy8 + Divider /8 + 1 + + + DivideBy16 + Divider /16 + 2 + + + DivideBy32 + Divider /32 + 3 + + + DivideBy64 + Divider /64 + 4 + + + DivideBy128 + Divider /128 + 5 + + + DivideBy256 + Divider /256 + 6 + + + DivideBy256bis + Divider /256 + 7 + + + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + 0 + 4095 + + + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + WDGA + read-write + + Disabled + Watchdog disabled + 0 + + + Enabled + Watchdog enabled + 1 + + + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + 0 + 127 + + + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early wakeup interrupt + 9 + 1 + + EWIW + write + + Enable + interrupt occurs whenever the counter reaches the value 0x40 + 1 + + + + + W + 7-bit window value + 0 + 7 + + + 0 + 127 + + + + + WDGTB + Timer base + 7 + 2 + + WDGTB + read-write + + Div1 + Counter clock (PCLK1 div 4096) div 1 + 0 + + + Div2 + Counter clock (PCLK1 div 4096) div 2 + 1 + + + Div4 + Counter clock (PCLK1 div 4096) div 4 + 2 + + + Div8 + Counter clock (PCLK1 div 4096) div 8 + 3 + + + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + zeroToClear + + EWIFR + read + + Finished + The EWI Interrupt Service Routine has been serviced + 0 + + + Pending + The EWI Interrupt Service Routine has been triggered + 1 + + + + EWIFW + write + + Finished + The EWI Interrupt Service Routine has been serviced + 0 + + + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_WKUP + RTC Wakeup interrupt through the EXTI + line + 3 + + + RTC_Alarm + RTC Alarms (A and B) through EXTI line + interrupt + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + PM + read-write + + AM + AM or 24-hour format + 0 + + + PM + PM + 1 + + + + + HT + Hour tens in BCD format + 20 + 2 + + + 0 + 3 + + + + + HU + Hour units in BCD format + 16 + 4 + + + 0 + 15 + + + + + MNT + Minute tens in BCD format + 12 + 3 + + + 0 + 7 + + + + + MNU + Minute units in BCD format + 8 + 4 + + + 0 + 15 + + + + + ST + Second tens in BCD format + 4 + 3 + + + 0 + 7 + + + + + SU + Second units in BCD format + 0 + 4 + + + 0 + 15 + + + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + 0 + 15 + + + + + YU + Year units in BCD format + 16 + 4 + + + 0 + 15 + + + + + WDU + Week day units + 13 + 3 + + + 1 + 7 + + + + + MT + Month tens in BCD format + 12 + 1 + + MT + read-write + + Zero + Month tens is 0 + 0 + + + One + Month tens is 1 + 1 + + + + + MU + Month units in BCD format + 8 + 4 + + + 0 + 15 + + + + + DT + Date tens in BCD format + 4 + 2 + + + 0 + 3 + + + + + DU + Date units in BCD format + 0 + 4 + + + 0 + 15 + + + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + COE + Calibration output enable + 23 + 1 + + COE + read-write + + Disabled + Calibration output disabled + 0 + + + Enabled + Calibration output enabled + 1 + + + + + OSEL + Output selection + 21 + 2 + + OSEL + read-write + + Disabled + Output disabled + 0 + + + AlarmA + Alarm A output enabled + 1 + + + AlarmB + Alarm B output enabled + 2 + + + Wakeup + Wakeup output enabled + 3 + + + + + POL + Output polarity + 20 + 1 + + POL + read-write + + High + The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + 0 + + + Low + The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + 1 + + + + + BKP + Backup + 18 + 1 + + BKP + read-write + + DST_Not_Changed + Daylight Saving Time change has not been performed + 0 + + + DST_Changed + Daylight Saving Time change has been performed + 1 + + + + + SUB1H + Subtract 1 hour (winter time + change) + 17 + 1 + + SUB1HW + write + + Sub1 + Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + 1 + + + + + ADD1H + Add 1 hour (summer time + change) + 16 + 1 + + ADD1HW + write + + Add1 + Adds 1 hour to the current time. This can be used for summer time change outside initialization mode + 1 + + + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + + TSIE + read-write + + Disabled + Time-stamp Interrupt disabled + 0 + + + Enabled + Time-stamp Interrupt enabled + 1 + + + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + + WUTIE + read-write + + Disabled + Wakeup timer interrupt disabled + 0 + + + Enabled + Wakeup timer interrupt enabled + 1 + + + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + ALRBIE + read-write + + Disabled + Alarm B Interrupt disabled + 0 + + + Enabled + Alarm B Interrupt enabled + 1 + + + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + ALRAIE + read-write + + Disabled + Alarm A interrupt disabled + 0 + + + Enabled + Alarm A interrupt enabled + 1 + + + + + TSE + Time stamp enable + 11 + 1 + + TSE + read-write + + Disabled + Timestamp disabled + 0 + + + Enabled + Timestamp enabled + 1 + + + + + WUTE + Wakeup timer enable + 10 + 1 + + WUTE + read-write + + Disabled + Wakeup timer disabled + 0 + + + Enabled + Wakeup timer enabled + 1 + + + + + ALRBE + Alarm B enable + 9 + 1 + + ALRBE + read-write + + Disabled + Alarm B disabled + 0 + + + Enabled + Alarm B enabled + 1 + + + + + ALRAE + Alarm A enable + 8 + 1 + + ALRAE + read-write + + Disabled + Alarm A disabled + 0 + + + Enabled + Alarm A enabled + 1 + + + + + DCE + Coarse digital calibration + enable + 7 + 1 + + + FMT + Hour format + 6 + 1 + + FMT + read-write + + Twenty_Four_Hour + 24 hour/day format + 0 + + + AM_PM + AM/PM hour format + 1 + + + + + REFCKON + Reference clock detection enable (50 or + 60 Hz) + 4 + 1 + + REFCKON + read-write + + Disabled + RTC_REFIN detection disabled + 0 + + + Enabled + RTC_REFIN detection enabled + 1 + + + + + TSEDGE + Time-stamp event active + edge + 3 + 1 + + TSEDGE + read-write + + RisingEdge + RTC_TS input rising edge generates a time-stamp event + 0 + + + FallingEdge + RTC_TS input falling edge generates a time-stamp event + 1 + + + + + WUCKSEL + Wakeup clock selection + 0 + 3 + + WUCKSEL + read-write + + Div16 + RTC/16 clock is selected + 0 + + + Div8 + RTC/8 clock is selected + 1 + + + Div4 + RTC/4 clock is selected + 2 + + + Div2 + RTC/2 clock is selected + 3 + + + ClockSpare + ck_spre (usually 1 Hz) clock is selected + 4 + + + ClockSpareWithOffset + ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + 6 + + + + + BYPSHAD + Bypass the shadow registers + 5 + 1 + read-write + + BYPSHAD + read-write + + ShadowReg + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles + 0 + + + BypassShadowReg + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters + 1 + + + + + COSEL + Calibration output selection + 19 + 1 + read-write + + COSEL + read-write + + CalFreq_512Hz + Calibration output is 512 Hz (with default prescaler setting) + 0 + + + CalFreq_1Hz + Calibration output is 1 Hz (with default prescaler setting) + 1 + + + + + + + ISR + ISR + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + ALRAWFR + read + + UpdateNotAllowed + Alarm update not allowed + 0 + + + UpdateAllowed + Alarm update allowed + 1 + + + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + WUTWFR + read + + UpdateNotAllowed + Wakeup timer configuration update not allowed + 0 + + + UpdateAllowed + Wakeup timer configuration update allowed + 1 + + + + + SHPF + Shift operation pending + 3 + 1 + read-write + + SHPFR + read + + NoShiftPending + No shift operation is pending + 0 + + + ShiftPending + A shift operation is pending + 1 + + + + + INITS + Initialization status flag + 4 + 1 + read-only + + INITSR + read + + NotInitalized + Calendar has not been initialized + 0 + + + Initalized + Calendar has been initialized + 1 + + + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + zeroToClear + + RSFR + read + + NotSynced + Calendar shadow registers not yet synchronized + 0 + + + Synced + Calendar shadow registers synchronized + 1 + + + + RSFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + INITF + Initialization flag + 6 + 1 + read-only + + INITFR + read + + NotAllowed + Calendar registers update is not allowed + 0 + + + Allowed + Calendar registers update is allowed + 1 + + + + + INIT + Initialization mode + 7 + 1 + read-write + + INIT + read-write + + FreeRunningMode + Free running mode + 0 + + + InitMode + Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + 1 + + + + + ALRAF + Alarm A flag + 8 + 1 + read-write + zeroToClear + + ALRAFR + read + + Match + This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + 1 + + + + ALRAFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + ALRBF + Alarm B flag + 9 + 1 + read-write + zeroToClear + + ALRBFR + read + + Match + This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + 1 + + + + ALRBFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + zeroToClear + + WUTFR + read + + Zero + This flag is set by hardware when the wakeup auto-reload counter reaches 0 + 1 + + + + WUTFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + TSF + Time-stamp flag + 11 + 1 + read-write + zeroToClear + + TSFR + read + + TimestampEvent + This flag is set by hardware when a time-stamp event occurs + 1 + + + + TSFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + zeroToClear + + TSOVFR + read + + Overflow + This flag is set by hardware when a time-stamp event occurs while TSF is already set + 1 + + + + TSOVFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + TAMP1F + Tamper detection flag + 13 + 1 + read-write + zeroToClear + + TAMP1FR + read + + Tampered + This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + 1 + + + + TAMP1FW + write + + Clear + Flag cleared by software writing 0 + 0 + + + + + TAMP2F + TAMPER2 detection flag + 14 + 1 + read-write + zeroToClear + + read + + + write + + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + RECALPFR + read + + Pending + The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + 1 + + + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + 0 + 127 + + + + + PREDIV_S + Synchronous prescaler + factor + 0 + 15 + + + 0 + 32767 + + + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + 0 + 65535 + + + + + + + CALIBR + CALIBR + calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + DCS + Digital calibration sign + 7 + 1 + + + DC + Digital calibration + 0 + 5 + + + + + 2 + 0x4 + A,B + ALRM%sR + ALRMAR + Alarm %s register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm date mask + 31 + 1 + + + + WDSEL + Week day selection + 30 + 1 + + WDSEL + read-write + + DateUnits + DU[3:0] represents the date units + 0 + + + WeekDay + DU[3:0] represents the week day. DT[1:0] is don’t care. + 1 + + + + + DT + Date tens in BCD format + 28 + 2 + + + 0 + 3 + + + + + DU + Date units or day in BCD format + 24 + 4 + + + 0 + 15 + + + + + MSK3 + Alarm hours mask + 23 + 1 + + + + PM + AM/PM notation + 22 + 1 + + PM + read-write + + AM + AM or 24-hour format + 0 + + + PM + PM + 1 + + + + + HT + Hour tens in BCD format + 20 + 2 + + + 0 + 3 + + + + + HU + Hour units in BCD format + 16 + 4 + + + 0 + 15 + + + + + MSK2 + Alarm minutes mask + 15 + 1 + + + + MNT + Minute tens in BCD format + 12 + 3 + + + 0 + 7 + + + + + MNU + Minute units in BCD format + 8 + 4 + + + 0 + 15 + + + + + MSK1 + Alarm seconds mask + 7 + 1 + + MSK1 + read-write + + Mask + Alarm set if the date/day match + 0 + + + NotMask + Date/day don’t care in Alarm comparison + 1 + + + + + ST + Second tens in BCD format + 4 + 3 + + + 0 + 7 + + + + + SU + Second units in BCD format + 0 + 4 + + + 0 + 15 + + + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + 0 + 255 + + + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + 0 + 65535 + + + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + ADD1SW + write + + Add1 + Add one second to the clock/calendar + 1 + + + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + 0 + 32767 + + + + + + + TSTR + TSTR + time stamp time register + 0x30 + + + TSDR + TSDR + time stamp date register + 0x34 + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + CALP + read-write + + NoChange + No RTCCLK pulses are added + 0 + + + IncreaseFreq + One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + 1 + + + + + CALW8 + Use an 8-second calibration cycle + period + 14 + 1 + + CALW8 + read-write + + Eight_Second + When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + 1 + + + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + CALW16 + read-write + + Sixteen_Second + When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + 1 + + + + + CALM + Calibration minus + 0 + 9 + + + 0 + 511 + + + + + + + TAFCR + TAFCR + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + ALARMOUTTYPE + AFO_ALARM output type + 18 + 1 + + + TSINSEL + TIMESTAMP mapping + 17 + 1 + + + TAMP1INSEL + TAMPER1 mapping + 16 + 1 + + + TAMPPUDIS + TAMPER pull-up disable + 15 + 1 + + + TAMPPRCH + Tamper precharge duration + 13 + 2 + + + TAMPFLT + Tamper filter count + 11 + 2 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMP2TRG + Active level for tamper 2 + 4 + 1 + + + TAMP2E + Tamper 2 detection enable + 3 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + + + 2 + 0x4 + A,B + ALRM%sSSR + ALRMASSR + Alarm %s sub-second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + 0 + 15 + + + + + SS + Sub seconds value + 0 + 15 + + + 0 + 32767 + + + + + + + 20 + 0x4 + 0-19 + BKP%sR + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + 0 + 4294967295 + + + + + + + + + UART4 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART4 + UART4 global interrupt + 52 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C00000 + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NF + Noise detected flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + 0 + 511 + + + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + 0 + 4095 + + + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + 0 + 15 + + + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + OVER8 + Oversampling mode + 15 + 1 + + OVER8 + read-write + + Oversample16 + Oversampling by 16 + 0 + + + Oversample8 + Oversampling by 8 + 1 + + + + + UE + USART enable + 13 + 1 + + UE + read-write + + Disabled + USART prescaler and outputs disabled + 0 + + + Enabled + USART enabled + 1 + + + + + M + Word length + 12 + 1 + + M + read-write + + M8 + 8 data bits + 0 + + + M9 + 9 data bits + 1 + + + + + WAKE + Wakeup method + 11 + 1 + + WAKE + read-write + + IdleLine + USART wakeup on idle line + 0 + + + AddressMark + USART wakeup on address mark + 1 + + + + + PCE + Parity control enable + 10 + 1 + + PCE + read-write + + Disabled + Parity control disabled + 0 + + + Enabled + Parity control enabled + 1 + + + + + PS + Parity selection + 9 + 1 + + PS + read-write + + Even + Even parity + 0 + + + Odd + Odd parity + 1 + + + + + PEIE + PE interrupt enable + 8 + 1 + + PEIE + read-write + + Disabled + PE interrupt disabled + 0 + + + Enabled + PE interrupt enabled + 1 + + + + + TXEIE + TXE interrupt enable + 7 + 1 + + TXEIE + read-write + + Disabled + TXE interrupt disabled + 0 + + + Enabled + TXE interrupt enabled + 1 + + + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + TCIE + read-write + + Disabled + TC interrupt disabled + 0 + + + Enabled + TC interrupt enabled + 1 + + + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + RXNEIE + read-write + + Disabled + RXNE interrupt disabled + 0 + + + Enabled + RXNE interrupt enabled + 1 + + + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + IDLEIE + read-write + + Disabled + IDLE interrupt disabled + 0 + + + Enabled + IDLE interrupt enabled + 1 + + + + + TE + Transmitter enable + 3 + 1 + + TE + read-write + + Disabled + Transmitter disabled + 0 + + + Enabled + Transmitter enabled + 1 + + + + + RE + Receiver enable + 2 + 1 + + RE + read-write + + Disabled + Receiver disabled + 0 + + + Enabled + Receiver enabled + 1 + + + + + RWU + Receiver wakeup + 1 + 1 + + RWU + read-write + + Active + Receiver in active mode + 0 + + + Mute + Receiver in mute mode + 1 + + + + + SBK + Send break + 0 + 1 + + SBK + read-write + + NoBreak + No break character is transmitted + 0 + + + Break + Break character transmitted + 1 + + + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + LINEN + LIN mode enable + 14 + 1 + + LINEN + read-write + + Disabled + LIN mode disabled + 0 + + + Enabled + LIN mode enabled + 1 + + + + + STOP + STOP bits + 12 + 2 + + STOP + read-write + + Stop1 + 1 stop bit + 0 + + + Stop2 + 2 stop bits + 2 + + + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + LBDIE + read-write + + Disabled + LIN break detection interrupt disabled + 0 + + + Enabled + LIN break detection interrupt enabled + 1 + + + + + LBDL + lin break detection length + 5 + 1 + + LBDL + read-write + + LBDL10 + 10-bit break detection + 0 + + + LBDL11 + 11-bit break detection + 1 + + + + + ADD + Address of the USART node + 0 + 4 + + + 0 + 15 + + + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x00000000 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + ONEBIT + read-write + + Sample3 + Three sample bit method + 0 + + + Sample1 + One sample bit method + 1 + + + + + DMAT + DMA enable transmitter + 7 + 1 + + DMAT + read-write + + Disabled + DMA mode is disabled for transmission + 0 + + + Enabled + DMA mode is enabled for transmission + 1 + + + + + DMAR + DMA enable receiver + 6 + 1 + + DMAR + read-write + + Disabled + DMA mode is disabled for reception + 0 + + + Enabled + DMA mode is enabled for reception + 1 + + + + + HDSEL + Half-duplex selection + 3 + 1 + + HDSEL + read-write + + FullDuplex + Half duplex mode is not selected + 0 + + + HalfDuplex + Half duplex mode is selected + 1 + + + + + IRLP + IrDA low-power + 2 + 1 + + IRLP + read-write + + Normal + Normal mode + 0 + + + LowPower + Low-power mode + 1 + + + + + IREN + IrDA mode enable + 1 + 1 + + IREN + read-write + + Disabled + IrDA disabled + 0 + + + Enabled + IrDA enabled + 1 + + + + + EIE + Error interrupt enable + 0 + 1 + + EIE + read-write + + Disabled + Error interrupt disabled + 0 + + + Enabled + Error interrupt enabled + 1 + + + + + + + GTPR + Guard Time and Prescaler Register + 0x18 + read-write + + + PSC + IrDA Low-Power pulse width peripheral clock prescaler + 0 + 8 + + + + + + + UART5 + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + ADC_Common + Common ADC registers + ADC_Common + 0x40012300 + + 0x0 + 0x400 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + OVR3 + Overrun flag of ADC3 + 21 + 1 + + + + STRT3 + Regular channel Start flag of ADC + 3 + 20 + 1 + + + + JSTRT3 + Injected channel Start flag of ADC + 3 + 19 + 1 + + + + JEOC3 + Injected channel end of conversion of + ADC 3 + 18 + 1 + + + + EOC3 + End of conversion of ADC 3 + 17 + 1 + + + + AWD3 + Analog watchdog flag of ADC + 3 + 16 + 1 + + + + OVR2 + Overrun flag of ADC 2 + 13 + 1 + + + + STRT2 + Regular channel Start flag of ADC + 2 + 12 + 1 + + + + JSTRT2 + Injected channel Start flag of ADC + 2 + 11 + 1 + + + + JEOC2 + Injected channel end of conversion of + ADC 2 + 10 + 1 + + + + EOC2 + End of conversion of ADC 2 + 9 + 1 + + + + AWD2 + Analog watchdog flag of ADC + 2 + 8 + 1 + + + + OVR1 + Overrun flag of ADC 1 + 5 + 1 + + OVR1 + read + + NoOverrun + No overrun occurred + 0 + + + Overrun + Overrun occurred + 1 + + + + + STRT1 + Regular channel Start flag of ADC + 1 + 4 + 1 + + STRT1 + read + + NotStarted + No regular channel conversion started + 0 + + + Started + Regular channel conversion has started + 1 + + + + + JSTRT1 + Injected channel Start flag of ADC + 1 + 3 + 1 + + JSTRT1 + read + + NotStarted + No injected channel conversion started + 0 + + + Started + Injected channel conversion has started + 1 + + + + + JEOC1 + Injected channel end of conversion of + ADC 1 + 2 + 1 + + JEOC1 + read + + NotComplete + Conversion is not complete + 0 + + + Complete + Conversion complete + 1 + + + + + EOC1 + End of conversion of ADC 1 + 1 + 1 + + EOC1 + read + + NotComplete + Conversion is not complete + 0 + + + Complete + Conversion complete + 1 + + + + + AWD1 + Analog watchdog flag of ADC + 1 + 0 + 1 + + AWD1 + read + + NoEvent + No analog watchdog event occurred + 0 + + + Event + Analog watchdog event occurred + 1 + + + + + + + CCR + CCR + ADC common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT + enable + 23 + 1 + + TSVREFE + read-write + + Disabled + Temperature sensor and V_REFINT channel disabled + 0 + + + Enabled + Temperature sensor and V_REFINT channel enabled + 1 + + + + + VBATE + VBAT enable + 22 + 1 + + VBATE + read-write + + Disabled + V_BAT channel disabled + 0 + + + Enabled + V_BAT channel enabled + 1 + + + + + ADCPRE + ADC prescaler + 16 + 2 + + ADCPRE + read-write + + Div2 + PCLK2 divided by 2 + 0 + + + Div4 + PCLK2 divided by 4 + 1 + + + Div6 + PCLK2 divided by 6 + 2 + + + Div8 + PCLK2 divided by 8 + 3 + + + + + DMA + Direct memory access mode for multi ADC + mode + 14 + 2 + + DMA + read-write + + Disabled + DMA mode disabled + 0 + + + Mode1 + DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3) + 1 + + + Mode2 + DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) + 2 + + + Mode3 + DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) + 3 + + + + + DDS + DMA disable selection for multi-ADC + mode + 13 + 1 + + DDS + read-write + + Single + No new DMA request is issued after the last transfer + 0 + + + Continuous + DMA requests are issued as long as data are converted and DMA=01, 10 or 11 + 1 + + + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + 0 + 15 + + + + + MULTI + Multi ADC mode selection + 0 + 5 + + MULTI + read-write + + Independent + All the ADCs independent: independent mode + 0 + + + DualRJ + Dual ADC1 and ADC2, combined regular and injected simultaneous mode + 1 + + + DualRA + Dual ADC1 and ADC2, combined regular and alternate trigger mode + 2 + + + DualJ + Dual ADC1 and ADC2, injected simultaneous mode only + 5 + + + DualR + Dual ADC1 and ADC2, regular simultaneous mode only + 6 + + + DualI + Dual ADC1 and ADC2, interleaved mode only + 7 + + + DualA + Dual ADC1 and ADC2, alternate trigger mode only + 9 + + + TripleRJ + Triple ADC, regular and injected simultaneous mode + 17 + + + TripleRA + Triple ADC, regular and alternate trigger mode + 18 + + + TripleJ + Triple ADC, injected simultaneous mode only + 21 + + + TripleR + Triple ADC, regular simultaneous mode only + 22 + + + TripleI + Triple ADC, interleaved mode only + 23 + + + TripleA + Triple ADC, alternate trigger mode only + 24 + + + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0x8 + 0x20 + read-only + 0x00000000 + + + DATA2 + 2nd data item of a pair of regular + conversions + 16 + 16 + + + DATA1 + 1st data item of a pair of regular + conversions + 0 + 16 + + + + + + + TIM1 + Advanced-timers + TIM + 0x40010000 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM9 + TIM1 Break interrupt and TIM9 global + interrupt + 24 + + + TIM1_UP_TIM10 + TIM1 Update interrupt and TIM10 global + interrupt + 25 + + + TIM1_TRG_COM_TIM11 + TIM1 Trigger and Commutation interrupts and + TIM11 global interrupt + 26 + + + TIM1_CC + TIM1 Capture Compare interrupt + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + CMS + Center-aligned mode + selection + 5 + 2 + + CMS + read-write + + EdgeAligned + The counter counts up or down depending on the direction bit + 0 + + + CenterAligned1 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + 1 + + + CenterAligned2 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + 2 + + + CenterAligned3 + The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + 3 + + + + + DIR + Direction + 4 + 1 + + DIR + read-write + + Up + Counter used as upcounter + 0 + + + Down + Counter used as downcounter + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + + OIS3N + Output Idle state 3 + 13 + 1 + + + + OIS3 + Output Idle state 3 + 12 + 1 + + + + OIS2N + Output Idle state 2 + 11 + 1 + + + + OIS2 + Output Idle state 2 + 10 + 1 + + + + OIS1N + Output Idle state 1 + 9 + 1 + + OIS1N + read-write + + Reset + OCxN=0 after a dead-time when MOE=0 + 0 + + + Set + OCxN=1 after a dead-time when MOE=0 + 1 + + + + + OIS1 + Output Idle state 1 + 8 + 1 + + OIS1 + read-write + + Reset + OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 + 0 + + + Set + OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 + 1 + + + + + TI1S + TI1 selection + 7 + 1 + + TI1S + read-write + + Normal + The TIMx_CH1 pin is connected to TI1 input + 0 + + + XOR + The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + 1 + + + + + MMS + Master mode selection + 4 + 3 + + MMS + read-write + + Reset + The UG bit from the TIMx_EGR register is used as trigger output + 0 + + + Enable + The counter enable signal, CNT_EN, is used as trigger output + 1 + + + Update + The update event is selected as trigger output + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + 3 + + + CompareOC1 + OC1REF signal is used as trigger output + 4 + + + CompareOC2 + OC2REF signal is used as trigger output + 5 + + + CompareOC3 + OC3REF signal is used as trigger output + 6 + + + CompareOC4 + OC4REF signal is used as trigger output + 7 + + + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + CCDS + read-write + + OnCompare + CCx DMA request sent when CCx event occurs + 0 + + + OnUpdate + CCx DMA request sent when update event occurs + 1 + + + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ETP + External trigger polarity + 15 + 1 + + ETP + read-write + + NotInverted + ETR is noninverted, active at high level or rising edge + 0 + + + Inverted + ETR is inverted, active at low level or falling edge + 1 + + + + + ECE + External clock enable + 14 + 1 + + ECE + read-write + + Disabled + External clock mode 2 disabled + 0 + + + Enabled + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 1 + + + + + ETPS + External trigger prescaler + 12 + 2 + + ETPS + read-write + + Div1 + Prescaler OFF + 0 + + + Div2 + ETRP frequency divided by 2 + 1 + + + Div4 + ETRP frequency divided by 4 + 2 + + + Div8 + ETRP frequency divided by 8 + 3 + + + + + ETF + External trigger filter + 8 + 4 + + ETF + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + MSM + Master/Slave mode + 7 + 1 + + MSM + read-write + + NoSync + No action + 0 + + + Sync + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + TS + Trigger selection + 4 + 3 + + TS + read-write + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + TI1F_ED + TI1 Edge Detector (TI1F_ED) + 4 + + + TI1FP1 + Filtered Timer Input 1 (TI1FP1) + 5 + + + TI2FP2 + Filtered Timer Input 2 (TI2FP2) + 6 + + + ETRF + External Trigger input (ETRF) + 7 + + + + + SMS + Slave mode selection + 0 + 3 + + SMS + read-write + + Disabled + Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + 0 + + + Encoder_Mode_1 + Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + 1 + + + Encoder_Mode_2 + Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + 2 + + + Encoder_Mode_3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 3 + + + Reset_Mode + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 4 + + + Gated_Mode + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 5 + + + Trigger_Mode + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 6 + + + Ext_Clock_Mode + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 7 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + TDE + read-write + + Disabled + Trigger DMA request disabled + 0 + + + Enabled + Trigger DMA request enabled + 1 + + + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + CC1DE + read-write + + Disabled + CCx DMA request disabled + 0 + + + Enabled + CCx DMA request enabled + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + UDE + read-write + + Disabled + Update DMA request disabled + 0 + + + Enabled + Update DMA request enabled + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + TIE + read-write + + Disabled + Trigger interrupt disabled + 0 + + + Enabled + Trigger interrupt enabled + 1 + + + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + CC1IE + read-write + + Disabled + CCx interrupt disabled + 0 + + + Enabled + CCx interrupt enabled + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + zeroToClear + + read + + + write + + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + zeroToClear + + read + + + write + + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + zeroToClear + + read + + + write + + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + zeroToClear + + CC1OFR + read + + Overcapture + The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set + 1 + + + + CC1OFW + write + + Clear + Clear flag + 0 + + + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + zeroToClear + + TIFR + read + + NoTrigger + No trigger event occurred + 0 + + + Trigger + Trigger interrupt pending + 1 + + + + TIFW + write + + Clear + Clear flag + 0 + + + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + zeroToClear + + read + + + write + + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + zeroToClear + + read + + + write + + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + zeroToClear + + read + + + write + + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + zeroToClear + + CC1IFR + read + + Match + If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. + 1 + + + + CC1IFW + write + + Clear + Clear flag + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + TGW + write + + Trigger + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + CC1GW + write + + Trigger + If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. + 1 + + + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + OC2PE + read-write + + Disabled + Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately + 0 + + + Enabled + Preload register on CCR2 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + CC2S + read-write + + Output + CC2 channel is configured as output + 0 + + + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + OC1PE + read-write + + Disabled + Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately + 0 + + + Enabled + Preload register on CCR1 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + CC1S + read-write + + Output + CC1 channel is configured as output + 0 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + 0 + 15 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + CC2S + read-write + + TI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + TI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + TRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + IC1F + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + CC1S + read-write + + TI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + TI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + TRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + OC4PE + read-write + + Disabled + Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately + 0 + + + Enabled + Preload register on CCR4 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + CC4S + read-write + + Output + CC4 channel is configured as output + 0 + + + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + OC3M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + OC3PE + read-write + + Disabled + Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately + 0 + + + Enabled + Preload register on CCR3 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + CC3S + read-write + + Output + CC3 channel is configured as output + 0 + + + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + 0 + 15 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + 0 + 3 + + + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + CC4S + read-write + + TI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + TI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + TRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + IC3F + Input capture 3 filter + 4 + 4 + + + 0 + 15 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + 0 + 3 + + + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + CC3S + read-write + + TI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + TI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + TRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + 0 + 65535 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + 4 + 0x4 + 1-4 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + 0 + 65535 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + 0 + 18 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 8 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + MOE + Main output enable + 15 + 1 + + MOE + read-write + + DisabledIdle + OC/OCN are disabled or forced idle depending on OSSI + 0 + + + Enabled + OC/OCN are enabled if CCxE/CCxNE are set + 1 + + + + + AOE + Automatic output enable + 14 + 1 + + AOE + read-write + + Manual + MOE can be set only by software + 0 + + + Automatic + MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) + 1 + + + + + BKP + Break polarity + 13 + 1 + + BKP + read-write + + ActiveLow + Break input BRKx is active low + 0 + + + ActiveHigh + Break input BRKx is active high + 1 + + + + + BKE + Break enable + 12 + 1 + + BKE + read-write + + Disabled + Break function x disabled + 0 + + + Enabled + Break function x disabled + 1 + + + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + OSSR + read-write + + Disabled + When inactive, OC/OCN outputs are disabled + 0 + + + IdleLevel + When inactive, OC/OCN outputs are enabled with their inactive level + 1 + + + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + OSSI + read-write + + Disabled + When inactive, OC/OCN outputs are disabled + 0 + + + IdleLevel + When inactive, OC/OCN outputs are forced to idle level + 1 + + + + + LOCK + Lock configuration + 8 + 2 + + LOCK + read-write + + Off + No bit is write protected + 0 + + + Level1 + Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written + 1 + + + Level2 + LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written + 2 + + + Level3 + LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written + 3 + + + + + DTG + Dead-time generator setup + 0 + 8 + + + 0 + 255 + + + + + + + + + TIM8 + TIM + 0x40010400 + + TIM8_BRK_TIM12 + TIM8 Break interrupt and TIM12 global + interrupt + 43 + + + TIM8_UP_TIM13 + TIM8 Update interrupt and TIM13 global + interrupt + 44 + + + TIM8_TRG_COM_TIM14 + TIM8 Trigger and Commutation interrupts and + TIM14 global interrupt + 45 + + + TIM8_CC + TIM8 Capture Compare interrupt + 46 + + + + TIM2 + General purpose timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + CMS + Center-aligned mode + selection + 5 + 2 + + CMS + read-write + + EdgeAligned + The counter counts up or down depending on the direction bit + 0 + + + CenterAligned1 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + 1 + + + CenterAligned2 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + 2 + + + CenterAligned3 + The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + 3 + + + + + DIR + Direction + 4 + 1 + + DIR + read-write + + Up + Counter used as upcounter + 0 + + + Down + Counter used as downcounter + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TI1S + TI1 selection + 7 + 1 + + TI1S + read-write + + Normal + The TIMx_CH1 pin is connected to TI1 input + 0 + + + XOR + The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + 1 + + + + + MMS + Master mode selection + 4 + 3 + + MMS + read-write + + Reset + The UG bit from the TIMx_EGR register is used as trigger output + 0 + + + Enable + The counter enable signal, CNT_EN, is used as trigger output + 1 + + + Update + The update event is selected as trigger output + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + 3 + + + CompareOC1 + OC1REF signal is used as trigger output + 4 + + + CompareOC2 + OC2REF signal is used as trigger output + 5 + + + CompareOC3 + OC3REF signal is used as trigger output + 6 + + + CompareOC4 + OC4REF signal is used as trigger output + 7 + + + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + CCDS + read-write + + OnCompare + CCx DMA request sent when CCx event occurs + 0 + + + OnUpdate + CCx DMA request sent when update event occurs + 1 + + + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ETP + External trigger polarity + 15 + 1 + + ETP + read-write + + NotInverted + ETR is noninverted, active at high level or rising edge + 0 + + + Inverted + ETR is inverted, active at low level or falling edge + 1 + + + + + ECE + External clock enable + 14 + 1 + + ECE + read-write + + Disabled + External clock mode 2 disabled + 0 + + + Enabled + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 1 + + + + + ETPS + External trigger prescaler + 12 + 2 + + ETPS + read-write + + Div1 + Prescaler OFF + 0 + + + Div2 + ETRP frequency divided by 2 + 1 + + + Div4 + ETRP frequency divided by 4 + 2 + + + Div8 + ETRP frequency divided by 8 + 3 + + + + + ETF + External trigger filter + 8 + 4 + + ETF + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + MSM + Master/Slave mode + 7 + 1 + + MSM + read-write + + NoSync + No action + 0 + + + Sync + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + TS + Trigger selection + 4 + 3 + + TS + read-write + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + TI1F_ED + TI1 Edge Detector (TI1F_ED) + 4 + + + TI1FP1 + Filtered Timer Input 1 (TI1FP1) + 5 + + + TI2FP2 + Filtered Timer Input 2 (TI2FP2) + 6 + + + ETRF + External Trigger input (ETRF) + 7 + + + + + SMS + Slave mode selection + 0 + 3 + + SMS + read-write + + Disabled + Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + 0 + + + Encoder_Mode_1 + Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + 1 + + + Encoder_Mode_2 + Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + 2 + + + Encoder_Mode_3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 3 + + + Reset_Mode + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 4 + + + Gated_Mode + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 5 + + + Trigger_Mode + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 6 + + + Ext_Clock_Mode + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 7 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + TDE + read-write + + Disabled + Trigger DMA request disabled + 0 + + + Enabled + Trigger DMA request enabled + 1 + + + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + CC1DE + read-write + + Disabled + CCx DMA request disabled + 0 + + + Enabled + CCx DMA request enabled + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + UDE + read-write + + Disabled + Update DMA request disabled + 0 + + + Enabled + Update DMA request enabled + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + TIE + read-write + + Disabled + Trigger interrupt disabled + 0 + + + Enabled + Trigger interrupt enabled + 1 + + + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + CC1IE + read-write + + Disabled + CCx interrupt disabled + 0 + + + Enabled + CCx interrupt enabled + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + zeroToClear + + read + + + write + + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + zeroToClear + + read + + + write + + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + zeroToClear + + read + + + write + + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + zeroToClear + + CC1OFR + read + + Overcapture + The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set + 1 + + + + CC1OFW + write + + Clear + Clear flag + 0 + + + + + TIF + Trigger interrupt flag + 6 + 1 + zeroToClear + + TIFR + read + + NoTrigger + No trigger event occurred + 0 + + + Trigger + Trigger interrupt pending + 1 + + + + TIFW + write + + Clear + Clear flag + 0 + + + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + zeroToClear + + read + + + write + + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + zeroToClear + + read + + + write + + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + zeroToClear + + read + + + write + + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + zeroToClear + + CC1IFR + read + + Match + If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. + 1 + + + + CC1IFW + write + + Clear + Clear flag + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + TG + Trigger generation + 6 + 1 + + TGW + write + + Trigger + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + CC1GW + write + + Trigger + If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. + 1 + + + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + OC2CE + 15 + 1 + + + OC2M + OC2M + 12 + 3 + + + + OC2PE + OC2PE + 11 + 1 + + OC2PE + read-write + + Disabled + Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately + 0 + + + Enabled + Preload register on CCR2 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + CC2S + read-write + + Output + CC2 channel is configured as output + 0 + + + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + OC1M + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC1PE + OC1PE + 3 + 1 + + OC1PE + read-write + + Disabled + Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately + 0 + + + Enabled + Preload register on CCR1 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC1FE + OC1FE + 2 + 1 + + + CC1S + CC1S + 0 + 2 + + CC1S + read-write + + Output + CC1 channel is configured as output + 0 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + 0 + 15 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + CC2S + read-write + + TI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + TI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + TRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + IC1F + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + CC1S + read-write + + TI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + TI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + TRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + O24CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + + OC4PE + OC4PE + 11 + 1 + + OC4PE + read-write + + Disabled + Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately + 0 + + + Enabled + Preload register on CCR4 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + CC4S + read-write + + Output + CC4 channel is configured as output + 0 + + + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + OC3M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC3PE + OC3PE + 3 + 1 + + OC3PE + read-write + + Disabled + Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately + 0 + + + Enabled + Preload register on CCR3 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + CC3S + read-write + + Output + CC3 channel is configured as output + 0 + + + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + 0 + 15 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + 0 + 3 + + + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + CC4S + read-write + + TI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + TI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + TRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + IC3F + Input capture 3 filter + 4 + 4 + + + 0 + 15 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + 0 + 3 + + + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + CC3S + read-write + + TI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + TI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + TRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Counter value + 0 + 32 + + + 0 + 4294967295 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 32 + + + 0 + 4294967295 + + + + + + + 4 + 0x4 + 1-4 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 32 + + + 0 + 4294967295 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + 0 + 18 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + OR + OR + TIM5 option register + 0x50 + 0x20 + read-write + 0x00000000 + + + ITR1_RMP + Timer Input 4 remap + 10 + 2 + + ITR1_RMP + read-write + + TIM8_TRGOUT + TIM8 trigger output is connected to TIM2_ITR1 input + 0 + + + OTG_FS_SOF + OTG FS SOF is connected to the TIM2_ITR1 input + 2 + + + OTG_HS_SOF + OTG HS SOF is connected to the TIM2_ITR1 input + 3 + + + + + + + + + TIM3 + General purpose timers + TIM + 0x40000400 + + 0x0 + 0x400 + registers + + + TIM3 + TIM3 global interrupt + 29 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + CMS + Center-aligned mode + selection + 5 + 2 + + CMS + read-write + + EdgeAligned + The counter counts up or down depending on the direction bit + 0 + + + CenterAligned1 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + 1 + + + CenterAligned2 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + 2 + + + CenterAligned3 + The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + 3 + + + + + DIR + Direction + 4 + 1 + + DIR + read-write + + Up + Counter used as upcounter + 0 + + + Down + Counter used as downcounter + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TI1S + TI1 selection + 7 + 1 + + TI1S + read-write + + Normal + The TIMx_CH1 pin is connected to TI1 input + 0 + + + XOR + The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + 1 + + + + + MMS + Master mode selection + 4 + 3 + + MMS + read-write + + Reset + The UG bit from the TIMx_EGR register is used as trigger output + 0 + + + Enable + The counter enable signal, CNT_EN, is used as trigger output + 1 + + + Update + The update event is selected as trigger output + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + 3 + + + CompareOC1 + OC1REF signal is used as trigger output + 4 + + + CompareOC2 + OC2REF signal is used as trigger output + 5 + + + CompareOC3 + OC3REF signal is used as trigger output + 6 + + + CompareOC4 + OC4REF signal is used as trigger output + 7 + + + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + CCDS + read-write + + OnCompare + CCx DMA request sent when CCx event occurs + 0 + + + OnUpdate + CCx DMA request sent when update event occurs + 1 + + + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ETP + External trigger polarity + 15 + 1 + + ETP + read-write + + NotInverted + ETR is noninverted, active at high level or rising edge + 0 + + + Inverted + ETR is inverted, active at low level or falling edge + 1 + + + + + ECE + External clock enable + 14 + 1 + + ECE + read-write + + Disabled + External clock mode 2 disabled + 0 + + + Enabled + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 1 + + + + + ETPS + External trigger prescaler + 12 + 2 + + ETPS + read-write + + Div1 + Prescaler OFF + 0 + + + Div2 + ETRP frequency divided by 2 + 1 + + + Div4 + ETRP frequency divided by 4 + 2 + + + Div8 + ETRP frequency divided by 8 + 3 + + + + + ETF + External trigger filter + 8 + 4 + + ETF + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + MSM + Master/Slave mode + 7 + 1 + + MSM + read-write + + NoSync + No action + 0 + + + Sync + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + TS + Trigger selection + 4 + 3 + + TS + read-write + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + TI1F_ED + TI1 Edge Detector (TI1F_ED) + 4 + + + TI1FP1 + Filtered Timer Input 1 (TI1FP1) + 5 + + + TI2FP2 + Filtered Timer Input 2 (TI2FP2) + 6 + + + ETRF + External Trigger input (ETRF) + 7 + + + + + SMS + Slave mode selection + 0 + 3 + + SMS + read-write + + Disabled + Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + 0 + + + Encoder_Mode_1 + Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + 1 + + + Encoder_Mode_2 + Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + 2 + + + Encoder_Mode_3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 3 + + + Reset_Mode + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 4 + + + Gated_Mode + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 5 + + + Trigger_Mode + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 6 + + + Ext_Clock_Mode + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 7 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + TDE + read-write + + Disabled + Trigger DMA request disabled + 0 + + + Enabled + Trigger DMA request enabled + 1 + + + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + CC1DE + read-write + + Disabled + CCx DMA request disabled + 0 + + + Enabled + CCx DMA request enabled + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + UDE + read-write + + Disabled + Update DMA request disabled + 0 + + + Enabled + Update DMA request enabled + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + TIE + read-write + + Disabled + Trigger interrupt disabled + 0 + + + Enabled + Trigger interrupt enabled + 1 + + + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + CC1IE + read-write + + Disabled + CCx interrupt disabled + 0 + + + Enabled + CCx interrupt enabled + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + zeroToClear + + read + + + write + + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + zeroToClear + + read + + + write + + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + zeroToClear + + read + + + write + + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + zeroToClear + + CC1OFR + read + + Overcapture + The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set + 1 + + + + CC1OFW + write + + Clear + Clear flag + 0 + + + + + TIF + Trigger interrupt flag + 6 + 1 + zeroToClear + + TIFR + read + + NoTrigger + No trigger event occurred + 0 + + + Trigger + Trigger interrupt pending + 1 + + + + TIFW + write + + Clear + Clear flag + 0 + + + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + zeroToClear + + read + + + write + + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + zeroToClear + + read + + + write + + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + zeroToClear + + read + + + write + + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + zeroToClear + + CC1IFR + read + + Match + If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. + 1 + + + + CC1IFW + write + + Clear + Clear flag + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + TG + Trigger generation + 6 + 1 + + TGW + write + + Trigger + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + CC1GW + write + + Trigger + If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. + 1 + + + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + OC2CE + 15 + 1 + + + OC2M + OC2M + 12 + 3 + + + + OC2PE + OC2PE + 11 + 1 + + OC2PE + read-write + + Disabled + Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately + 0 + + + Enabled + Preload register on CCR2 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + CC2S + read-write + + Output + CC2 channel is configured as output + 0 + + + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + OC1M + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC1PE + OC1PE + 3 + 1 + + OC1PE + read-write + + Disabled + Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately + 0 + + + Enabled + Preload register on CCR1 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC1FE + OC1FE + 2 + 1 + + + CC1S + CC1S + 0 + 2 + + CC1S + read-write + + Output + CC1 channel is configured as output + 0 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + 0 + 15 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + CC2S + read-write + + TI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + TI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + TRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + IC1F + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + CC1S + read-write + + TI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + TI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + TRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + O24CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + + OC4PE + OC4PE + 11 + 1 + + OC4PE + read-write + + Disabled + Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately + 0 + + + Enabled + Preload register on CCR4 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + CC4S + read-write + + Output + CC4 channel is configured as output + 0 + + + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + OC3M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC3PE + OC3PE + 3 + 1 + + OC3PE + read-write + + Disabled + Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately + 0 + + + Enabled + Preload register on CCR3 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + CC3S + read-write + + Output + CC3 channel is configured as output + 0 + + + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + 0 + 15 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + 0 + 3 + + + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + CC4S + read-write + + TI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + TI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + TRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + IC3F + Input capture 3 filter + 4 + 4 + + + 0 + 15 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + 0 + 3 + + + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + CC3S + read-write + + TI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + TI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + TRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + 0 + 65535 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + 4 + 0x4 + 1-4 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + 0 + 65535 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + 0 + 18 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + + + TIM4 + TIM + 0x40000800 + + TIM4 + TIM4 global interrupt + 30 + + + + TIM5 + General-purpose-timers + TIM + 0x40000C00 + + 0x0 + 0x400 + registers + + + TIM5 + TIM5 global interrupt + 50 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + CMS + Center-aligned mode + selection + 5 + 2 + + CMS + read-write + + EdgeAligned + The counter counts up or down depending on the direction bit + 0 + + + CenterAligned1 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + 1 + + + CenterAligned2 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + 2 + + + CenterAligned3 + The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + 3 + + + + + DIR + Direction + 4 + 1 + + DIR + read-write + + Up + Counter used as upcounter + 0 + + + Down + Counter used as downcounter + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TI1S + TI1 selection + 7 + 1 + + TI1S + read-write + + Normal + The TIMx_CH1 pin is connected to TI1 input + 0 + + + XOR + The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + 1 + + + + + MMS + Master mode selection + 4 + 3 + + MMS + read-write + + Reset + The UG bit from the TIMx_EGR register is used as trigger output + 0 + + + Enable + The counter enable signal, CNT_EN, is used as trigger output + 1 + + + Update + The update event is selected as trigger output + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + 3 + + + CompareOC1 + OC1REF signal is used as trigger output + 4 + + + CompareOC2 + OC2REF signal is used as trigger output + 5 + + + CompareOC3 + OC3REF signal is used as trigger output + 6 + + + CompareOC4 + OC4REF signal is used as trigger output + 7 + + + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + CCDS + read-write + + OnCompare + CCx DMA request sent when CCx event occurs + 0 + + + OnUpdate + CCx DMA request sent when update event occurs + 1 + + + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ETP + External trigger polarity + 15 + 1 + + ETP + read-write + + NotInverted + ETR is noninverted, active at high level or rising edge + 0 + + + Inverted + ETR is inverted, active at low level or falling edge + 1 + + + + + ECE + External clock enable + 14 + 1 + + ECE + read-write + + Disabled + External clock mode 2 disabled + 0 + + + Enabled + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 1 + + + + + ETPS + External trigger prescaler + 12 + 2 + + ETPS + read-write + + Div1 + Prescaler OFF + 0 + + + Div2 + ETRP frequency divided by 2 + 1 + + + Div4 + ETRP frequency divided by 4 + 2 + + + Div8 + ETRP frequency divided by 8 + 3 + + + + + ETF + External trigger filter + 8 + 4 + + ETF + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + MSM + Master/Slave mode + 7 + 1 + + MSM + read-write + + NoSync + No action + 0 + + + Sync + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + TS + Trigger selection + 4 + 3 + + TS + read-write + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + TI1F_ED + TI1 Edge Detector (TI1F_ED) + 4 + + + TI1FP1 + Filtered Timer Input 1 (TI1FP1) + 5 + + + TI2FP2 + Filtered Timer Input 2 (TI2FP2) + 6 + + + ETRF + External Trigger input (ETRF) + 7 + + + + + SMS + Slave mode selection + 0 + 3 + + SMS + read-write + + Disabled + Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + 0 + + + Encoder_Mode_1 + Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + 1 + + + Encoder_Mode_2 + Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + 2 + + + Encoder_Mode_3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 3 + + + Reset_Mode + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 4 + + + Gated_Mode + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 5 + + + Trigger_Mode + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 6 + + + Ext_Clock_Mode + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 7 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + TDE + read-write + + Disabled + Trigger DMA request disabled + 0 + + + Enabled + Trigger DMA request enabled + 1 + + + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + CC1DE + read-write + + Disabled + CCx DMA request disabled + 0 + + + Enabled + CCx DMA request enabled + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + UDE + read-write + + Disabled + Update DMA request disabled + 0 + + + Enabled + Update DMA request enabled + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + TIE + read-write + + Disabled + Trigger interrupt disabled + 0 + + + Enabled + Trigger interrupt enabled + 1 + + + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + CC1IE + read-write + + Disabled + CCx interrupt disabled + 0 + + + Enabled + CCx interrupt enabled + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + zeroToClear + + read + + + write + + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + zeroToClear + + read + + + write + + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + zeroToClear + + read + + + write + + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + zeroToClear + + CC1OFR + read + + Overcapture + The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set + 1 + + + + CC1OFW + write + + Clear + Clear flag + 0 + + + + + TIF + Trigger interrupt flag + 6 + 1 + zeroToClear + + TIFR + read + + NoTrigger + No trigger event occurred + 0 + + + Trigger + Trigger interrupt pending + 1 + + + + TIFW + write + + Clear + Clear flag + 0 + + + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + zeroToClear + + read + + + write + + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + zeroToClear + + read + + + write + + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + zeroToClear + + read + + + write + + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + zeroToClear + + CC1IFR + read + + Match + If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. + 1 + + + + CC1IFW + write + + Clear + Clear flag + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + TG + Trigger generation + 6 + 1 + + TGW + write + + Trigger + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + CC1GW + write + + Trigger + If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. + 1 + + + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + OC2CE + 15 + 1 + + + OC2M + OC2M + 12 + 3 + + + + OC2PE + OC2PE + 11 + 1 + + OC2PE + read-write + + Disabled + Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately + 0 + + + Enabled + Preload register on CCR2 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + CC2S + read-write + + Output + CC2 channel is configured as output + 0 + + + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + OC1M + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC1PE + OC1PE + 3 + 1 + + OC1PE + read-write + + Disabled + Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately + 0 + + + Enabled + Preload register on CCR1 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC1FE + OC1FE + 2 + 1 + + + CC1S + CC1S + 0 + 2 + + CC1S + read-write + + Output + CC1 channel is configured as output + 0 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + 0 + 15 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + CC2S + read-write + + TI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + TI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + TRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + IC1F + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + CC1S + read-write + + TI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + TI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + TRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + O24CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + + OC4PE + OC4PE + 11 + 1 + + OC4PE + read-write + + Disabled + Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately + 0 + + + Enabled + Preload register on CCR4 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + CC4S + read-write + + Output + CC4 channel is configured as output + 0 + + + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + OC3M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC3PE + OC3PE + 3 + 1 + + OC3PE + read-write + + Disabled + Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately + 0 + + + Enabled + Preload register on CCR3 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + CC3S + read-write + + Output + CC3 channel is configured as output + 0 + + + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + 0 + 15 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + 0 + 3 + + + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + CC4S + read-write + + TI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + TI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + TRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + IC3F + Input capture 3 filter + 4 + 4 + + + 0 + 15 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + 0 + 3 + + + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + CC3S + read-write + + TI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + TI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + TRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Counter value + 0 + 32 + + + 0 + 4294967295 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 32 + + + 0 + 4294967295 + + + + + + + 4 + 0x4 + 1-4 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 32 + + + 0 + 4294967295 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + 0 + 18 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + OR + OR + TIM5 option register + 0x50 + 0x20 + read-write + 0x00000000 + + + IT4_RMP + Timer Input 4 remap + 6 + 2 + + + + + + + TIM9 + General purpose timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM9 + TIM1 Break interrupt and TIM9 global + interrupt + 24 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS + Master mode selection + 4 + 3 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + TG + Trigger generation + 6 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 3 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 3 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + 2 + 0x4 + 1-2 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + + + + + TIM12 + TIM + 0x40001800 + + TIM8_BRK_TIM12 + TIM8 Break interrupt and TIM12 global + interrupt + 43 + + + + TIM10 + General-purpose-timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + TIM1_UP_TIM10 + TIM1 Update interrupt and TIM10 global + interrupt + 25 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + 1 + 0x4 + 1-1 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + + + + + TIM13 + TIM + 0x40001C00 + + TIM8_UP_TIM13 + TIM8 Update interrupt and TIM13 global + interrupt + 44 + + + + TIM14 + TIM + 0x40002000 + + TIM8_TRG_COM_TIM14 + TIM8 Trigger and Commutation interrupts and + TIM14 global interrupt + 45 + + + + TIM11 + General-purpose-timers + TIM + 0x40014800 + + 0x0 + 0x400 + registers + + + TIM1_TRG_COM_TIM11 + TIM1 Trigger and Commutation interrupts and + TIM11 global interrupt + 26 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + 1 + 0x4 + 1-1 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + + + OR + OR + option register + 0x50 + 0x20 + read-write + 0x00000000 + + + RMP + Input 1 remapping + capability + 0 + 2 + + + + + + + TIM6 + Basic timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt, DAC1 and DAC2 underrun + error interrupt + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS + Master mode selection + 4 + 3 + + MMS + read-write + + Reset + Use UG bit from TIMx_EGR register + 0 + + + Enable + Use CNT bit from TIMx_CEN register + 1 + + + Update + Use the update event + 2 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + UDE + Update DMA request enable + 8 + 1 + + UDE + read-write + + Disabled + Update DMA request disabled + 0 + + + Enabled + Update DMA request enabled + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Low counter value + 0 + 16 + + + 0 + 65535 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Low Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + + + TIM7 + TIM + 0x40001400 + + TIM7 + TIM7 global interrupt + 55 + + + + CRC + Cryptographic processor + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + 0 + 4294967295 + + + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + 0 + 255 + + + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Control regidter + 0 + 1 + + RESETW + write + + Reset + Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF + 1 + + + + + + + + + OTG_FS_GLOBAL + USB on the go full speed + USB_OTG_FS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTG_FS_WKUP + USB On-The-Go FS Wakeup through EXTI line + interrupt + 42 + + + OTG_FS + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTG_FS control and status register + (OTG_FS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTG_FS interrupt register + (OTG_FS_GOTGINT) + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + GAHBCFG + GAHBCFG + OTG_FS AHB configuration register + (OTG_FS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GINT + Global interrupt mask + 0 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + OTG_FS USB configuration register + (OTG_FS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + Full Speed serial transceiver + select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + FHMOD + Force host mode + 29 + 1 + read-write + + + FDMOD + Force device mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTG_FS reset register + (OTG_FS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTG_FS core interrupt register + (OTG_FS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFE + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + IPXFR_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEM + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + IPXFRM_IISOOXFRM + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-write + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTG_FS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTG status debug read (host mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTG_FS Receive FIFO size register + (OTG_FS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + OTG_FS non-periodic transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + HNPTXFSIZ + HNPTXFSIZ + OTG_FS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSA + Non-periodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTG_FS non-periodic transmit FIFO/queue + status register (OTG_FS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSAV + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTG_FS general core configuration register + (OTG_FS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDWN + Power down + 16 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing + device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + NOVBUSSENS + Vbus sensing disable option + 21 + 1 + + + + + CID + CID + core ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTG_FS Host periodic transmit FIFO size + register (OTG_FS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZ + Host periodic TxFIFO depth + 16 + 16 + + + + + 5 + 0x4 + 1-5 + DIEPTXF%s + DIEPTXF1 + OTF_FS device IN endpoint transmit FIFO size register + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + GRXSTSP_Device + OTG status read and pop (device mode) + 0x20 + 0x20 + read-only + 0x00000000 + + + FRMNUM + Frame number + 21 + 4 + + + PKTSTS + Packet status + 17 + 4 + + + DPID + Data PID + 15 + 2 + + + BCNT + Byte count + 4 + 11 + + + EPNUM + Endpoint number + 0 + 4 + + + + + GRXSTSP_Host + OTG status read and pop (host mode) + GRXSTSP_Device + 0x20 + 0x20 + read-only + 0x00000000 + + + PKTSTS + Packet status + 17 + 4 + + + DPID + Data PID + 15 + 2 + + + BCNT + Byte count + 4 + 11 + + + CHNUM + Channel number + 0 + 4 + + + + + + + OTG_FS_HOST + USB on the go full speed + USB_OTG_FS + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTG_FS host configuration register + (OTG_FS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-write + + + + + HFIR + HFIR + OTG_FS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTG_FS host frame number/frame time + remaining register (OTG_FS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTG_FS_Host periodic transmit FIFO/queue + status register (OTG_FS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTG_FS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTG_FS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTG_FS host port control and status register + (OTG_FS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + 12 + 0x20 + 0-11 + HC%s + Host channel + 0x100 + + CHAR + HCCHAR0 + OTG_FS host channel-0 characteristics + register (OTG_FS_HCCHAR0) + 0x0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + INT + HCINT0 + OTG_FS host channel-0 interrupt register + (OTG_FS_HCINT0) + 0x8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + INTMSK + HCINTMSK0 + OTG_FS host channel-0 mask register + (OTG_FS_HCINTMSK0) + 0xC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + TSIZ + HCTSIZ0 + OTG_FS host channel-0 transfer size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + + + + OTG_FS_DEVICE + USB on the go full speed + USB_OTG_FS + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTG_FS device configuration register + (OTG_FS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Non-zero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTG_FS device control register + (OTG_FS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + read-write + + + CGINAK + Clear global IN NAK + 8 + 1 + read-write + + + SGONAK + Set global OUT NAK + 9 + 1 + read-write + + + CGONAK + Clear global OUT NAK + 10 + 1 + read-write + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTG_FS device status register + (OTG_FS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTG_FS device IN endpoint common interrupt + mask register (OTG_FS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + + + DOEPMSK + DOEPMSK + OTG_FS device OUT endpoint common interrupt + mask register (OTG_FS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + + + DAINT + DAINT + OTG_FS device all endpoints interrupt + register (OTG_FS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTG_FS all endpoints interrupt mask register + (OTG_FS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + OTG_FS device VBUS discharge time + register + 0x28 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + OTG_FS device VBUS pulsing time + register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTG_FS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEP0 + Device IN endpoint 0 + 0x100 + + CTL + DIEPCTL0 + OTG_FS device control IN endpoint 0 control + register (OTG_FS_DIEPCTL0) + 0x0 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + INT + DIEPINT0 + device endpoint-x interrupt + register + 0x8 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + TSIZ + DIEPTSIZ0 + device endpoint-0 transfer size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PKTCNT + Packet count + 19 + 2 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + TXFSTS + DTXFSTS0 + OTG_FS device IN endpoint transmit FIFO + status register + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + + 5 + 0x20 + 1-5 + DIEP%s + Device IN endpoint X + 0x120 + + CTL + DIEPCTL1 + OTG device endpoint-1 control + register + 0x0 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM_SD1PID + SODDFRM/SD1PID + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + INT + DIEPINT1 + device endpoint-1 interrupt + register + 0x8 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + TSIZ + DIEPTSIZ1 + device endpoint-1 transfer size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + TXFSTS + DTXFSTS1 + OTG_FS device IN endpoint transmit FIFO + status register + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + + DOEP0 + Device OUT endpoint 0 + 0x300 + + CTL + DOEPCTL0 + device endpoint-0 control + register + 0x0 + 0x20 + 0x00008000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-only + + + MPSIZ + MPSIZ + 0 + 2 + read-only + + + + + INT + DOEPINT0 + device endpoint-0 interrupt + register + 0x8 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + TSIZ + DOEPTSIZ0 + device OUT endpoint-0 transfer size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + STUPCNT + SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 1 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + + 5 + 0x20 + 1-5 + DOEP%s + Device IN endpoint X + 0x320 + + CTL + DOEPCTL1 + device endpoint-1 control + register + 0x0 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + INT + DOEPINT1 + device endpoint-1 interrupt + register + 0x8 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + TSIZ + DOEPTSIZ1 + device OUT endpoint-1 transfer size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + + + + OTG_FS_PWRCLK + USB on the go full speed + USB_OTG_FS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTG_FS power and clock gating control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY Suspended + 4 + 1 + + + + + + + CAN1 + Controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupts + 19 + + + CAN1_RX0 + CAN1 RX0 interrupts + 20 + + + CAN1_RX1 + CAN1 RX1 interrupts + 21 + + + CAN1_SCE + CAN1 SCE interrupt + 22 + + + + MCR + MCR + master control register + 0x0 + 0x20 + read-write + 0x00010002 + + + DBF + DBF + 16 + 1 + + + RESET + RESET + 15 + 1 + + + TTCM + TTCM + 7 + 1 + + + ABOM + ABOM + 6 + 1 + + + AWUM + AWUM + 5 + 1 + + + NART + NART + 4 + 1 + + + RFLM + RFLM + 3 + 1 + + + TXFP + TXFP + 2 + 1 + + + SLEEP + SLEEP + 1 + 1 + + + INRQ + INRQ + 0 + 1 + + + + + MSR + MSR + master status register + 0x4 + 0x20 + 0x00000C02 + + + RX + RX + 11 + 1 + read-only + + + SAMP + SAMP + 10 + 1 + read-only + + + RXM + RXM + 9 + 1 + read-only + + + TXM + TXM + 8 + 1 + read-only + + + SLAKI + SLAKI + 4 + 1 + read-write + + + WKUI + WKUI + 3 + 1 + read-write + + + ERRI + ERRI + 2 + 1 + read-write + + + SLAK + SLAK + 1 + 1 + read-only + + + INAK + INAK + 0 + 1 + read-only + + + + + TSR + TSR + transmit status register + 0x8 + 0x20 + 0x1C000000 + + + 3 + 0x1 + 0-2 + LOW%s + Lowest priority flag for mailbox + %s + 29 + 1 + read-only + + + 3 + 0x1 + 0-2 + TME%s + Lowest priority flag for mailbox + %s + 26 + 1 + read-only + + + CODE + CODE + 24 + 2 + read-only + + + ABRQ2 + ABRQ2 + 23 + 1 + read-write + + + TERR2 + TERR2 + 19 + 1 + read-write + + + ALST2 + ALST2 + 18 + 1 + read-write + + + TXOK2 + TXOK2 + 17 + 1 + read-write + + + RQCP2 + RQCP2 + 16 + 1 + read-write + + + ABRQ1 + ABRQ1 + 15 + 1 + read-write + + + TERR1 + TERR1 + 11 + 1 + read-write + + + ALST1 + ALST1 + 10 + 1 + read-write + + + TXOK1 + TXOK1 + 9 + 1 + read-write + + + RQCP1 + RQCP1 + 8 + 1 + read-write + + + ABRQ0 + ABRQ0 + 7 + 1 + read-write + + + TERR0 + TERR0 + 3 + 1 + read-write + + + ALST0 + ALST0 + 2 + 1 + read-write + + + TXOK0 + TXOK0 + 1 + 1 + read-write + + + RQCP0 + RQCP0 + 0 + 1 + read-write + + + + + 2 + 0x4 + 0-1 + RF%sR + RF0R + receive FIFO %s register + 0xC + 0x20 + 0x00000000 + + + RFOM + RFOM0 + 5 + 1 + read-write + + RFOM0W + write + + Release + Set by software to release the output mailbox of the FIFO + 1 + + + + + FOVR + FOVR0 + 4 + 1 + read-write + + FOVR0R + read + + NoOverrun + No FIFO x overrun + 0 + + + Overrun + FIFO x overrun + 1 + + + + FOVR0W + write + + Clear + Clear flag + 1 + + + + + FULL + FULL0 + 3 + 1 + read-write + + FULL0R + read + + NotFull + FIFO x is not full + 0 + + + Full + FIFO x is full + 1 + + + + FULL0W + write + + Clear + Clear flag + 1 + + + + + FMP + FMP0 + 0 + 2 + read-only + + + + + IER + IER + interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLKIE + SLKIE + 17 + 1 + + SLKIE + read-write + + Disabled + No interrupt when SLAKI bit is set + 0 + + + Enabled + Interrupt generated when SLAKI bit is set + 1 + + + + + WKUIE + WKUIE + 16 + 1 + + WKUIE + read-write + + Disabled + No interrupt when WKUI is set + 0 + + + Enabled + Interrupt generated when WKUI bit is set + 1 + + + + + ERRIE + ERRIE + 15 + 1 + + ERRIE + read-write + + Disabled + No interrupt will be generated when an error condition is pending in the CAN_ESR + 0 + + + Enabled + An interrupt will be generation when an error condition is pending in the CAN_ESR + 1 + + + + + LECIE + LECIE + 11 + 1 + + LECIE + read-write + + Disabled + ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection + 0 + + + Enabled + ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection + 1 + + + + + BOFIE + BOFIE + 10 + 1 + + BOFIE + read-write + + Disabled + ERRI bit will not be set when BOFF is set + 0 + + + Enabled + ERRI bit will be set when BOFF is set + 1 + + + + + EPVIE + EPVIE + 9 + 1 + + EPVIE + read-write + + Disabled + ERRI bit will not be set when EPVF is set + 0 + + + Enabled + ERRI bit will be set when EPVF is set + 1 + + + + + EWGIE + EWGIE + 8 + 1 + + EWGIE + read-write + + Disabled + ERRI bit will not be set when EWGF is set + 0 + + + Enabled + ERRI bit will be set when EWGF is set + 1 + + + + + FOVIE1 + FOVIE1 + 6 + 1 + + FOVIE1 + read-write + + Disabled + No interrupt when FOVR is set + 0 + + + Enabled + Interrupt generation when FOVR is set + 1 + + + + + FFIE1 + FFIE1 + 5 + 1 + + FFIE1 + read-write + + Disabled + No interrupt when FULL bit is set + 0 + + + Enabled + Interrupt generated when FULL bit is set + 1 + + + + + FMPIE1 + FMPIE1 + 4 + 1 + + FMPIE1 + read-write + + Disabled + No interrupt generated when state of FMP[1:0] bits are not 00b + 0 + + + Enabled + Interrupt generated when state of FMP[1:0] bits are not 00b + 1 + + + + + FOVIE0 + FOVIE0 + 3 + 1 + + FOVIE0 + read-write + + Disabled + No interrupt when FOVR bit is set + 0 + + + Enabled + Interrupt generated when FOVR bit is set + 1 + + + + + FFIE0 + FFIE0 + 2 + 1 + + FFIE0 + read-write + + Disabled + No interrupt when FULL bit is set + 0 + + + Enabled + Interrupt generated when FULL bit is set + 1 + + + + + FMPIE0 + FMPIE0 + 1 + 1 + + FMPIE0 + read-write + + Disabled + No interrupt generated when state of FMP[1:0] bits are not 00 + 0 + + + Enabled + Interrupt generated when state of FMP[1:0] bits are not 00b + 1 + + + + + TMEIE + TMEIE + 0 + 1 + + TMEIE + read-write + + Disabled + No interrupt when RQCPx bit is set + 0 + + + Enabled + Interrupt generated when RQCPx bit is set + 1 + + + + + + + ESR + ESR + interrupt enable register + 0x18 + 0x20 + 0x00000000 + + + REC + REC + 24 + 8 + read-only + + + TEC + TEC + 16 + 8 + read-only + + + LEC + LEC + 4 + 3 + read-write + + LEC + read-write + + NoError + No Error + 0 + + + Stuff + Stuff Error + 1 + + + Form + Form Error + 2 + + + Ack + Acknowledgment Error + 3 + + + BitRecessive + Bit recessive Error + 4 + + + BitDominant + Bit dominant Error + 5 + + + Crc + CRC Error + 6 + + + Custom + Set by software + 7 + + + + + BOFF + BOFF + 2 + 1 + read-only + + + EPVF + EPVF + 1 + 1 + read-only + + + EWGF + EWGF + 0 + 1 + read-only + + + + + BTR + BTR + bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + SILM + SILM + 31 + 1 + + SILM + read-write + + Normal + Normal operation + 0 + + + Silent + Silent Mode + 1 + + + + + LBKM + LBKM + 30 + 1 + + LBKM + read-write + + Disabled + Loop Back Mode disabled + 0 + + + Enabled + Loop Back Mode enabled + 1 + + + + + SJW + SJW + 24 + 2 + + + TS2 + TS2 + 20 + 3 + + + TS1 + TS1 + 16 + 4 + + + BRP + BRP + 0 + 10 + + + + + 3 + 0x10 + 0-2 + TX%s + CAN Transmit cluster + 0x180 + + TIR + TI0R + TX mailbox identifier register + 0x0 + 0x20 + read-write + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + IDE + read-write + + Standard + Standard identifier + 0 + + + Extended + Extended identifier + 1 + + + + + RTR + RTR + 1 + 1 + + RTR + read-write + + Data + Data frame + 0 + + + Remote + Remote frame + 1 + + + + + TXRQ + TXRQ + 0 + 1 + + + + + TDTR + TDT0R + mailbox data length control and time stamp + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TIME + TIME + 16 + 16 + + + TGT + TGT + 8 + 1 + + + DLC + DLC + 0 + 4 + + + 0 + 8 + + + + + + + TDLR + TDL0R + mailbox data low register + 0x8 + 0x20 + read-write + 0x00000000 + + + 4 + 0x8 + 0-3 + DATA%s + DATA%s + 0 + 8 + + + + + TDHR + TDH0R + mailbox data high register + 0xC + 0x20 + read-write + 0x00000000 + + + 4 + 0x8 + 4-7 + DATA%s + DATA%s + 0 + 8 + + + + + + 2 + 0x10 + 0-1 + RX%s + CAN Receive cluster + 0x1B0 + + RIR + RI0R + receive FIFO mailbox identifier + register + 0x0 + 0x20 + read-only + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + IDE + read + + Standard + Standard identifier + 0 + + + Extended + Extended identifier + 1 + + + + + RTR + RTR + 1 + 1 + + RTR + read + + Data + Data frame + 0 + + + Remote + Remote frame + 1 + + + + + + + RDTR + RDT0R + mailbox data high register + 0x4 + 0x20 + read-only + 0x00000000 + + + TIME + TIME + 16 + 16 + + + FMI + FMI + 8 + 8 + + + DLC + DLC + 0 + 4 + + + 0 + 8 + + + + + + + RDLR + RDL0R + mailbox data high register + 0x8 + 0x20 + read-only + 0x00000000 + + + 4 + 0x8 + 0-3 + DATA%s + DATA%s + 0 + 8 + + + + + RDHR + RDH0R + receive FIFO mailbox data high + register + 0xC + 0x20 + read-only + 0x00000000 + + + 4 + 0x8 + 4-7 + DATA%s + DATA%s + 0 + 8 + + + + + + FMR + FMR + filter master register + 0x200 + 0x20 + read-write + 0x2A1C0E01 + + + CAN2SB + CAN2SB + 8 + 6 + + + FINIT + FINIT + 0 + 1 + + + + + FM1R + FM1R + filter mode register + 0x204 + 0x20 + read-write + 0x00000000 + + + 28 + 0x1 + 0-27 + FBM%s + Filter mode + 0 + 1 + + + + + FS1R + FS1R + filter scale register + 0x20C + 0x20 + read-write + 0x00000000 + + + 28 + 0x1 + 0-27 + FSC%s + Filter scale configuration + 0 + 1 + + + + + FFA1R + FFA1R + filter FIFO assignment + register + 0x214 + 0x20 + read-write + 0x00000000 + + + 28 + 0x1 + 0-27 + FFA%s + Filter FIFO assignment for filter %s + 0 + 1 + + + + + FA1R + FA1R + filter activation register + 0x21C + 0x20 + read-write + 0x00000000 + + + 28 + 0x1 + 0-27 + FACT%s + Filter active + 0 + 1 + + + + + 28 + 0x8 + 0-27 + FB%s + CAN Filter Bank cluster + 0x240 + + FR1 + F0R1 + Filter bank x register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + FB + Filter bits + 0 + 32 + + + + + FR2 + F0R2 + Filter bank x register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + FB + Filter bits + 0 + 32 + + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupts + 63 + + + CAN2_RX0 + CAN2 RX0 interrupts + 64 + + + CAN2_RX1 + CAN2 RX1 interrupts + 65 + + + CAN2_SCE + CAN2 SCE interrupt + 66 + + + + FLASH + FLASH + FLASH + 0x40023C00 + + 0x0 + 0x400 + registers + + + + ACR + ACR + Flash access control register + 0x0 + 0x20 + 0x00000000 + + + LATENCY + Latency + 0 + 3 + read-write + + LATENCY + read-write + + WS0 + 0 wait states + 0 + + + WS1 + 1 wait states + 1 + + + WS2 + 2 wait states + 2 + + + WS3 + 3 wait states + 3 + + + WS4 + 4 wait states + 4 + + + WS5 + 5 wait states + 5 + + + WS6 + 6 wait states + 6 + + + WS7 + 7 wait states + 7 + + + + + PRFTEN + Prefetch enable + 8 + 1 + read-write + + PRFTEN + read-write + + Disabled + Prefetch is disabled + 0 + + + Enabled + Prefetch is enabled + 1 + + + + + ICEN + Instruction cache enable + 9 + 1 + read-write + + ICEN + read-write + + Disabled + Instruction cache is disabled + 0 + + + Enabled + Instruction cache is enabled + 1 + + + + + DCEN + Data cache enable + 10 + 1 + read-write + + DCEN + read-write + + Disabled + Data cache is disabled + 0 + + + Enabled + Data cache is enabled + 1 + + + + + ICRST + Instruction cache reset + 11 + 1 + write-only + + ICRST + write + + NotReset + Instruction cache is not reset + 0 + + + Reset + Instruction cache is reset + 1 + + + + + DCRST + Data cache reset + 12 + 1 + read-write + + DCRST + read-write + + NotReset + Data cache is not reset + 0 + + + Reset + Data cache is reset + 1 + + + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEY + FPEC key + 0 + 32 + + + 0 + 4294967295 + + + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + 0 + 4294967295 + + + + + + + SR + SR + Status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 0 + 1 + read-write + oneToClear + + EOPW + write + + Clear + Clear error flag + 1 + + + + + OPERR + Operation error + 1 + 1 + read-write + oneToClear + + OPERRW + write + + Clear + Clear error flag + 1 + + + + + WRPERR + Write protection error + 4 + 1 + read-write + oneToClear + + WRPERRW + write + + Clear + Clear error flag + 1 + + + + + PGAERR + Programming alignment + error + 5 + 1 + read-write + oneToClear + + PGAERRW + write + + Clear + Clear error flag + 1 + + + + + PGPERR + Programming parallelism + error + 6 + 1 + read-write + oneToClear + + PGPERRW + write + + Clear + Clear error flag + 1 + + + + + PGSERR + Programming sequence error + 7 + 1 + read-write + oneToClear + + PGSERRW + write + + Clear + Clear error flag + 1 + + + + + BSY + Busy + 16 + 1 + read-only + + BSYR + read + + NotBusy + no Flash memory operation ongoing + 0 + + + Busy + Flash memory operation ongoing + 1 + + + + + + + CR + CR + Control register + 0x10 + 0x20 + read-write + 0x80000000 + + + PG + Programming + 0 + 1 + + PG + read-write + + Program + Flash programming activated + 1 + + + + + SER + Sector Erase + 1 + 1 + + SER + read-write + + SectorErase + Erase activated for selected sector + 1 + + + + + MER + Mass Erase + 2 + 1 + + MER + read-write + + MassErase + Erase activated for all user sectors + 1 + + + + + SNB + Sector number + 3 + 4 + + + 0 + 11 + + + + + PSIZE + Program size + 8 + 2 + + PSIZE + read-write + + PSIZE8 + Program x8 + 0 + + + PSIZE16 + Program x16 + 1 + + + PSIZE32 + Program x32 + 2 + + + PSIZE64 + Program x64 + 3 + + + + + STRT + Start + 16 + 1 + + STRT + read-write + + Start + Trigger an erase operation + 1 + + + + + EOPIE + End of operation interrupt + enable + 24 + 1 + + EOPIE + read-write + + Disabled + End of operation interrupt disabled + 0 + + + Enabled + End of operation interrupt enabled + 1 + + + + + ERRIE + Error interrupt enable + 25 + 1 + + ERRIE + read-write + + Disabled + Error interrupt generation disabled + 0 + + + Enabled + Error interrupt generation enabled + 1 + + + + + LOCK + Lock + 31 + 1 + + LOCK + read-write + + Unlocked + FLASH_CR register is unlocked + 0 + + + Locked + FLASH_CR register is locked + 1 + + + + + + + OPTCR + OPTCR + Flash option control register + 0x14 + 0x20 + read-write + 0x00000014 + + + OPTLOCK + Option lock + 0 + 1 + + + OPTSTRT + Option start + 1 + 1 + + + BOR_LEV + BOR reset Level + 2 + 2 + + + WDG_SW + WDG_SW User option bytes + 5 + 1 + + + nRST_STOP + nRST_STOP User option + bytes + 6 + 1 + + + nRST_STDBY + nRST_STDBY User option + bytes + 7 + 1 + + + RDP + Read protect + 8 + 8 + + + nWRP + Not write protect + 16 + 12 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40013C00 + + 0x0 + 0x400 + registers + + + TAMP_STAMP + Tamper and TimeStamp interrupts through the + EXTI line + 2 + + + EXTI0 + EXTI Line0 interrupt + 6 + + + EXTI1 + EXTI Line1 interrupt + 7 + + + EXTI2 + EXTI Line2 interrupt + 8 + + + EXTI3 + EXTI Line3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 40 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + MR0 + read-write + + Masked + Interrupt request line is masked + 0 + + + Unmasked + Interrupt request line is unmasked + 1 + + + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + + MR20 + Interrupt Mask on line 20 + 20 + 1 + + + + MR21 + Interrupt Mask on line 21 + 21 + 1 + + + + MR22 + Interrupt Mask on line 22 + 22 + 1 + + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + MR0 + read-write + + Masked + Interrupt request line is masked + 0 + + + Unmasked + Interrupt request line is unmasked + 1 + + + + + MR1 + Event Mask on line 1 + 1 + 1 + + + + MR2 + Event Mask on line 2 + 2 + 1 + + + + MR3 + Event Mask on line 3 + 3 + 1 + + + + MR4 + Event Mask on line 4 + 4 + 1 + + + + MR5 + Event Mask on line 5 + 5 + 1 + + + + MR6 + Event Mask on line 6 + 6 + 1 + + + + MR7 + Event Mask on line 7 + 7 + 1 + + + + MR8 + Event Mask on line 8 + 8 + 1 + + + + MR9 + Event Mask on line 9 + 9 + 1 + + + + MR10 + Event Mask on line 10 + 10 + 1 + + + + MR11 + Event Mask on line 11 + 11 + 1 + + + + MR12 + Event Mask on line 12 + 12 + 1 + + + + MR13 + Event Mask on line 13 + 13 + 1 + + + + MR14 + Event Mask on line 14 + 14 + 1 + + + + MR15 + Event Mask on line 15 + 15 + 1 + + + + MR16 + Event Mask on line 16 + 16 + 1 + + + + MR17 + Event Mask on line 17 + 17 + 1 + + + + MR18 + Event Mask on line 18 + 18 + 1 + + + + MR19 + Event Mask on line 19 + 19 + 1 + + + + MR20 + Event Mask on line 20 + 20 + 1 + + + + MR21 + Event Mask on line 21 + 21 + 1 + + + + MR22 + Event Mask on line 22 + 22 + 1 + + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + TR0 + read-write + + Disabled + Rising edge trigger is disabled + 0 + + + Enabled + Rising edge trigger is enabled + 1 + + + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + + TR10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + + TR11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + + TR12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + + TR13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + + TR14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + + TR15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + + TR16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + + TR17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + + TR18 + Rising trigger event configuration of + line 18 + 18 + 1 + + + + TR19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + + TR20 + Rising trigger event configuration of + line 20 + 20 + 1 + + + + TR21 + Rising trigger event configuration of + line 21 + 21 + 1 + + + + TR22 + Rising trigger event configuration of + line 22 + 22 + 1 + + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + TR0 + read-write + + Disabled + Falling edge trigger is disabled + 0 + + + Enabled + Falling edge trigger is enabled + 1 + + + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + + TR10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + + TR11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + + TR12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + + TR13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + + TR14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + + TR15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + + TR16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + + TR17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + + TR18 + Falling trigger event configuration of + line 18 + 18 + 1 + + + + TR19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + + TR20 + Falling trigger event configuration of + line 20 + 20 + 1 + + + + TR21 + Falling trigger event configuration of + line 21 + 21 + 1 + + + + TR22 + Falling trigger event configuration of + line 22 + 22 + 1 + + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line + 0 + 0 + 1 + + SWIER0W + write + + Pend + Generates an interrupt request + 1 + + + + + SWIER1 + Software Interrupt on line + 1 + 1 + 1 + + + + SWIER2 + Software Interrupt on line + 2 + 2 + 1 + + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + + SWIER10 + Software Interrupt on line + 10 + 10 + 1 + + + + SWIER11 + Software Interrupt on line + 11 + 11 + 1 + + + + SWIER12 + Software Interrupt on line + 12 + 12 + 1 + + + + SWIER13 + Software Interrupt on line + 13 + 13 + 1 + + + + SWIER14 + Software Interrupt on line + 14 + 14 + 1 + + + + SWIER15 + Software Interrupt on line + 15 + 15 + 1 + + + + SWIER16 + Software Interrupt on line + 16 + 16 + 1 + + + + SWIER17 + Software Interrupt on line + 17 + 17 + 1 + + + + SWIER18 + Software Interrupt on line + 18 + 18 + 1 + + + + SWIER19 + Software Interrupt on line + 19 + 19 + 1 + + + + SWIER20 + Software Interrupt on line + 20 + 20 + 1 + + + + SWIER21 + Software Interrupt on line + 21 + 21 + 1 + + + + SWIER22 + Software Interrupt on line + 22 + 22 + 1 + + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PR0 + Pending bit 0 + 0 + 1 + oneToClear + + PR0R + read + + NotPending + No trigger request occurred + 0 + + + Pending + Selected trigger request occurred + 1 + + + + PR0W + write + + Clear + Clears pending bit + 1 + + + + + PR1 + Pending bit 1 + 1 + 1 + oneToClear + + read + + + write + + + + PR2 + Pending bit 2 + 2 + 1 + oneToClear + + read + + + write + + + + PR3 + Pending bit 3 + 3 + 1 + oneToClear + + read + + + write + + + + PR4 + Pending bit 4 + 4 + 1 + oneToClear + + read + + + write + + + + PR5 + Pending bit 5 + 5 + 1 + oneToClear + + read + + + write + + + + PR6 + Pending bit 6 + 6 + 1 + oneToClear + + read + + + write + + + + PR7 + Pending bit 7 + 7 + 1 + oneToClear + + read + + + write + + + + PR8 + Pending bit 8 + 8 + 1 + oneToClear + + read + + + write + + + + PR9 + Pending bit 9 + 9 + 1 + oneToClear + + read + + + write + + + + PR10 + Pending bit 10 + 10 + 1 + oneToClear + + read + + + write + + + + PR11 + Pending bit 11 + 11 + 1 + oneToClear + + read + + + write + + + + PR12 + Pending bit 12 + 12 + 1 + oneToClear + + read + + + write + + + + PR13 + Pending bit 13 + 13 + 1 + oneToClear + + read + + + write + + + + PR14 + Pending bit 14 + 14 + 1 + oneToClear + + read + + + write + + + + PR15 + Pending bit 15 + 15 + 1 + oneToClear + + read + + + write + + + + PR16 + Pending bit 16 + 16 + 1 + oneToClear + + read + + + write + + + + PR17 + Pending bit 17 + 17 + 1 + oneToClear + + read + + + write + + + + PR18 + Pending bit 18 + 18 + 1 + oneToClear + + read + + + write + + + + PR19 + Pending bit 19 + 19 + 1 + oneToClear + + read + + + write + + + + PR20 + Pending bit 20 + 20 + 1 + oneToClear + + read + + + write + + + + PR21 + Pending bit 21 + 21 + 1 + oneToClear + + read + + + write + + + + PR22 + Pending bit 22 + 22 + 1 + oneToClear + + read + + + write + + + + + + + + OTG_HS_GLOBAL + USB on the go high speed + USB_OTG_HS + 0x40040000 + + 0x0 + 0x131 + registers + + + OTG_HS_EP1_OUT + USB On The Go HS End Point 1 Out global + interrupt + 74 + + + OTG_HS_EP1_IN + USB On The Go HS End Point 1 In global + interrupt + 75 + + + OTG_HS_WKUP + USB On The Go HS Wakeup through EXTI + interrupt + 76 + + + OTG_HS + USB On The Go HS global + interrupt + 77 + + + + GOTGCTL + GOTGCTL + OTG_HS control and status + register + 0x0 + 0x20 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTG_HS interrupt register + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + GAHBCFG + GAHBCFG + OTG_HS AHB configuration + register + 0x8 + 0x20 + read-write + 0x00000000 + + + GINT + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst length/type + 1 + 4 + + + DMAEN + DMA enable + 5 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + OTG_HS USB configuration + register + 0xC + 0x20 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + USB 2.0 high-speed ULPI PHY or USB 1.1 + full-speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + PHYLPCS + PHY Low-power clock select + 15 + 1 + read-write + + + ULPIFSLS + ULPI FS/LS select + 17 + 1 + read-write + + + ULPIAR + ULPI Auto-resume + 18 + 1 + read-write + + + ULPICSM + ULPI Clock SuspendM + 19 + 1 + read-write + + + ULPIEVBUSD + ULPI External VBUS Drive + 20 + 1 + read-write + + + ULPIEVBUSI + ULPI external VBUS + indicator + 21 + 1 + read-write + + + TSDPS + TermSel DLine pulsing + selection + 22 + 1 + read-write + + + PCCI + Indicator complement + 23 + 1 + read-write + + + PTCI + Indicator pass through + 24 + 1 + read-write + + + ULPIIPD + ULPI interface protect + disable + 25 + 1 + read-write + + + FHMOD + Forced host mode + 29 + 1 + read-write + + + FDMOD + Forced peripheral mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTG_HS reset register + 0x10 + 0x20 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + DMAREQ + DMA request signal + 30 + 1 + read-only + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTG_HS core interrupt register + 0x14 + 0x20 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO nonempty + 4 + 1 + read-only + + + NPTXFE + Nonperiodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN nonperiodic NAK + effective + 6 + 1 + read-only + + + BOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + PXFR_INCOMPISOOUT + Incomplete periodic + transfer + 21 + 1 + read-write + + + DATAFSUSP + Data fetch suspended + 22 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_HS interrupt mask register + 0x18 + 0x20 + 0x00000000 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO nonempty mask + 4 + 1 + read-write + + + NPTXFEM + Nonperiodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global nonperiodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + PXFRM_IISOOXFRM + Incomplete periodic transfer + mask + 21 + 1 + read-write + + + FSUSPM + Data fetch suspended mask + 22 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Host + GRXSTSR_Host + OTG_HS Receive status debug read register + (host mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXSTSP_Host + GRXSTSP_Host + OTG_HS status read and pop register (host + mode) + 0x20 + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTG_HS Receive FIFO size + register + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + HNPTXFSIZ + HNPTXFSIZ + OTG_HS nonperiodic transmit FIFO size + register (host mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSA + Nonperiodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Nonperiodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + Endpoint 0 transmit FIFO size (peripheral + mode) + HNPTXFSIZ + 0x28 + 0x20 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + HNPTXSTS + GNPTXSTS + OTG_HS nonperiodic transmit FIFO/queue + status register + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSAV + Nonperiodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Nonperiodic transmit request queue space + available + 16 + 8 + + + NPTXQTOP + Top of the nonperiodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTG_HS general core configuration + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDWN + Power down + 16 + 1 + + + I2CPADEN + Enable I2C bus connection for the + external I2C PHY interface + 17 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing + device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + NOVBUSSENS + VBUS sensing disable + option + 21 + 1 + + + + + CID + CID + OTG_HS core ID register + 0x3C + 0x20 + read-write + 0x00001200 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTG_HS Host periodic transmit FIFO size + register + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFD + Host periodic TxFIFO depth + 16 + 16 + + + + + 5 + 0x4 + 1-5 + DIEPTXF%s + DIEPTXF1 + OTG_HS device IN endpoint transmit FIFO size + register + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + GRXSTSR_Device + GRXSTSR_Peripheral + OTG_HS Receive status debug read register + (peripheral mode mode) + GRXSTSR_Host + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + GRXSTSP_Device + GRXSTSP_Peripheral + OTG_HS status read and pop register + (peripheral mode) + GRXSTSP_Host + 0x20 + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + + + OTG_HS_HOST + USB on the go high speed + USB_OTG_HS + 0x40040400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTG_HS host configuration + register + 0x0 + 0x20 + 0x00000000 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTG_HS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTG_HS host frame number/frame time + remaining register + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTG_HS_Host periodic transmit FIFO/queue + status register + 0x10 + 0x20 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTG_HS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTG_HS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTG_HS host port control and status + register + 0x40 + 0x20 + 0x00000000 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + 12 + 0x20 + 0-11 + HC%s + Host channel + 0x100 + + CHAR + HCCHAR0 + OTG_HS host channel-0 characteristics + register + 0x0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + SPLT + HCSPLT0 + OTG_HS host channel-0 split control + register + 0x4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + INT + HCINT0 + OTG_HS host channel-11 interrupt + register + 0x8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + INTMSK + HCINTMSK0 + OTG_HS host channel-11 interrupt mask + register + 0xC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + TSIZ + HCTSIZ0 + OTG_HS host channel-11 transfer size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + DMA + HCDMA0 + OTG_HS host channel-0 DMA address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + 0 + 32 + + + + + + + + OTG_HS_DEVICE + USB on the go high speed + USB_OTG_HS + 0x40040800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTG_HS device configuration + register + 0x0 + 0x20 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Nonzero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic (micro)frame + interval + 11 + 2 + + + PERSCHIVL + Periodic scheduling + interval + 24 + 2 + + + + + DCTL + DCTL + OTG_HS device control register + 0x4 + 0x20 + 0x00000000 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTG_HS device status register + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTG_HS device IN endpoint common interrupt + mask register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTG_HS device OUT endpoint common interrupt + mask register + 0x14 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received + mask + 6 + 1 + + + OPEM + OUT packet error mask + 8 + 1 + + + BOIM + BNA interrupt mask + 9 + 1 + + + + + DAINT + DAINT + OTG_HS device all endpoints interrupt + register + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTG_HS all endpoints interrupt mask + register + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + OTG_HS device VBUS discharge time + register + 0x28 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + OTG_HS device VBUS pulsing time + register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + DTHRCTL + DTHRCTL + OTG_HS Device threshold control + register + 0x30 + 0x20 + read-write + 0x00000000 + + + NONISOTHREN + Nonisochronous IN endpoints threshold + enable + 0 + 1 + + + ISOTHREN + ISO IN endpoint threshold + enable + 1 + 1 + + + TXTHRLEN + Transmit threshold length + 2 + 9 + + + RXTHREN + Receive threshold enable + 16 + 1 + + + RXTHRLEN + Receive threshold length + 17 + 9 + + + ARPEN + Arbiter parking enable + 27 + 1 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTG_HS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DEACHINT + DEACHINT + OTG_HS device each endpoint interrupt + register + 0x38 + 0x20 + read-write + 0x00000000 + + + IEP1INT + IN endpoint 1interrupt bit + 1 + 1 + + + OEP1INT + OUT endpoint 1 interrupt + bit + 17 + 1 + + + + + DEACHINTMSK + DEACHINTMSK + OTG_HS device each endpoint interrupt + register mask + 0x3C + 0x20 + read-write + 0x00000000 + + + IEP1INTM + IN Endpoint 1 interrupt mask + bit + 1 + 1 + + + OEP1INTM + OUT Endpoint 1 interrupt mask + bit + 17 + 1 + + + + + DIEPEACHMSK1 + DIEPEACHMSK1 + OTG_HS device each in endpoint-1 interrupt + register + 0x44 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + + + DOEPEACHMSK1 + DOEPEACHMSK1 + OTG_HS device each OUT endpoint-1 interrupt + register + 0x84 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + OUT packet error mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + BERRM + Bubble error interrupt + mask + 12 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + NYETM + NYET interrupt mask + 14 + 1 + + + + + DIEP0 + Device IN endpoint 0 + 0x100 + + CTL + DIEPCTL0 + OTG device endpoint-0 control + register + 0x0 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + INT + DIEPINT0 + OTG device endpoint-0 interrupt + register + 0x8 + 0x20 + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + TSIZ + DIEPTSIZ0 + OTG_HS device IN endpoint 0 transfer size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DMA + OTG_HS device endpoint-0 DMA address register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + 0 + 32 + + + + + TXFSTS + DTXFSTS0 + OTG_HS device IN endpoint transmit FIFO + status register + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + + 5 + 0x20 + 1-5 + DIEP%s + Device IN endpoint X + 0x120 + + CTL + DIEPCTL1 + OTG device endpoint-1 control + register + 0x0 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + INT + DIEPINT1 + OTG device endpoint-1 interrupt + register + 0x8 + 0x20 + 0x00000000 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + TSIZ + DIEPTSIZ1 + OTG_HS device endpoint transfer size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + DMA + DIEPDMA1 + OTG_HS device endpoint-1 DMA address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + 0 + 32 + + + + + TXFSTS + DTXFSTS1 + OTG_HS device IN endpoint transmit FIFO + status register + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + + DOEP0 + Device OUT endpoint 0 + 0x300 + + CTL + DOEPCTL0 + OTG_HS device control OUT endpoint 0 control + register + 0x0 + 0x20 + 0x00008000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-only + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + SNPM + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + INT + DOEPINT0 + OTG_HS device endpoint-0 interrupt + register + 0x8 + 0x20 + read-write + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + TSIZ + DOEPTSIZ0 + OTG_HS device endpoint-1 transfer size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + STUPCNT + SETUP packet count + 29 + 2 + + + + + DMA + OTG_HS device endpoint-0 DMA address register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + 0 + 32 + + + + + + 5 + 0x20 + 1-5 + DOEP%s + Device IN endpoint X + 0x320 + + CTL + DOEPCTL1 + OTG device endpoint-1 control + register + 0x0 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + INT + DOEPINT1 + OTG_HS device endpoint-1 interrupt + register + 0x8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + DMA + OTG_HS device endpoint-1 DMA address register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + 0 + 32 + + + + + TSIZ + DOEPTSIZ1 + OTG_HS device endpoint-2 transfer size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + + + + OTG_HS_PWRCLK + USB on the go high speed + USB_OTG_HS + 0x40040E00 + + 0x0 + 0x3F200 + registers + + + + PCGCCTL + PCGCCTL + Power and clock gating control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY suspended + 4 + 1 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0x351 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear-Enable + Register + 0x88 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending + Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active Bit Register + 0x208 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + SAI1 + Serial audio interface + SAI + 0x40015800 + + 0x0 + 0x400 + registers + + + + 2 + 0x20 + A,B + CH%s + Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + 0x4 + + CR1 + ACR1 + SAI AConfiguration register 1 + 0x0 + 0x20 + read-write + 0x00000040 + + + MCKDIV + Master clock divider + 20 + 4 + + + MODE + Audio block mode + 0 + 2 + + MODE + read-write + + MasterTx + Master transmitter + 0 + + + MasterRx + Master receiver + 1 + + + SlaveTx + Slave transmitter + 2 + + + SlaveRx + Slave receiver + 3 + + + + + PRTCFG + Protocol configuration + 2 + 2 + + PRTCFG + read-write + + Free + Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + 0 + + + Spdif + SPDIF protocol + 1 + + + Ac97 + AC’97 protocol + 2 + + + + + DS + Data size + 5 + 3 + + DS + read-write + + Bit8 + 8 bits + 2 + + + Bit10 + 10 bits + 3 + + + Bit16 + 16 bits + 4 + + + Bit20 + 20 bits + 5 + + + Bit24 + 24 bits + 6 + + + Bit32 + 32 bits + 7 + + + + + LSBFIRST + Least significant bit + first + 8 + 1 + + LSBFIRST + read-write + + MsbFirst + Data are transferred with MSB first + 0 + + + LsbFirst + Data are transferred with LSB first + 1 + + + + + CKSTR + Clock strobing edge + 9 + 1 + + CKSTR + read-write + + FallingEdge + Data strobing edge is falling edge of SCK + 0 + + + RisingEdge + Data strobing edge is rising edge of SCK + 1 + + + + + SYNCEN + Synchronization enable + 10 + 2 + + SYNCEN + read-write + + Asynchronous + audio sub-block in asynchronous mode + 0 + + + Internal + audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + 1 + + + External + audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + 2 + + + + + MONO + Mono mode + 12 + 1 + + MONO + read-write + + Stereo + Stereo mode + 0 + + + Mono + Mono mode + 1 + + + + + OUTDRIV + Output drive + 13 + 1 + + OUTDRIV + read-write + + OnStart + Audio block output driven when SAIEN is set + 0 + + + Immediately + Audio block output driven immediately after the setting of this bit + 1 + + + + + SAIEN + Audio block enable + 16 + 1 + + SAIEN + read-write + + Disabled + SAI audio block disabled + 0 + + + Enabled + SAI audio block enabled + 1 + + + + + DMAEN + DMA enable + 17 + 1 + + DMAEN + read-write + + Disabled + DMA disabled + 0 + + + Enabled + DMA enabled + 1 + + + + + NODIV + No divider + 19 + 1 + + NODIV + read-write + + MasterClock + MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + 0 + + + NoDiv + MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + 1 + + + + + + + CR2 + ACR2 + SAI AConfiguration register 2 + 0x4 + 0x20 + read-write + 0x00000040 + + + FTH + FIFO threshold + 0 + 3 + read-write + + FTH + read-write + + Empty + FIFO empty + 0 + + + Quarter1 + 1⁄4 FIFO + 1 + + + Quarter2 + 1⁄2 FIFO + 2 + + + Quarter3 + 3⁄4 FIFO + 3 + + + Full + FIFO full + 4 + + + + + FFLUSH + FIFO flush + 3 + 1 + + FFLUSH + read-write + + NoFlush + No FIFO flush + 0 + + + Flush + FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared + 1 + + + + + TRIS + Tristate management on data + line + 4 + 1 + read-write + + + MUTE + Mute + 5 + 1 + read-write + + MUTE + read-write + + Disabled + No mute mode + 0 + + + Enabled + Mute mode enabled + 1 + + + + + MUTEVAL + Mute value + 6 + 1 + read-write + + MUTEVAL + read-write + + SendZero + Bit value 0 is sent during the mute mode + 0 + + + SendLast + Last values are sent during the mute mode + 1 + + + + + MUTECNT + Mute counter + 7 + 6 + read-write + + + CPL + Complement bit + 13 + 1 + read-write + + CPL + read-write + + OnesComplement + 1’s complement representation + 0 + + + TwosComplement + 2’s complement representation + 1 + + + + + COMP + Companding mode + 14 + 2 + read-write + + COMP + read-write + + NoCompanding + No companding algorithm + 0 + + + MuLaw + μ-Law algorithm + 2 + + + ALaw + A-Law algorithm + 3 + + + + + + + FRCR + AFRCR + SAI AFrame configuration + register + 0x8 + 0x20 + 0x00000007 + + + FRL + Frame length + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length + 8 + 7 + read-write + + + FSDEF + Frame synchronization + definition + 16 + 1 + read-write + + + FSPOL + Frame synchronization + polarity + 17 + 1 + read-write + + FSPOL + read-write + + FallingEdge + FS is active low (falling edge) + 0 + + + RisingEdge + FS is active high (rising edge) + 1 + + + + + FSOFF + Frame synchronization + offset + 18 + 1 + read-write + + FSOFF + read-write + + OnFirst + FS is asserted on the first bit of the slot 0 + 0 + + + BeforeFirst + FS is asserted one bit before the first bit of the slot 0 + 1 + + + + + + + SLOTR + ASLOTR + SAI ASlot register + 0xC + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset + 0 + 5 + + + SLOTSZ + Slot size + 6 + 2 + + SLOTSZ + read-write + + DataSize + The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + 0 + + + Bit16 + 16-bit + 1 + + + Bit32 + 32-bit + 2 + + + + + NBSLOT + Number of slots in an audio + frame + 8 + 4 + + + SLOTEN + Slot enable + 16 + 16 + + SLOTEN + read-write + + Inactive + Inactive slot + 0 + + + Active + Active slot + 1 + + + + + + + IM + AIM + SAI AInterrupt mask register2 + 0x10 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt + enable + 0 + 1 + + OVRUDRIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + MUTEDETIE + Mute detection interrupt + enable + 1 + 1 + + MUTEDETIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + WCKCFGIE + Wrong clock configuration interrupt + enable + 2 + 1 + + WCKCFGIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + FREQIE + FIFO request interrupt + enable + 3 + 1 + + FREQIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + CNRDYIE + Codec not ready interrupt + enable + 4 + 1 + + CNRDYIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + AFSDETIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + LFSDETIE + Late frame synchronization detection + interrupt enable + 6 + 1 + + LFSDETIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + + + SR + ASR + SAI AStatus register + 0x14 + 0x20 + read-only + 0x00000008 + + + OVRUDR + Overrun / underrun + 0 + 1 + + OVRUDRR + read + + NoError + No overrun/underrun error + 0 + + + Overrun + Overrun/underrun error detection + 1 + + + + + MUTEDET + Mute detection + 1 + 1 + + MUTEDETR + read + + NoMute + No MUTE detection on the SD input line + 0 + + + Mute + MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame + 1 + + + + + WCKCFG + Wrong clock configuration + flag + 2 + 1 + + WCKCFGR + read + + Correct + Clock configuration is correct + 0 + + + Wrong + Clock configuration does not respect the rule concerning the frame length specification + 1 + + + + + FREQ + FIFO request + 3 + 1 + + FREQR + read + + NoRequest + No FIFO request + 0 + + + Request + FIFO request to read or to write the SAI_xDR + 1 + + + + + CNRDY + Codec not ready + 4 + 1 + + CNRDYR + read + + Ready + External AC’97 Codec is ready + 0 + + + NotReady + External AC’97 Codec is not ready + 1 + + + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + + AFSDETR + read + + NoError + No error + 0 + + + EarlySync + Frame synchronization signal is detected earlier than expected + 1 + + + + + LFSDET + Late frame synchronization + detection + 6 + 1 + + LFSDETR + read + + NoError + No error + 0 + + + NoSync + Frame synchronization signal is not present at the right time + 1 + + + + + FLVL + FIFO level threshold + 16 + 3 + + FLVLR + read + + Empty + FIFO empty + 0 + + + Quarter1 + FIFO <= 1⁄4 but not empty + 1 + + + Quarter2 + 1⁄4 < FIFO <= 1⁄2 + 2 + + + Quarter3 + 1⁄2 < FIFO <= 3⁄4 + 3 + + + Quarter4 + 3⁄4 < FIFO but not full + 4 + + + Full + FIFO full + 5 + + + + + + + CLRFR + ACLRFR + SAI AClear flag register + 0x18 + 0x20 + read-write + 0x00000000 + + + COVRUDR + Clear overrun / underrun + 0 + 1 + + COVRUDRW + write + + Clear + Clears the OVRUDR flag + 1 + + + + + CMUTEDET + Mute detection flag + 1 + 1 + + CMUTEDETW + write + + Clear + Clears the MUTEDET flag + 1 + + + + + CWCKCFG + Clear wrong clock configuration + flag + 2 + 1 + + CWCKCFGW + write + + Clear + Clears the WCKCFG flag + 1 + + + + + CCNRDY + Clear codec not ready flag + 4 + 1 + + CCNRDYW + write + + Clear + Clears the CNRDY flag + 1 + + + + + CAFSDET + Clear anticipated frame synchronization + detection flag + 5 + 1 + + CAFSDETW + write + + Clear + Clears the AFSDET flag + 1 + + + + + CLFSDET + Clear late frame synchronization + detection flag + 6 + 1 + + CLFSDETW + write + + Clear + Clears the LFSDET flag + 1 + + + + + + + DR + ADR + SAI AData register + 0x1C + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + + + + LTDC + LCD-TFT Controller + LTDC + 0x40016800 + + 0x0 + 0x400 + registers + + + LTDC + LTDC global interrupt + 88 + + + LTDC_ER + LTDC global error interrupt + 89 + + + + SSCR + SSCR + Synchronization Size Configuration + Register + 0x8 + 0x20 + read-write + 0x00000000 + + + HSW + Horizontal Synchronization Width (in + units of pixel clock period) + 16 + 12 + + + 0 + 4095 + + + + + VSH + Vertical Synchronization Height (in + units of horizontal scan line) + 0 + 11 + + + 0 + 2047 + + + + + + + BPCR + BPCR + Back Porch Configuration + Register + 0xC + 0x20 + read-write + 0x00000000 + + + AHBP + Accumulated Horizontal back porch (in + units of pixel clock period) + 16 + 12 + + + 0 + 4095 + + + + + AVBP + Accumulated Vertical back porch (in + units of horizontal scan line) + 0 + 11 + + + 0 + 2047 + + + + + + + AWCR + AWCR + Active Width Configuration + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + AAW + Accumulated Active Width (in units of pixel clock period) + 16 + 12 + + + 0 + 4095 + + + + + AAH + Accumulated Active Height (in units of + horizontal scan line) + 0 + 11 + + + 0 + 2047 + + + + + + + TWCR + TWCR + Total Width Configuration + Register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTALW + Total Width (in units of pixel clock + period) + 16 + 12 + + + 0 + 4095 + + + + + TOTALH + Total Height (in units of horizontal + scan line) + 0 + 11 + + + 0 + 2047 + + + + + + + GCR + GCR + Global Control Register + 0x18 + 0x20 + 0x00002220 + + + HSPOL + Horizontal Synchronization + Polarity + 31 + 1 + read-write + + HSPOL + read-write + + ActiveLow + Horizontal synchronization polarity is active low + 0 + + + ActiveHigh + Horizontal synchronization polarity is active high + 1 + + + + + VSPOL + Vertical Synchronization + Polarity + 30 + 1 + read-write + + VSPOL + read-write + + ActiveLow + Vertical synchronization polarity is active low + 0 + + + ActiveHigh + Vertical synchronization polarity is active high + 1 + + + + + DEPOL + Data Enable Polarity + 29 + 1 + read-write + + DEPOL + read-write + + ActiveLow + Data enable polarity is active low + 0 + + + ActiveHigh + Data enable polarity is active high + 1 + + + + + PCPOL + Pixel Clock Polarity + 28 + 1 + read-write + + PCPOL + read-write + + RisingEdge + Pixel clock on rising edge + 0 + + + FallingEdge + Pixel clock on falling edge + 1 + + + + + DEN + Dither Enable + 16 + 1 + read-write + + DEN + read-write + + Disabled + Dither disabled + 0 + + + Enabled + Dither enabled + 1 + + + + + DRW + Dither Red Width + 12 + 3 + read-only + + + DGW + Dither Green Width + 8 + 3 + read-only + + + DBW + Dither Blue Width + 4 + 3 + read-only + + + LTDCEN + LCD-TFT controller enable + bit + 0 + 1 + read-write + + LTDCEN + read-write + + Disabled + LCD-TFT controller disabled + 0 + + + Enabled + LCD-TFT controller enabled + 1 + + + + + + + SRCR + SRCR + Shadow Reload Configuration + Register + 0x24 + 0x20 + read-write + 0x00000000 + + + VBR + Vertical Blanking Reload + 1 + 1 + + VBR + read-write + + NoEffect + This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + 0 + + + Reload + The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). + 1 + + + + + IMR + Immediate Reload + 0 + 1 + + IMR + read-write + + NoEffect + This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + 0 + + + Reload + The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload + 1 + + + + + + + BCCR + BCCR + Background Color Configuration + Register + 0x2C + 0x20 + read-write + 0x00000000 + + + BCBLUE + Background color blue value + 0 + 8 + + + 0 + 255 + + + + + BCGREEN + Background color green value + 8 + 8 + + + 0 + 255 + + + + + BCRED + Background color red value + 16 + 8 + + + 0 + 255 + + + + + + + IER + IER + Interrupt Enable Register + 0x34 + 0x20 + read-write + 0x00000000 + + + RRIE + Register Reload interrupt + enable + 3 + 1 + + RRIE + read-write + + Disabled + Register reload interrupt disabled + 0 + + + Enabled + Register reload interrupt enabled + 1 + + + + + TERRIE + Transfer Error Interrupt + Enable + 2 + 1 + + TERRIE + read-write + + Disabled + Transfer error interrupt disabled + 0 + + + Enabled + Transfer error interrupt enabled + 1 + + + + + FUIE + FIFO Underrun Interrupt + Enable + 1 + 1 + + FUIE + read-write + + Disabled + FIFO underrun interrupt disabled + 0 + + + Enabled + FIFO underrun interrupt enabled + 1 + + + + + LIE + Line Interrupt Enable + 0 + 1 + + LIE + read-write + + Disabled + Line interrupt disabled + 0 + + + Enabled + Line interrupt enabled + 1 + + + + + + + ISR + ISR + Interrupt Status Register + 0x38 + 0x20 + read-only + 0x00000000 + + + RRIF + Register Reload Interrupt + Flag + 3 + 1 + + RRIF + read + + NoReload + No register reload + 0 + + + Reload + Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) + 1 + + + + + TERRIF + Transfer Error interrupt + flag + 2 + 1 + + TERRIF + read + + NoError + No transfer error + 0 + + + Error + Transfer error interrupt generated when a bus error occurs + 1 + + + + + FUIF + FIFO Underrun Interrupt + flag + 1 + 1 + + FUIF + read + + NoUnderrun + No FIFO underrun + 0 + + + Underrun + FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO + 1 + + + + + LIF + Line Interrupt flag + 0 + 1 + + LIF + read + + NotReached + Programmed line not reached + 0 + + + Reached + Line interrupt generated when a programmed line is reached + 1 + + + + + + + ICR + ICR + Interrupt Clear Register + 0x3C + 0x20 + write-only + 0x00000000 + + + CRRIF + Clears Register Reload Interrupt + Flag + 3 + 1 + oneToClear + + CRRIFW + write + + Clear + Clears the RRIF flag in the ISR register + 1 + + + + + CTERRIF + Clears the Transfer Error Interrupt + Flag + 2 + 1 + oneToClear + + CTERRIFW + write + + Clear + Clears the TERRIF flag in the ISR register + 1 + + + + + CFUIF + Clears the FIFO Underrun Interrupt + flag + 1 + 1 + oneToClear + + CFUIFW + write + + Clear + Clears the FUIF flag in the ISR register + 1 + + + + + CLIF + Clears the Line Interrupt + Flag + 0 + 1 + oneToClear + + CLIFW + write + + Clear + Clears the LIF flag in the ISR register + 1 + + + + + + + LIPCR + LIPCR + Line Interrupt Position Configuration + Register + 0x40 + 0x20 + read-write + 0x00000000 + + + LIPOS + Line Interrupt Position + 0 + 11 + + + 0 + 2047 + + + + + + + CPSR + CPSR + Current Position Status + Register + 0x44 + 0x20 + read-only + 0x00000000 + + + CXPOS + Current X Position + 16 + 16 + + + CYPOS + Current Y Position + 0 + 16 + + + + + CDSR + CDSR + Current Display Status + Register + 0x48 + 0x20 + read-only + 0x0000000F + + + HSYNCS + Horizontal Synchronization display + Status + 3 + 1 + + HSYNCS + read + + NotActive + Currently not in HSYNC phase + 0 + + + Active + Currently in HSYNC phase + 1 + + + + + VSYNCS + Vertical Synchronization display + Status + 2 + 1 + + VSYNCS + read + + NotActive + Currently not in VSYNC phase + 0 + + + Active + Currently in VSYNC phase + 1 + + + + + HDES + Horizontal Data Enable display + Status + 1 + 1 + + HDES + read + + NotActive + Currently not in horizontal Data Enable phase + 0 + + + Active + Currently in horizontal Data Enable phase + 1 + + + + + VDES + Vertical Data Enable display + Status + 0 + 1 + + VDES + read + + NotActive + Currently not in vertical Data Enable phase + 0 + + + Active + Currently in vertical Data Enable phase + 1 + + + + + + + 2 + 0x80 + 1-2 + LAYER%s + Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR + 0x84 + + CR + L1CR + Layerx Control Register + 0x0 + 0x20 + read-write + 0x00000000 + + + CLUTEN + Color Look-Up Table Enable + 4 + 1 + + CLUTEN + read-write + + Disabled + Color look-up table disabled + 0 + + + Enabled + Color look-up table enabled + 1 + + + + + COLKEN + Color Keying Enable + 1 + 1 + + COLKEN + read-write + + Disabled + Color keying disabled + 0 + + + Enabled + Color keying enabled + 1 + + + + + LEN + Layer Enable + 0 + 1 + + LEN + read-write + + Disabled + Layer disabled + 0 + + + Enabled + Layer enabled + 1 + + + + + + + WHPCR + L1WHPCR + Layerx Window Horizontal Position + Configuration Register + 0x4 + 0x20 + read-write + 0x00000000 + + + WHSPPOS + Window Horizontal Stop + Position + 16 + 12 + + + 0 + 4095 + + + + + WHSTPOS + Window Horizontal Start + Position + 0 + 12 + + + 0 + 4095 + + + + + + + WVPCR + L1WVPCR + Layerx Window Vertical Position + Configuration Register + 0x8 + 0x20 + read-write + 0x00000000 + + + WVSPPOS + Window Vertical Stop + Position + 16 + 11 + + + 0 + 2047 + + + + + WVSTPOS + Window Vertical Start + Position + 0 + 11 + + + 0 + 2047 + + + + + + + CKCR + L1CKCR + Layerx Color Keying Configuration + Register + 0xC + 0x20 + read-write + 0x00000000 + + + CKRED + Color Key Red value + 16 + 8 + + + 0 + 255 + + + + + CKGREEN + Color Key Green value + 8 + 8 + + + 0 + 255 + + + + + CKBLUE + Color Key Blue value + 0 + 8 + + + 0 + 255 + + + + + + + PFCR + L1PFCR + Layerx Pixel Format Configuration + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + PF + Pixel Format + 0 + 3 + + PF + read-write + + ARGB8888 + ARGB8888 + 0 + + + RGB888 + RGB888 + 1 + + + RGB565 + RGB565 + 2 + + + ARGB1555 + ARGB1555 + 3 + + + ARGB4444 + ARGB4444 + 4 + + + L8 + L8 (8-bit luminance) + 5 + + + AL44 + AL44 (4-bit alpha, 4-bit luminance) + 6 + + + AL88 + AL88 (8-bit alpha, 8-bit luminance) + 7 + + + + + + + CACR + L1CACR + Layerx Constant Alpha Configuration + Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CONSTA + Constant Alpha + 0 + 8 + + + 0 + 255 + + + + + + + DCCR + L1DCCR + Layerx Default Color Configuration + Register + 0x18 + 0x20 + read-write + 0x00000000 + + + DCALPHA + Default Color Alpha + 24 + 8 + + + 0 + 255 + + + + + DCRED + Default Color Red + 16 + 8 + + + 0 + 255 + + + + + DCGREEN + Default Color Green + 8 + 8 + + + 0 + 255 + + + + + DCBLUE + Default Color Blue + 0 + 8 + + + 0 + 255 + + + + + + + BFCR + L1BFCR + Layerx Blending Factors Configuration + Register + 0x1C + 0x20 + read-write + 0x00000607 + + + BF1 + Blending Factor 1 + 8 + 3 + + BF1 + read-write + + Constant + BF1 = constant alpha + 4 + + + Pixel + BF1 = pixel alpha * constant alpha + 6 + + + + + BF2 + Blending Factor 2 + 0 + 3 + + BF2 + read-write + + Constant + BF2 = 1 - constant alpha + 5 + + + Pixel + BF2 = 1 - pixel alpha * constant alpha + 7 + + + + + + + CFBAR + L1CFBAR + Layerx Color Frame Buffer Address + Register + 0x28 + 0x20 + read-write + 0x00000000 + + + CFBADD + Color Frame Buffer Start + Address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CFBLR + L1CFBLR + Layerx Color Frame Buffer Length + Register + 0x2C + 0x20 + read-write + 0x00000000 + + + CFBP + Color Frame Buffer Pitch in + bytes + 16 + 13 + + + 0 + 8191 + + + + + CFBLL + Color Frame Buffer Line + Length + 0 + 13 + + + 0 + 8191 + + + + + + + CFBLNR + L1CFBLNR + Layerx ColorFrame Buffer Line Number + Register + 0x30 + 0x20 + read-write + 0x00000000 + + + CFBLNBR + Frame Buffer Line Number + 0 + 11 + + + 0 + 2047 + + + + + + + CLUTWR + L1CLUTWR + Layerx CLUT Write Register + 0x40 + 0x20 + write-only + 0x00000000 + + + CLUTADD + CLUT Address + 24 + 8 + + + 0 + 255 + + + + + RED + Red value + 16 + 8 + + + 0 + 255 + + + + + GREEN + Green value + 8 + 8 + + + 0 + 255 + + + + + BLUE + Blue value + 0 + 8 + + + 0 + 255 + + + + + + + + + + HASH + Hash processor + HASH + 0x50060400 + + 0x0 + 0x400 + registers + + + HASH_RNG + Hash and Rng global interrupt + 80 + + + + CR + CR + control register + 0x0 + 0x20 + 0x00000000 + + + INIT + Initialize message digest + calculation + 2 + 1 + write-only + + + DMAE + DMA enable + 3 + 1 + read-write + + + DATATYPE + Data type selection + 4 + 2 + read-write + + + MODE + Mode selection + 6 + 1 + read-write + + + ALGO0 + Algorithm selection + 7 + 1 + read-write + + + NBW + Number of words already + pushed + 8 + 4 + read-only + + + DINNE + DIN not empty + 12 + 1 + read-only + + + MDMAT + Multiple DMA Transfers + 13 + 1 + read-write + + + LKEY + Long key selection + 16 + 1 + read-write + + + ALGO1 + ALGO + 18 + 1 + read-write + + + + + DIN + DIN + data input register + 0x4 + 0x20 + read-write + 0x00000000 + + + DATAIN + Data input + 0 + 32 + + + + + STR + STR + start register + 0x8 + 0x20 + 0x00000000 + + + DCAL + Digest calculation + 8 + 1 + write-only + + + NBLW + Number of valid bits in the last word of + the message + 0 + 5 + read-write + + + + + 5 + 0x4 + 0-4 + HR%s + HR0 + digest registers + 0xC + 0x20 + read-only + 0x00000000 + + + H + H0 + 0 + 32 + + + + + IMR + IMR + interrupt enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + DCIE + Digest calculation completion interrupt + enable + 1 + 1 + + + DINIE + Data input interrupt + enable + 0 + 1 + + + + + SR + SR + status register + 0x24 + 0x20 + 0x00000001 + + + BUSY + Busy bit + 3 + 1 + read-only + + + DMAS + DMA Status + 2 + 1 + read-only + + + DCIS + Digest calculation completion interrupt + status + 1 + 1 + read-write + + + DINIS + Data input interrupt + status + 0 + 1 + read-write + + + + + 54 + 0x4 + 0-53 + CSR%s + CSR0 + context swap registers + 0xF8 + 0x20 + read-write + 0x00000000 + + + CSR + CSR0 + 0 + 32 + + + + + 8 + 0x4 + 0-7 + HASH_HR%s + HASH_HR0 + HASH digest register %s + 0x310 + 0x20 + read-only + 0x00000000 + + + H + H0 + 0 + 32 + + + + + + + CRYP + Cryptographic processor + CRYP + 0x50060000 + + 0x0 + 0x400 + registers + + + CRYP + CRYP crypto global interrupt + 79 + + + + CR + CR + control register + 0x0 + 0x20 + 0x00000000 + + + ALGODIR + Algorithm direction + 2 + 1 + read-write + + + ALGOMODE0 + Algorithm mode + 3 + 3 + read-write + + + DATATYPE + Data type selection + 6 + 2 + read-write + + + KEYSIZE + Key size selection (AES mode + only) + 8 + 2 + read-write + + + FFLUSH + FIFO flush + 14 + 1 + write-only + + + CRYPEN + Cryptographic processor + enable + 15 + 1 + read-write + + + GCM_CCMPH + GCM_CCMPH + 16 + 2 + read-write + + + ALGOMODE3 + ALGOMODE + 19 + 1 + read-write + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000003 + + + BUSY + Busy bit + 4 + 1 + + + OFFU + Output FIFO full + 3 + 1 + + + OFNE + Output FIFO not empty + 2 + 1 + + + IFNF + Input FIFO not full + 1 + 1 + + + IFEM + Input FIFO empty + 0 + 1 + + + + + DIN + DIN + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + DATAIN + Data input + 0 + 32 + + + + + DOUT + DOUT + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + DATAOUT + Data output + 0 + 32 + + + + + DMACR + DMACR + DMA control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DOEN + DMA output enable + 1 + 1 + + + DIEN + DMA input enable + 0 + 1 + + + + + IMSCR + IMSCR + interrupt mask set/clear + register + 0x14 + 0x20 + read-write + 0x00000000 + + + OUTIM + Output FIFO service interrupt + mask + 1 + 1 + + + INIM + Input FIFO service interrupt + mask + 0 + 1 + + + + + RISR + RISR + raw interrupt status register + 0x18 + 0x20 + read-only + 0x00000001 + + + OUTRIS + Output FIFO service raw interrupt + status + 1 + 1 + + + INRIS + Input FIFO service raw interrupt + status + 0 + 1 + + + + + MISR + MISR + masked interrupt status + register + 0x1C + 0x20 + read-only + 0x00000000 + + + OUTMIS + Output FIFO service masked interrupt + status + 1 + 1 + + + INMIS + Input FIFO service masked interrupt + status + 0 + 1 + + + + + 4 + 0x8 + 0-3 + KEY%s + Cluster KEY%s, containing K?LR, K?RR + 0x20 + + KLR + K0LR + key registers + 0x0 + 0x20 + write-only + 0x00000000 + + + b2 + b224 + 0 + 32 + + + + + KRR + K0RR + key registers + 0x4 + 0x20 + write-only + 0x00000000 + + + b + b192 + 0 + 32 + + + + + + 2 + 0x8 + 0-1 + INIT%s + Cluster INIT%s, containing IV?LR, IV?RR + 0x40 + + IVLR + IV0LR + initialization vector + registers + 0x0 + 0x20 + read-write + 0x00000000 + + + IV + IV31 + 0 + 32 + + + + + IVRR + IV0RR + initialization vector + registers + 0x4 + 0x20 + read-write + 0x00000000 + + + IV + IV63 + 0 + 32 + + + + + + 8 + 0x4 + 0-7 + CSGCMCCM%sR + CSGCMCCM0R + context swap register + 0x50 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM0R + CSGCMCCM0R + 0 + 32 + + + + + 8 + 0x4 + 0-7 + CSGCM%sR + CSGCM0R + context swap register + 0x70 + 0x20 + read-write + 0x00000000 + + + CSGCMR + CSGCM0R + 0 + 32 + + + + + + + FPU + Floting point unit + FPU + 0xE000EF34 + + 0x0 + 0xD + registers + + + FPU + Floating point unit interrupt + 81 + + + + FPCCR + FPCCR + Floating-point context control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + LSPACT + LSPACT + 0 + 1 + + + USER + USER + 1 + 1 + + + THREAD + THREAD + 3 + 1 + + + HFRDY + HFRDY + 4 + 1 + + + MMRDY + MMRDY + 5 + 1 + + + BFRDY + BFRDY + 6 + 1 + + + MONRDY + MONRDY + 8 + 1 + + + LSPEN + LSPEN + 30 + 1 + + + ASPEN + ASPEN + 31 + 1 + + + + + FPCAR + FPCAR + Floating-point context address + register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Location of unpopulated + floating-point + 3 + 29 + + + + + FPSCR + FPSCR + Floating-point status control + register + 0x8 + 0x20 + read-write + 0x00000000 + + + IOC + Invalid operation cumulative exception + bit + 0 + 1 + + + DZC + Division by zero cumulative exception + bit. + 1 + 1 + + + OFC + Overflow cumulative exception + bit + 2 + 1 + + + UFC + Underflow cumulative exception + bit + 3 + 1 + + + IXC + Inexact cumulative exception + bit + 4 + 1 + + + IDC + Input denormal cumulative exception + bit. + 7 + 1 + + + RMode + Rounding Mode control + field + 22 + 2 + + + FZ + Flush-to-zero mode control + bit: + 24 + 1 + + + DN + Default NaN mode control + bit + 25 + 1 + + + AHP + Alternative half-precision control + bit + 26 + 1 + + + V + Overflow condition code + flag + 28 + 1 + + + C + Carry condition code flag + 29 + 1 + + + Z + Zero condition code flag + 30 + 1 + + + N + Negative condition code + flag + 31 + 1 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + TYPER + TYPER + MPU type register + 0x0 + 0x20 + read-only + 0x00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction + regions + 16 + 8 + + + + + CTRL + CTRL + MPU control register + 0x4 + 0x20 + read-only + 0x00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard + fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to + default memory map + 2 + 1 + + + + + RNR + RNR + MPU region number register + 0x8 + 0x20 + read-write + 0x00000000 + + + REGION + MPU region + 0 + 8 + + + + + RBAR + RBAR + MPU region base address + register + 0xC + 0x20 + read-write + 0x00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + RASR + RASR + MPU region attribute and size + register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection + region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable + bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CTRL + CTRL + SysTick control and status + register + 0x0 + 0x20 + read-write + 0x00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request + enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + LOAD + LOAD + SysTick reload value register + 0x4 + 0x20 + read-write + 0x00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + VAL + VAL + SysTick current value register + 0x8 + 0x20 + read-write + 0x00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0x00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS + value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR1 + SHPR1 + System handler priority + registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler + 4 + 0 + 8 + + + PRI_5 + Priority of system handler + 5 + 8 + 8 + + + PRI_6 + Priority of system handler + 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + SHCRS + SHCRS + System handler control and state + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active + bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active + bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active + bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active + bit + 10 + 1 + + + SYSTICKACT + SysTick exception active + bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending + bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception + pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending + bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable + bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status + register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + Instruction access violation + flag + 1 + 1 + + + MUNSTKERR + Memory manager fault on unstacking for a + return from exception + 3 + 1 + + + MSTKERR + Memory manager fault on stacking for + exception entry. + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + Memory Management Fault Address Register + (MMAR) valid flag + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return + from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception + entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state + preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid + flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage + fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage + fault + 18 + 1 + + + NOCP + No coprocessor usage + fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage + fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + MMFAR + Memory management fault + address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + BFAR + Bus fault address + 0 + 32 + + + + + AFSR + AFSR + Auxiliary fault status + register + 0x3C + 0x20 + read-write + 0x00000000 + + + IMPDEF + Implementation defined + 0 + 32 + + + + + + + NVIC_STIR + Nested vectored interrupt + controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt + register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt + ID + 0 + 9 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + CP + CP + 20 + 4 + + + + + + + SCB_ACTRL + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISMCYCINT + DISMCYCINT + 0 + 1 + + + DISDEFWBUF + DISDEFWBUF + 1 + 1 + + + DISFOLD + DISFOLD + 2 + 1 + + + DISFPCA + DISFPCA + 8 + 1 + + + DISOOFP + DISOOFP + 9 + 1 + + + + + + +