diff --git a/clashilator.cabal b/clashilator.cabal
--- a/clashilator.cabal
+++ b/clashilator.cabal
@@ -5,7 +5,7 @@
 -- see: https://github.com/sol/hpack
 
 name:           clashilator
-version:        0.1.1
+version:        0.1.2
 synopsis:       Automated Clash to Verilator bridge
 description:    Code generator and @Setup.hs@ hooks to generate a Verilator simulation and access it from Clash
 category:       Hardware, Development
@@ -42,8 +42,8 @@
       Cabal >=3.2.1 && <3.3
     , aeson >=1.5 && <1.6 || >=2.0 && <2.1
     , base >=4.14 && <5
-    , clash-ghc >=1.4.2 && <1.5
-    , clash-lib >=1.4.2 && <1.5
+    , clash-ghc >=1.4.2 && <1.5 || >=1.6.1 && <1.7
+    , clash-lib >=1.4.2 && <1.5 || >=1.6.1 && <1.7
     , containers
     , filepath
     , ghc
@@ -69,8 +69,8 @@
       Cabal >=3.2.1 && <3.3
     , aeson >=1.5 && <1.6 || >=2.0 && <2.1
     , base >=4.14 && <5
-    , clash-ghc >=1.4.2 && <1.5
-    , clash-lib >=1.4.2 && <1.5
+    , clash-ghc >=1.4.2 && <1.5 || >=1.6.1 && <1.7
+    , clash-lib >=1.4.2 && <1.5 || >=1.6.1 && <1.7
     , containers
     , filepath
     , ghc
diff --git a/src/Clash/Clashilator.hs b/src/Clash/Clashilator.hs
--- a/src/Clash/Clashilator.hs
+++ b/src/Clash/Clashilator.hs
@@ -94,6 +94,11 @@
     , "outputDir"    .= outputDir
     ]
   where
+#if MIN_VERSION_clash_lib(1, 6, 0)
+    inPorts = [ port | port@ManifestPort{..} <- ports, mpDirection `elem` [In, InOut] ]
+    outPorts = [ port | port@ManifestPort{..} <- ports, mpDirection `elem` [InOut, Out] ]
+#endif
+
     (clock, ins) = getClockAndInPorts clkName inPorts
     outs = [ Port mpName mpWidth | ManifestPort{..} <- outPorts ]