clash-vhdl 0.7.1 → 0.7.2

raw patch · 3 files changed

+6/−2 lines, 3 files

Files

CHANGELOG.md +4/−0
clash-vhdl.cabal +1/−1
src/CLaSH/Backend/VHDL.hs +1/−1

CHANGELOG.md view

@@ -1,5 +1,9 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.7.2 *April 25th 2017*+* New features:+  * Sum-of-product types: unused bits now "don't-care" [#212](https://github.com/clash-lang/clash-compiler/commit/fabf745793491ce3baf84ef0066b4ccf0753d503)+ ## 0.7.1 *April 11th 2017* * Fixes bugs:   * resize `Integer` multiplication result

clash-vhdl.cabal view

@@ -1,5 +1,5 @@ Name:                 clash-vhdl-Version:              0.7.1+Version:              0.7.2 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

src/CLaSH/Backend/VHDL.hs view

@@ -737,7 +737,7 @@     argExprs   = zipWith toSLV argTys es     extraArg   = case typeSize ty - dcSize of                    0 -> []-                   n -> [exprLit (Just (ty,n)) (NumLit 0)]+                   n -> [bits (replicate n U)]     assignExpr = "std_logic_vector'" <> parens (hcat $ punctuate " & " $ sequence (dcExpr:argExprs ++ extraArg))  expr_ _ (DataCon ty@(Sum _ _) (DC (_,i)) []) = "to_unsigned" <> tupled (sequence [int i,int (typeSize ty)])