diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,9 @@
 # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package
 
+## 0.6.1 *October 16th 2015*
+* New features:
+  * Support for `clash-prelude` 0.10.1
+
 ## 0.6 *October 3rd 2015*
 * New features:
   * Support `clash-prelude-0.10`
diff --git a/clash-vhdl.cabal b/clash-vhdl.cabal
--- a/clash-vhdl.cabal
+++ b/clash-vhdl.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-vhdl
-Version:              0.6
+Version:              0.6.1
 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -51,6 +51,7 @@
                       primitives/CLaSH.Prelude.ROM.File.json
                       primitives/CLaSH.Prelude.Testbench.json
                       primitives/CLaSH.Promoted.Nat.json
+                      primitives/CLaSH.Promoted.Nat.Unsafe.json
                       primitives/CLaSH.Promoted.Symbol.json
                       primitives/CLaSH.Signal.Bundle.json
                       primitives/CLaSH.Signal.Explicit.json
@@ -94,7 +95,7 @@
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
                       clash-lib               >= 0.6,
-                      clash-prelude           >= 0.10,
+                      clash-prelude           >= 0.10.1,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,
                       mtl                     >= 2.1.2,
diff --git a/primitives/CLaSH.Promoted.Nat.Unsafe.json b/primitives/CLaSH.Promoted.Nat.Unsafe.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Promoted.Nat.Unsafe.json
@@ -0,0 +1,7 @@
+[ { "BlackBox" :
+    { "name"      : "CLaSH.Promoted.Nat.Unsafe.unsafeSNat"
+    , "type"      : "CLaSH.Promoted.Nat.Unsafe.unsafeSNat :: Integer -> SNat k"
+    , "templateE" : "~LIT[0]"
+    }
+  }
+]
diff --git a/primitives/CLaSH.Promoted.Nat.json b/primitives/CLaSH.Promoted.Nat.json
--- a/primitives/CLaSH.Promoted.Nat.json
+++ b/primitives/CLaSH.Promoted.Nat.json
@@ -10,4 +10,28 @@
     , "templateE" : "~LIT[0]"
     }
   }
+, { "BlackBox" :
+    { "name"      : "CLaSH.Promoted.Nat.addSNat"
+    , "type"      : "CLaSH.Promoted.Nat.addSNat :: SNat a -> SNat b -> SNat (a + b)"
+    , "templateE" : "~LIT[0] + ~LIT[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "CLaSH.Promoted.Nat.subSNat"
+    , "type"      : "CLaSH.Promoted.Nat.subSNat :: SNat a -> SNat b -> SNat (a - b)"
+    , "templateE" : "~LIT[0] - ~LIT[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "CLaSH.Promoted.Nat.mulSNat"
+    , "type"      : "CLaSH.Promoted.Nat.mulSNat :: SNat a -> SNat b -> SNat (a * b)"
+    , "templateE" : "~LIT[0] * ~LIT[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "CLaSH.Promoted.Nat.powSNat"
+    , "type"      : "CLaSH.Promoted.Nat.powSNat :: SNat a -> SNat b -> SNat (a ^ b)"
+    , "templateE" : "~LIT[0] ** ~LIT[1]"
+    }
+  }
 ]
diff --git a/primitives/CLaSH.Sized.Vector.json b/primitives/CLaSH.Sized.Vector.json
--- a/primitives/CLaSH.Sized.Vector.json
+++ b/primitives/CLaSH.Sized.Vector.json
@@ -1,16 +1,4 @@
 [ { "BlackBox" :
-    { "name"      : "CLaSH.Sized.Vector.eq#"
-    , "type"      : "eq# :: Eq a => Vec n a -> Vec n a -> Bool"
-    , "templateE" : "~ARG[1] = ~ARG[2]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "CLaSH.Sized.Vector.neq#"
-    , "type"      : "neq# :: Eq a => Vec n a -> Vec n a -> Bool"
-    , "templateE" : "~ARG[1] /= ~ARG[2]"
-    }
-  }
-, { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.head"
     , "type"      : "head :: Vec (n + 1) a -> a"
     , "templateD" :
@@ -441,6 +429,52 @@
   end generate;
 end block;
 -- unconcatBitVector end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "CLaSH.Sized.Vector.rotateLeftS"
+    , "type"      : "rotateLeftS :: KnownNat n => Vec n a -> SNat d -> Vec n a"
+    , "templateD" :
+"-- rotateLeftS begin
+rotateLeftS_~SYM[0] : block
+  signal ~SYM[1] : ~TYP[1];
+  constant shift_amount_~SYM[2] : natural := ~LIT[2] mod ~LIT[0];
+begin
+  ~SYM[1] <= ~ARG[1];
+
+  no_shift : if shift_amount_~SYM[2] = 0 generate
+    ~RESULT <= ~SYM[1];
+  end generate;
+
+  do_shift : if shift_amount_~SYM[2] /= 0 generate
+    ~RESULT <= ~SYM[1](shift_amount_~SYM[2] to ~LIT[0]-1) &
+               ~SYM[1](0 to shift_amount_~SYM[2]-1);
+  end generate;
+end block;
+-- rotateLeftS end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "CLaSH.Sized.Vector.rotateRightS"
+    , "type"      : "rotateRightS :: KnownNat n => Vec n a -> SNat d -> Vec n a"
+    , "templateD" :
+"-- rotateRightS begin
+rotateLeftS_~SYM[0] : block
+  signal ~SYM[1] : ~TYP[1];
+  constant shift_amount_~SYM[2] : natural := ~LIT[2] mod ~LIT[0];
+begin
+  ~SYM[1] <= ~ARG[1];
+
+  no_shift : if shift_amount_~SYM[2] = 0 generate
+    ~RESULT <= ~SYM[1];
+  end generate;
+
+  do_shift : if shift_amount_~SYM[2] /= 0 generate
+    ~RESULT <= ~SYM[1](~LIT[0]-shift_amount_~SYM[2] to ~LIT[0]-1) &
+               ~SYM[1](0 to ~LIT[0]-shift_amount_~SYM[2]-1);
+  end generate;
+end block;
+-- rotateRightS end"
     }
   }
 ]
diff --git a/src/CLaSH/Backend/VHDL.hs b/src/CLaSH/Backend/VHDL.hs
--- a/src/CLaSH/Backend/VHDL.hs
+++ b/src/CLaSH/Backend/VHDL.hs
@@ -353,6 +353,7 @@
                               n -> "unsigned" <> parens (int (n -1) <+> "downto 0")
 vhdlType' t@(Product _ _) = tyName t
 vhdlType' Void            = "std_logic_vector" <> parens (int (-1) <+> "downto 0")
+vhdlType' String          = "string"
 
 sigDecl :: VHDLM Doc -> HWType -> VHDLM Doc
 sigDecl d t = d <+> colon <+> vhdlType t
@@ -410,6 +411,7 @@
 vhdlTypeErrValue (Reset _ _)         = "'X'"
 vhdlTypeErrValue (Clock _ _)         = "'X'"
 vhdlTypeErrValue Void                = "(0 downto 1 => 'X')"
+vhdlTypeErrValue String              = "\"ERROR\""
 
 decls :: [Declaration] -> VHDLM Doc
 decls [] = empty
@@ -434,15 +436,24 @@
 inst_ (Assignment id_ e) = fmap Just $
   text id_ <+> larrow <+> expr_ False e <> semi
 
-inst_ (CondAssignment id_ _ scrut es) = fmap Just $
+inst_ (CondAssignment id_ _ scrut _ [(Just (BoolLit b), l),(_,r)]) = fmap Just $
+  text id_ <+> larrow
+           <+> align (vsep (sequence [expr_ False t <+> "when" <+>
+                                      expr_ False scrut <+> "else"
+                                     ,expr_ False f <> semi
+                                     ]))
+  where
+    (t,f) = if b then (l,r) else (r,l)
+
+inst_ (CondAssignment id_ _ scrut scrutTy es) = fmap Just $
     "with" <+> parens (expr_ True scrut) <+> "select" <$>
       indent 2 (text id_ <+> larrow <+> align (vcat (punctuate comma (conds es)) <> semi))
   where
-    conds :: [(Maybe Expr,Expr)] -> VHDLM [Doc]
+    conds :: [(Maybe Literal,Expr)] -> VHDLM [Doc]
     conds []                = return []
     conds [(_,e)]           = expr_ False e <+> "when" <+> "others" <:> return []
     conds ((Nothing,e):_)   = expr_ False e <+> "when" <+> "others" <:> return []
-    conds ((Just c ,e):es') = expr_ False e <+> "when" <+> parens (expr_ True c) <:> conds es'
+    conds ((Just c ,e):es') = expr_ False e <+> "when" <+> patLit scrutTy c <:> conds es'
 
 inst_ (InstDecl nm lbl pms) = fmap Just $
     nest 2 $ text lbl <+> colon <+> "entity"
@@ -587,6 +598,19 @@
 exprLit _             (BitLit b)    = squotes $ bit_char b
 exprLit _             (StringLit s) = text . T.pack $ show s
 exprLit _             l             = error $ $(curLoc) ++ "exprLit: " ++ show l
+
+patLit :: HWType -> Literal -> VHDLM Doc
+patLit Integer (NumLit i) =
+  let integerLow  = -2^(31 :: Integer) :: Integer
+      integerHigh = 2^(31 :: Integer) - 1 :: Integer
+      i' = if i < integerLow
+              then integerLow
+              else if i > integerHigh
+                   then integerHigh
+                   else i
+  in  parenIf (i' < 0) (integer i')
+patLit hwTy (NumLit i) = bits (toBits (conSize hwTy) i)
+patLit _    l          = exprLit Nothing l
 
 toBits :: Integral a => Int -> a -> [Bit]
 toBits size val = map (\x -> if odd x then H else L)