clash-vhdl 0.6.6 → 0.6.7

raw patch · 4 files changed

+7/−3 lines, 4 files

Files

• CHANGELOG.md +4/−0
• clash-vhdl.cabal +1/−1
• primitives/CLaSH.Sized.Internal.BitVector.json +1/−1
• primitives/CLaSH.Sized.Vector.json +1/−1

@@ -1,5 +1,9 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.6.7+* Fixes bugs:+  * insufficient type-qualifiers for concatenation operator [#121](https://github.com/clash-lang/clash-compiler/issues/121)+ ## 0.6.6 *January 29th 2016* * New features:   * Support clash-lib-0.6.9

@@ -1,5 +1,5 @@ Name:                 clash-vhdl-Version:              0.6.6+Version:              0.6.7 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

@@ -25,7 +25,7 @@ , { "BlackBox" :     { "name"      : "CLaSH.Sized.Internal.BitVector.++#"     , "type"      : "(++#) :: KnownNat m => BitVector n -> BitVector m -> BitVector (n + m)"-    , "templateE" : "std_logic_vector'(~ARG[1]) & std_logic_vector'(~ARG[2])"+    , "templateE" : "std_logic_vector'(std_logic_vector'(~ARG[1]) & std_logic_vector'(~ARG[2]))"     }   } , { "BlackBox" :

@@ -81,7 +81,7 @@ , { "BlackBox" :     { "name"      : "CLaSH.Sized.Vector.++"     , "type"      : "(++) :: Vec n a -> Vec m a -> Vec (n + m) a"-    , "templateE" : "~TYPM[0]'(~ARG[0]) & ~TYPM[1]'(~ARG[1])"+    , "templateE" : "~TYPMO'(~TYPM[0]'(~ARG[0]) & ~TYPM[1]'(~ARG[1]))"     }   } , { "BlackBox" :