diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,6 +1,13 @@
 # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package
 
-## 0.6.5 *January 13th 2015*
+## 0.6.6 *January 29th 2016*
+* New features:
+  * Support clash-lib-0.6.9
+  * Support for `Debug.Trace.trace`, thanks to @ggreif
+* Fixes bugs:
+  * BlockRAM elements must be bit vectors [#113](https://github.com/clash-lang/clash-compiler/issues/113)
+
+## 0.6.5 *January 13th 2016*
 * New features:
   * Support for Haskell's: `Char`, `Int8`, `Int16`, `Int32`, `Int64`, `Word`, `Word8`, `Word16`, `Word32`, `Word64`.
   * Int/Word/Integer bitwidth for generated VHDL is configurable using the `-clash-intwidth=N` flag, where `N` can be either 32 or 64.
diff --git a/clash-vhdl.cabal b/clash-vhdl.cabal
--- a/clash-vhdl.cabal
+++ b/clash-vhdl.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-vhdl
-Version:              0.6.5
+Version:              0.6.6
 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -34,7 +34,7 @@
 License-file:         LICENSE
 Author:               Christiaan Baaij
 Maintainer:           Christiaan Baaij <christiaan.baaij@gmail.com>
-Copyright:            Copyright © 2015 University of Twente
+Copyright:            Copyright © 2015-2016 University of Twente
 Category:             Hardware
 Build-type:           Simple
 
@@ -61,7 +61,9 @@
                       primitives/CLaSH.Sized.Internal.Signed.json
                       primitives/CLaSH.Sized.Internal.Unsigned.json
                       primitives/CLaSH.Sized.Vector.json
+                      primitives/CLaSH.Transformations.json
                       primitives/Control.Exception.Base.json
+                      primitives/Debug.Trace.json
                       primitives/GHC.Base.json
                       primitives/GHC.Classes.json
                       primitives/GHC.CString.json
diff --git a/primitives/CLaSH.Prelude.BlockRam.json b/primitives/CLaSH.Prelude.BlockRam.json
--- a/primitives/CLaSH.Prelude.BlockRam.json
+++ b/primitives/CLaSH.Prelude.BlockRam.json
@@ -12,8 +12,19 @@
     , "templateD" :
 "-- blockRam begin
 blockRam_~COMPNAME_~SYM[0] : block
-  signal RAM_~SYM[1]  : ~TYP[2] := ~LIT[2];
-  signal dout_~SYM[2] : ~TYP[6];
+  type RamType is array(natural range <>) of std_logic_vector(~SIZE[~TYPO]-1 downto 0);
+
+  function init_to_bv (arg : in ~TYP[2]) return RamType is
+    variable RAM_init : RamType(0 to ~LENGTH[~TYP[2]]-1);
+  begin
+    for i in RAM_init'range loop
+      RAM_init(i) := ~TOBV[arg(i)][6];
+    end loop;
+    return RAM_init;
+  end function;
+
+  signal RAM_~SYM[1]  : RamType (0 to ~LENGTH[~TYP[2]]-1) := init_to_bv(~LIT[2]);
+  signal dout_~SYM[2] : std_logic_vector(~SIZE[~TYP[6]]-1 downto 0);
   signal wr_~SYM[3]   : integer range 0 to ~LIT[0] - 1;
   signal rd_~SYM[4]   : integer range 0 to ~LIT[0] - 1;
 begin
@@ -33,13 +44,13 @@
   begin
     if rising_edge(~CLK[1]) then
       if ~ARG[5] then
-        RAM_~SYM[1](wr_~SYM[3]) <= ~ARG[6];
+        RAM_~SYM[1](wr_~SYM[3]) <= ~TOBV[~ARG[6]][6];
       end if;
       dout_~SYM[2] <= RAM_~SYM[1](rd_~SYM[4]);
     end if;
   end process;
 
-  ~RESULT <= dout_~SYM[2];
+  ~RESULT <= ~FROMBVO[dout_~SYM[2]];
 end block;
 -- blockRam end"
     }
diff --git a/primitives/CLaSH.Transformations.json b/primitives/CLaSH.Transformations.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Transformations.json
@@ -0,0 +1,7 @@
+[ { "BlackBox" :
+    { "name"      : "CLaSH.Transformations.removedArg"
+    , "type"      : "removedArg :: a"
+    , "templateE" : "~ERRORO"
+    }
+  }
+]
diff --git a/primitives/Debug.Trace.json b/primitives/Debug.Trace.json
new file mode 100644
--- /dev/null
+++ b/primitives/Debug.Trace.json
@@ -0,0 +1,7 @@
+[ { "BlackBox" :
+    { "name"      : "Debug.Trace.trace"
+    , "type"      : "trace :: String -> a -> a"
+    , "templateE" : "~ARG[1]"
+    }
+  }
+]
diff --git a/src/CLaSH/Backend/VHDL.hs b/src/CLaSH/Backend/VHDL.hs
--- a/src/CLaSH/Backend/VHDL.hs
+++ b/src/CLaSH/Backend/VHDL.hs
@@ -1,3 +1,11 @@
+{-|
+  Copyright   :  (C) 2015-2016, University of Twente
+  License     :  BSD2 (see the file LICENSE)
+  Maintainer  :  Christiaan Baaij <christiaan.baaij@gmail.com>
+
+  Generate VHDL for assorted Netlist datatypes
+-}
+
 {-# LANGUAGE CPP               #-}
 {-# LANGUAGE OverloadedStrings #-}
 {-# LANGUAGE RecursiveDo       #-}
@@ -5,7 +13,6 @@
 {-# LANGUAGE TupleSections     #-}
 {-# LANGUAGE ViewPatterns      #-}
 
--- | Generate VHDL for assorted Netlist datatypes
 module CLaSH.Backend.VHDL (VHDLState) where
 
 import qualified Control.Applicative                  as A
@@ -68,6 +75,8 @@
   inst            = inst_
   expr            = expr_
   iwWidth         = use intWidth
+  toBV _ id_      = "toSLV" <> parens (text id_)
+  fromBV hty id_  = fromSLV hty id_ (typeSize hty - 1) 0
 
 type VHDLM a = State VHDLState a