clash-vhdl 0.6.14 → 0.6.15
raw patch · 4 files changed
+41/−7 lines, 4 files
Files
- CHANGELOG.md +5/−0
- clash-vhdl.cabal +1/−1
- primitives/CLaSH.Sized.Internal.Index.json +1/−1
- src/CLaSH/Backend/VHDL.hs +34/−5
CHANGELOG.md view
@@ -1,5 +1,10 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.6.15 *July 19th 2016*+* Fixes bugs:+ * Incorrect primitive for `Index`s `*#`+ * Incorrect handling of `Index`s `fromInteger#` and `maxBound#` primitives for values larger than 2^MACHINE_WIDTH+ ## 0.6.14 *July 15th 2016* * New features: * Support clash-lib-0.6.18
clash-vhdl.cabal view
@@ -1,5 +1,5 @@ Name: clash-vhdl-Version: 0.6.14+Version: 0.6.15 Synopsis: CAES Language for Synchronous Hardware - VHDL backend Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that
primitives/CLaSH.Sized.Internal.Index.json view
@@ -67,7 +67,7 @@ , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.Index.*#" , "type" : "(*#) :: KnownNat n => Index n -> Index n -> Index n"- , "templateE" : "resize(~ARG[1] * ~ARG[2], ~LIT[0])"+ , "templateE" : "resize(~ARG[1] * ~ARG[2], ~SIZE[~TYPO])" } } , { "BlackBox" :
src/CLaSH/Backend/VHDL.hs view
@@ -29,6 +29,7 @@ import Data.Text.Lazy (unpack) import qualified Data.Text.Lazy as T import Prelude hiding ((<$>))+import Text.Printf import Text.PrettyPrint.Leijen.Text.Monadic import CLaSH.Backend@@ -38,7 +39,7 @@ import CLaSH.Netlist.Id (mkBasicId') import CLaSH.Netlist.Types hiding (_intWidth, intWidth) import CLaSH.Netlist.Util hiding (mkBasicId)-import CLaSH.Util (curLoc, first, makeCached, on, (<:>))+import CLaSH.Util (clogBase, curLoc, first, makeCached, on, (<:>)) #ifdef CABAL import qualified Paths_clash_vhdl@@ -642,6 +643,21 @@ = exprLit (Just (BitVector (fromInteger n),fromInteger n)) i expr_ _ (BlackBoxE pNm _ bbCtx _)+ | pNm == "CLaSH.Sized.Internal.Index.fromInteger#"+ , [Literal _ (NumLit n), Literal _ i] <- extractLiterals bbCtx+ , Just k <- clogBase 2 n+ , let k' = max 1 k+ = exprLit (Just (Unsigned k',k')) i++expr_ _ (BlackBoxE pNm _ bbCtx _)+ | pNm == "CLaSH.Sized.Internal.Index.maxBound#"+ , [Literal _ (NumLit n)] <- extractLiterals bbCtx+ , n > 0+ , Just k <- clogBase 2 n+ , let k' = max 1 k+ = exprLit (Just (Unsigned k',k')) (NumLit (n-1))++expr_ _ (BlackBoxE pNm _ bbCtx _) | pNm == "GHC.Types.I#" , [Literal _ (NumLit n)] <- extractLiterals bbCtx = do iw <- use intWidth@@ -705,22 +721,27 @@ exprLit (Just (hty,sz)) (NumLit i) = case hty of Unsigned n | i < 2^(31 :: Integer) -> "to_unsigned" <> parens (integer i <> "," <> int n)- | otherwise -> "unsigned'" <> parens blit+ | otherwise -> "unsigned'" <> parens (if sz `mod` 4 == 0 then hlit else blit) Signed n | i < 2^(31 :: Integer) && i > (-2^(31 :: Integer)) -> "to_signed" <> parens (integer i <> "," <> int n)- | otherwise -> "signed'" <> parens blit- BitVector _ -> "std_logic_vector'" <> parens blit+ | otherwise -> "signed'" <> parens hlit+ BitVector _ -> "std_logic_vector'" <> parens (if sz `mod` 4 == 0 then hlit else blit) _ -> blit where blit = bits (toBits sz i)+ hlit = hex (toHex sz i) exprLit _ (BoolLit t) = if t then "true" else "false" exprLit _ (BitLit b) = squotes $ bit_char b exprLit _ (StringLit s) = text . T.pack $ show s exprLit _ l = error $ $(curLoc) ++ "exprLit: " ++ show l patLit :: HWType -> Literal -> VHDLM Doc-patLit hwTy (NumLit i) = bits (toBits (conSize hwTy) i)+patLit hwTy (NumLit i) =+ let sz = conSize hwTy+ in case sz `mod` 4 of+ 0 -> hex (toHex sz i)+ _ -> bits (toBits sz i) patLit _ l = exprLit Nothing l patMod :: HWType -> Literal -> Literal@@ -736,6 +757,14 @@ bits :: [Bit] -> VHDLM Doc bits = dquotes . hcat . mapM bit_char++toHex :: Int -> Integer -> String+toHex sz i =+ let Just d = clogBase 16 (2^sz)+ in printf ("%0" ++ show d ++ "X") i++hex :: String -> VHDLM Doc+hex s = char 'x' <> dquotes (text (T.pack s)) bit_char :: Bit -> VHDLM Doc bit_char H = char '1'