clash-vhdl 0.6.12 → 0.6.13

raw patch · 3 files changed

+11/−2 lines, 3 files

Files

CHANGELOG.md +4/−0
clash-vhdl.cabal +1/−1
src/CLaSH/Backend/VHDL.hs +6/−1

CHANGELOG.md view

@@ -1,5 +1,9 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.6.13 *June 9th 2016*+* Fixes bugs:+  * Converting product types to std_logic_vector fails when the `clash-hdlsyn Vivado` flag is enabled+ ## 0.6.12 *June 7th 2016* * Fixes bugs:   * Incorrect primitive specification for `snatToInteger` [#149](https://github.com/clash-lang/clash-compiler/issues/149)

clash-vhdl.cabal view

@@ -1,5 +1,5 @@ Name:                 clash-vhdl-Version:              0.6.12+Version:              0.6.13 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

src/CLaSH/Backend/VHDL.hs view

@@ -783,6 +783,9 @@     selIds   = map (fmap (\n -> Identifier n Nothing)) selNames toSLV (Product _ tys) (DataCon _ _ es) = do   encloseSep lparen rparen " & " (zipWithM toSLV tys es)+toSLV (Product _ _) e = do+  nm <- use modNm+  text (T.toLower $ T.pack nm) <> "_types.toSLV" <> parens (expr_ False e) toSLV (SP _ _) e = expr_ False e toSLV (Vector n elTy) (Identifier id_ Nothing) = do     selIds' <- sequence selIds@@ -795,7 +798,9 @@     selNames = map (fmap (displayT . renderOneLine) ) $ [text id_ <> parens (int i) | i <- [0 .. (n-1)]]     selIds   = map (fmap (`Identifier` Nothing)) selNames toSLV (Vector n elTy) (DataCon _ _ es) = parens $ vcat $ punctuate " & " (zipWithM toSLV [elTy,Vector (n-1) elTy] es)-toSLV (Vector _ _) e = "toSLV" <> parens (expr_ False e)+toSLV (Vector _ _) e = do+  nm <- use modNm+  text (T.toLower $ T.pack nm) <> "_types.toSLV" <> parens (expr_ False e) toSLV hty      e = error $ $(curLoc) ++  "toSLV: ty:" ++ show hty ++ "\n expr: " ++ show e  fromSLV :: HWType -> Identifier -> Int -> Int -> VHDLM Doc