clash-vhdl 0.6.10 → 0.6.11

raw patch · 3 files changed

+32/−8 lines, 3 filesPVP ok

version bump matches the API change (PVP)

API changes (from Hackage documentation)

Files

• CHANGELOG.md +5/−0
• clash-vhdl.cabal +1/−1
• primitives/CLaSH.Sized.Internal.BitVector.json +26/−7

@@ -1,5 +1,10 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.6.11 *April 7th 2016*+* Fixes bugs:+  * Incorrect primitives for `BitVector`s `quot#` and `rem#`+  * Bit indexing and replacement primitives fail to synthesise in Synopsis tools+ ## 0.6.10 *March 15th 2016* * Fixes bugs:   * XST cannot finds "_types" package unless it is prefixed with "work." [#133](https://github.com/clash-lang/clash-compiler/pull/133)

@@ -1,5 +1,5 @@ Name:                 clash-vhdl-Version:              0.6.10+Version:              0.6.11 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

@@ -145,7 +145,7 @@   -- pragma translate_on                ; -  ~RESULT <= ~ARG[1](~SYM[1] downto ~SYM[1]);+  ~RESULT(0) <= ~ARG[1](~SYM[1]); end block;~ELSE ~SYM[0] : block   signal ~GENSYM[bv][2] : ~TYP[1];@@ -158,7 +158,7 @@   -- pragma translate_on                ; -  ~RESULT <= ~SYM[2](~SYM[1] downto ~SYM[1]);+  ~RESULT(0) <= ~SYM[2](~SYM[1]); end block;~FI -- indexBitVector end"     }@@ -172,7 +172,7 @@              -> Bit         -- ARG[3]              -> BitVector n"     , "templateD" :-"-- replaceBit begin+"-- replaceBit begin~IF ~ISVAR[3] ~THEN ~GENSYM[replaceBit][0] : block   signal ~GENSYM[vec_index][1] : integer range 0 to ~LIT[0]-1; begin@@ -186,10 +186,29 @@     variable ~GENSYM[ivec][2] : ~TYP[1];   begin     ~SYM[2] := ~ARG[1];-    ~SYM[2](~SYM[1] downto ~SYM[1]) := ~ARG[3];+    ~SYM[2](~SYM[1]) := ~ARG[3](0);     ~RESULT <= ~SYM[2];   end process;-end block;+end block;~ELSE+~SYM[0] : block+  signal ~SYM[1] : integer range 0 to ~LIT[0]-1;+  signal ~GENSYM[b][3] : ~TYP[3];+begin+  ~SYM[1] <= to_integer(~ARG[2])+  -- pragma translate_off+               mod ~LIT[0]+  -- pragma translate_on+               ;+  ~SYM[3] <= ~ARG[3];++  process(~SYM[1],~SYM[3]~VARS[1])+    variable ~SYM[2] : ~TYP[1];+  begin+    ~SYM[2] := ~ARG[1];+    ~SYM[2](~SYM[1]) := ~SYM[3](0);+    ~RESULT <= ~SYM[2];+  end process;+end block;~FI -- replaceBit end"     }   }@@ -404,13 +423,13 @@ , { "BlackBox" :     { "name"      : "CLaSH.Sized.Internal.BitVector.quot#"     , "type"      : "quot# :: BitVector n -> BitVector n -> BitVector n"-    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) / unsigned(~ARG[2]))"+    , "templateE" : "std_logic_vector(unsigned(~ARG[0]) / unsigned(~ARG[1]))"     }   } , { "BlackBox" :     { "name"      : "CLaSH.Sized.Internal.BitVector.rem#"     , "type"      : "rem# :: BitVector n -> BitVector n -> BitVector n"-    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) rem unsigned(~ARG[2]))"+    , "templateE" : "std_logic_vector(unsigned(~ARG[0]) rem unsigned(~ARG[1]))"     }   } , { "BlackBox" :