clash-vhdl 0.5.9 → 0.5.10

raw patch · 3 files changed

+6/−1 lines, 3 filesPVP ok

version bump matches the API change (PVP)

API changes (from Hackage documentation)

Files

CHANGELOG.md +4/−0
clash-vhdl.cabal +1/−1
src/CLaSH/Backend/VHDL.hs +1/−0

CHANGELOG.md view

@@ -1,5 +1,9 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.5.10 *September 8th 2015*+* Fixes bugs:+  * Maybe (Index n) not translatable to VHDL [#75](https://github.com/clash-lang/clash-compiler/issues/75)+ ## 0.5.9 *September 7th 2015* * Fixes bugs:   * Bug in VHDL ROM generation [#69](https://github.com/clash-lang/clash-compiler/issues/69)

clash-vhdl.cabal view

@@ -1,5 +1,5 @@ Name:                 clash-vhdl-Version:              0.5.9+Version:              0.5.10 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

src/CLaSH/Backend/VHDL.hs view

@@ -599,6 +599,7 @@ toSLV (BitVector _) e = expr_ False e toSLV (Signed _)   e = "std_logic_vector" <> parens (expr_ False e) toSLV (Unsigned _) e = "std_logic_vector" <> parens (expr_ False e)+toSLV (Index _)    e = "std_logic_vector" <> parens (expr_ False e) toSLV (Sum _ _)    e = "std_logic_vector" <> parens (expr_ False e) toSLV t@(Product _ tys) (Identifier id_ Nothing) = do     selIds' <- sequence selIds