clash-vhdl 0.5.8 → 0.5.9

raw patch · 5 files changed

+69/−15 lines, 5 filesPVP: major bump suggested

API removals or changes: PVP suggests a major version bump

API changes (from Hackage documentation)

Files

• CHANGELOG.md +7/−0
• README.md +27/−3
• clash-vhdl.cabal +28/−5
• primitives/CLaSH.Prelude.ROM.json +2/−2
• primitives/CLaSH.Sized.Internal.Signed.json +5/−5

@@ -1,5 +1,12 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.5.9 *September 7th 2015*+* Fixes bugs:+  * Bug in VHDL ROM generation [#69](https://github.com/clash-lang/clash-compiler/issues/69)+  * Fix asyncRom VHDL primitive [#71](https://github.com/clash-lang/clash-compiler/pull/71)+  * Fix primitive for CLaSH.Sized.Internal.Signed.size# [#72](https://github.com/clash-lang/clash-compiler/pull/72)+  * rem and quot on Signed are broken [#73](https://github.com/clash-lang/clash-compiler/issues/73)+ ## 0.5.8 *July 9th 2015* * New features:   * Generate VHDL-93 instead of VHDL-2002, the VHDL-93 standard is supported by a larger range of tools

@@ -1,5 +1,29 @@-# Support-For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the [forum](https://groups.google.com/d/forum/clash-language)+# `clash-vhdl` - VHDL backend for the CλaSH compiler -# `clash-vhdl`   * See the LICENSE file for license and copyright details++# CλaSH - A functional hardware description language+CλaSH (pronounced ‘clash’) is a functional hardware description language that+borrows both its syntax and semantics from the functional programming language+Haskell. The CλaSH compiler transforms these high-level descriptions to+low-level synthesizable VHDL, Verilog, or SystemVerilog.++Features of CλaSH:++  * Strongly typed (like VHDL), yet with a very high degree of type inference,+    which enables both safe and fast prototying using consise descriptions (like+    Verilog)++  * Interactive REPL: load your designs in an interpreter and easily test all+    your component without needing to setup a test bench.++  * Higher-order functions, with type inference, result in designs that are+    fully parametric by default.++  * Synchronous sequential circuit design based on streams of values, called+    `Signal`s.++  * Support for multiple clock domains, with type safe clock domain crossing.++# Support+For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the [forum](https://groups.google.com/d/forum/clash-language)

@@ -1,14 +1,30 @@ Name:                 clash-vhdl-Version:              0.5.8+Version:              0.5.9 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that   borrows both its syntax and semantics from the functional programming language-  Haskell. The merits of using a functional language to describe hardware comes-  from the fact that combinational circuits can be directly modelled as-  mathematical functions and that functional languages lend themselves very well-  at describing and (de-)composing mathematical functions.+  Haskell. The CλaSH compiler transforms these high-level descriptions to+  low-level synthesizable VHDL, Verilog, or SystemVerilog.   .+  Features of CλaSH:+  .+  * Strongly typed (like VHDL), yet with a very high degree of type inference,+    which enables both safe and fast prototying using consise descriptions (like+    Verilog)+  .+  * Interactive REPL: load your designs in an interpreter and easily test all+    your component without needing to setup a test bench.+  .+  * Higher-order functions, with type inference, result in designs that are+    fully parametric by default.+  .+  * Synchronous sequential circuit design based on streams of values, called+    @Signal@s.+  .+  * Support for multiple clock domains, with type safe clock domain crossing.+  .+  .   This package provides:   .   * VHDL Backend@@ -68,6 +84,13 @@   default-language:   Haskell2010   ghc-options:        -Wall   CPP-Options:        -DCABAL++  other-extensions:   CPP+                      OverloadedStrings+                      RecursiveDo+                      TemplateHaskell+                      TupleSections+                      ViewPatterns    Build-depends:      base                    >= 4.6.0.1 && < 5,                       clash-lib               >= 0.5.8,

@@ -11,7 +11,7 @@   signal ROM       : ~TYP[1];   signal rom_index : integer range 0 to ~LIT[0]-1; begin-  ROM <= ARG[1];+  ROM <= ~ARG[1];    rom_index <= ~ARG[2]   -- pragma translate_off@@ -47,7 +47,7 @@   -- pragma translate_on         ; -  rom : process (~CLK[1])+  romSync : process (~CLK[1])   begin     if (rising_edge(~CLK[1])) then       dout <= ROM(rd);

@@ -1,5 +1,5 @@ [ { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Internal.Signed.size#"+    { "name"      : "CLaSH.Sized.Internal.Signed.size#"     , "type"      : "size# :: KnownNat n => Signed n -> Int"     , "templateE" : "~LIT[0]"     }@@ -124,14 +124,14 @@   } , { "BlackBox" :     { "name"      : "CLaSH.Sized.Internal.Signed.quot#"-    , "type"      : "quot# :: KnownNat n => Signed n -> Signed n -> Signed n"-    , "templateE" : "~ARG[1] / ~ARG[2]"+    , "type"      : "quot# :: Signed n -> Signed n -> Signed n"+    , "templateE" : "~ARG[0] / ~ARG[1]"     }   } , { "BlackBox" :     { "name"      : "CLaSH.Sized.Internal.Signed.rem#"-    , "type"      : "rem# :: KnownNat n => Signed n -> Signed n -> Signed n"-    , "templateE" : "~ARG[1] rem ~ARG[2]"+    , "type"      : "rem# :: Signed n -> Signed n -> Signed n"+    , "templateE" : "~ARG[0] rem ~ARG[1]"     }   } , { "BlackBox" :