clash-vhdl 0.5.7.1 → 0.5.8

raw patch · 6 files changed

+20/−16 lines, 6 filesPVP ok

version bump matches the API change (PVP)

API changes (from Hackage documentation)

Files

• CHANGELOG.md +4/−0
• clash-vhdl.cabal +1/−1
• primitives/CLaSH.Prelude.BlockRam.File.json +4/−4
• primitives/CLaSH.Prelude.RAM.json +2/−2
• primitives/CLaSH.Prelude.ROM.File.json +8/−8
• src/CLaSH/Backend/VHDL.hs +1/−1

@@ -1,5 +1,9 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.5.8 *July 9th 2015*+* New features:+  * Generate VHDL-93 instead of VHDL-2002, the VHDL-93 standard is supported by a larger range of tools+ ## 0.5.7.1 *June 26th 2015* * Support for `genStmt` backend method 

@@ -1,5 +1,5 @@ Name:                 clash-vhdl-Version:              0.5.7.1+Version:              0.5.8 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

@@ -13,21 +13,21 @@     , "templateD" : "-- blockRamFile begin blockRamFile_~COMPNAME_~SYM[0] : block-  type RamType is array(0 to ~LIT[2]-1) of bit_vector(~LIT[0]-1 downto 0);+  type RamType is array(natural range <>) of bit_vector(~LIT[0]-1 downto 0);    impure function InitRamFromFile (RamFileName : in string) return RamType is     FILE RamFile : text open read_mode is RamFileName;     variable RamFileLine : line;-    variable RAM : RamType;+    variable RAM : RamType(0 to ~LIT[2]-1);   begin-    for i in RamType'range loop+    for i in RAM'range loop       readline(RamFile,RamFileLine);       read(RamFileLine,RAM(i));     end loop;     return RAM;   end function; -  signal RAM  : RamType := InitRamFromFile(~FILE[~LIT[3]]);+  signal RAM  : RamType(0 to ~LIT[2]-1) := InitRamFromFile(~FILE[~LIT[3]]);   signal dout : ~TYP[7];   signal wr   : integer range 0 to ~LIT[2]-1;   signal rd   : integer range 0 to ~LIT[2]-1;

@@ -12,8 +12,8 @@     , "templateD" : "-- asyncRam begin asyncRam_~COMPNAME_~SYM[0] : block-  type RamType is array(0 to ~LIT[2]-1) of ~TYP[6];-  signal RAM : RamType;+  type RamType is array(natural range <>) of ~TYP[6];+  signal RAM : RamType(0 to ~LIT[2]-1);   signal wr  : integer range 0 to ~LIT[2] - 1;   signal rd  : integer range 0 to ~LIT[2] - 1; begin

@@ -9,21 +9,21 @@     , "templateD" : "-- asyncRomFile begin asyncROMFile_~SYM[0] : block-  type RomType is array(0 to ~LIT[1]-1) of bit_vector(~LIT[0]-1 downto 0);+  type RomType is array(natural range <>) of bit_vector(~LIT[0]-1 downto 0);    impure function InitRomFromFile (RomFileName : in string) return RomType is     FILE RomFile : text open read_mode is RomFileName;     variable RomFileLine : line;-    variable ROM : RomType;+    variable ROM : RomType(0 to ~LIT[1]-1);   begin-    for i in RomType'range loop+    for i in ROM'range loop       readline(RomFile,RomFileLine);       read(RomFileLine,ROM(i));     end loop;     return ROM;   end function; -  signal ROM : RomType := InitRomFromFile(~FILE[~LIT[2]]);+  signal ROM : RomType(0 to ~LIT[1]-1) := InitRomFromFile(~FILE[~LIT[2]]);   signal rd  : integer range 0 to ~LIT[1]-1; begin   rd <= ~ARG[3]@@ -49,21 +49,21 @@     , "templateD" : "-- romFile begin romFile_~COMPNAME_~SYM[0] : block-  type RomType is array(0 to ~LIT[2]-1) of bit_vector(~LIT[0]-1 downto 0);+  type RomType is array(natural range <>) of bit_vector(~LIT[0]-1 downto 0);    impure function InitRomFromFile (RomFileName : in string) return RomType is     FILE RomFile : text open read_mode is RomFileName;     variable RomFileLine : line;-    variable ROM : RomType;+    variable ROM : RomType(0 to ~LIT[2]-1);   begin-    for i in RomType'range loop+    for i in ROM'range loop       readline(RomFile,RomFileLine);       read(RomFileLine,ROM(i));     end loop;     return ROM;   end function; -  signal ROM  : RomType := InitRomFromFile(~FILE[~LIT[3]]);+  signal ROM  : RomType(0 to ~LIT[2]-1) := InitRomFromFile(~FILE[~LIT[3]]);   signal rd   : integer range 0 to ~LIT[2]-1;   signal dout : ~TYPO; begin

@@ -74,7 +74,7 @@ genVHDL modName c = (unpack cName,) A.<$> vhdl   where     cName   = componentName c-    vhdl    = "-- Automatically generated VHDL-2002" <$$>+    vhdl    = "-- Automatically generated VHDL-93" <$$>               tyImports modName <$$> linebreak <>               entity c <$$> linebreak <>               architecture c