clash-vhdl 0.5.4 → 0.5.5
raw patch · 4 files changed
+27/−19 lines, 4 filesdep ~clash-libdep ~clash-preludePVP ok
version bump matches the API change (PVP)
Dependency ranges changed: clash-lib, clash-prelude
API changes (from Hackage documentation)
Files
- CHANGELOG.md +6/−1
- clash-vhdl.cabal +3/−3
- primitives/CLaSH.Sized.Vector.json +2/−2
- src/CLaSH/Backend/VHDL.hs +16/−13
CHANGELOG.md view
@@ -1,6 +1,11 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package -## 0.5.4+## 0.5.5 *June 3rd 2015*+* New features:+ * Compile against `clash-lib-0.5.6`+ * Generated component names are prefixed by the name of the module containing the `topEntity`++## 0.5.4 *May 10th 2015* * New features: * Make VHDL 'assert' primitive GHDL friendly * Generate smarter labels for `register` and `blockRam` blackboxes to make finding longest paths easier
clash-vhdl.cabal view
@@ -1,5 +1,5 @@ Name: clash-vhdl-Version: 0.5.4+Version: 0.5.5 Synopsis: CAES Language for Synchronous Hardware - VHDL backend Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -66,8 +66,8 @@ CPP-Options: -DCABAL Build-depends: base >= 4.6.0.1 && < 5,- clash-lib >= 0.5.4,- clash-prelude >= 0.7.2,+ clash-lib >= 0.5.6,+ clash-prelude >= 0.8, fgl >= 5.4.2.4, lens >= 3.9.2, mtl >= 2.1.2,
primitives/CLaSH.Sized.Vector.json view
@@ -351,7 +351,7 @@ concatBitVectorSN_~SYM[3] : if ~RESULT'length /= 0 generate concatBitVectorIter_~SYM[4] : for ~SYM[5] in ~SYM[1]'range generate- ~RESULT(((~SYM[5] * ~LIT[0]) + ~LIT[0] - 1) downto (~SYM[5] * ~LIT[0])) <= ~TYPMO(~SYM[1](~SYM[5]));+ ~RESULT(((~SYM[5] * ~LIT[0]) + ~LIT[0] - 1) downto (~SYM[5] * ~LIT[0])) <= ~TYPMO(~SYM[1](~SYM[1]'high - ~SYM[5])); end generate; end generate; end block;"@@ -375,7 +375,7 @@ unconcatBitVectorSN_~SYM[3] : if ~SYM[1]'length /= 0 generate unconcatBitVectorIter_~SYM[4] : for ~SYM[5] in ~RESULT'range generate- ~RESULT(~SYM[5]) <= ~SYM[1](((~SYM[5] * ~LIT[1]) + ~LIT[1] - 1) downto (~SYM[5] * ~LIT[1]));+ ~RESULT(~RESULT'high - ~SYM[5]) <= ~SYM[1](((~SYM[5] * ~LIT[1]) + ~LIT[1] - 1) downto (~SYM[5] * ~LIT[1])); end generate; end generate; end block;"
src/CLaSH/Backend/VHDL.hs view
@@ -69,28 +69,30 @@ type VHDLM a = State VHDLState a -- | Generate VHDL for a Netlist component-genVHDL :: Component -> VHDLM (String,Doc)-genVHDL c = (unpack cName,) A.<$> vhdl+genVHDL :: String -> Component -> VHDLM (String,Doc)+genVHDL modName c = (unpack cName,) A.<$> vhdl where cName = componentName c- vhdl = "-- Automatically generated VHDL" <$$>- tyImports <$$> linebreak <>+ vhdl = "-- Automatically generated VHDL-2002" <$$>+ tyImports modName <$$> linebreak <> entity c <$$> linebreak <> architecture c -- | Generate a VHDL package containing type definitions for the given HWTypes-mkTyPackage_ :: [HWType]- -> VHDLM Doc-mkTyPackage_ hwtys =+mkTyPackage_ :: String+ -> [HWType]+ -> VHDLM [(String,Doc)]+mkTyPackage_ modName hwtys = (:[]) A.<$> (modName ++ "_types",) A.<$> "library IEEE;" <$> "use IEEE.STD_LOGIC_1164.ALL;" <$> "use IEEE.NUMERIC_STD.ALL;" <$$> linebreak <>- "package" <+> "types" <+> "is" <$>+ "package" <+> modNameD <> "_types" <+> "is" <$> indent 2 ( packageDec <$> vcat (sequence funDecs) ) <$> "end" <> semi <> packageBodyDec where+ modNameD = text (T.pack modName) usedTys = concatMap mkUsedTys hwtys needsDec = nubBy eqReprTy . map mkVecZ $ (hwtys ++ usedTys) hwTysSorted = topSortHWTys needsDec@@ -101,7 +103,7 @@ packageBodyDec = case funBodies of [] -> empty _ -> linebreak <$>- "package" <+> "body" <+> "types" <+> "is" <$>+ "package" <+> "body" <+> modNameD <> "_types" <+> "is" <$> indent 2 (vcat (sequence funBodies)) <$> "end" <> semi @@ -293,15 +295,15 @@ "end" <> semi ) -tyImports :: VHDLM Doc-tyImports =+tyImports :: String -> VHDLM Doc+tyImports modName = punctuate' semi $ sequence [ "library IEEE" , "use IEEE.STD_LOGIC_1164.ALL" , "use IEEE.NUMERIC_STD.ALL" , "use IEEE.MATH_REAL.ALL" , "use work.all"- , "use work.types.all"+ , "use work." <> text (T.pack modName) <> "_types.all" ] @@ -442,7 +444,7 @@ inst_ (Assignment id_ e) = fmap Just $ text id_ <+> larrow <+> expr_ False e <> semi -inst_ (CondAssignment id_ scrut es) = fmap Just $+inst_ (CondAssignment id_ _ scrut es) = fmap Just $ "with" <+> parens (expr_ True scrut) <+> "select" <$> indent 2 (text id_ <+> larrow <+> align (vcat (punctuate comma (conds es)) <> semi)) where@@ -563,6 +565,7 @@ Unsigned _ -> "unsigned'" <> parens blit Signed _ -> "signed'" <> parens blit BitVector _ -> "std_logic_vector'" <> parens blit+ Integer -> integer i _ -> blit where