diff --git a/CHANGELOG.md b/CHANGELOG.md --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,12 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.5.3 *May 1st 2015* +* New features: + * Support wrapper generation + +* Fixes bugs: + * Incorrect primitives for BitVector `minBound` and `maxBound` + ## 0.5.2 *April 24th 2015* * Fixes bugs: * Fix bug where not enough array type definitions were created diff --git a/clash-vhdl.cabal b/clash-vhdl.cabal --- a/clash-vhdl.cabal +++ b/clash-vhdl.cabal @@ -1,5 +1,5 @@ Name: clash-vhdl -Version: 0.5.2 +Version: 0.5.3 Synopsis: CAES Language for Synchronous Hardware - VHDL backend Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that @@ -26,6 +26,7 @@ CHANGELOG.md Data-files: primitives/CLaSH.Driver.TestbenchGen.json + primitives/CLaSH.Driver.TopWrapper.json primitives/CLaSH.GHC.GHC2Core.json primitives/CLaSH.Prelude.BlockRam.json primitives/CLaSH.Prelude.Testbench.json diff --git a/primitives/CLaSH.Driver.TopWrapper.json b/primitives/CLaSH.Driver.TopWrapper.json new file mode 100644 --- /dev/null +++ b/primitives/CLaSH.Driver.TopWrapper.json @@ -0,0 +1,24 @@ +[ { "BlackBox" : + { "name" : "CLaSH.TopWrapper.syncReset" + , "templateD" : +"-- reset ~RESULT is asynchronously asserted, but synchronously de-asserted +resetSync_~SYM[0] : block + signal ~SYM[1] : ~TYP[0]; + signal ~SYM[2] : ~TYP[0]; +begin + process(~CLKO,~ARG[0]) + begin + if ~ARG[0] = '0' then + ~SYM[1] <= '0'; + ~SYM[2] <= '0'; + elsif rising_edge(~CLKO) then + ~SYM[1] <= '1'; + ~SYM[2] <= ~SYM[1]; + end if; + end process; + + ~RESULT <= ~SYM[2]; +end block;" + } + } +] diff --git a/primitives/CLaSH.Sized.Internal.BitVector.json b/primitives/CLaSH.Sized.Internal.BitVector.json --- a/primitives/CLaSH.Sized.Internal.BitVector.json +++ b/primitives/CLaSH.Sized.Internal.BitVector.json @@ -330,14 +330,14 @@ { "name" : "CLaSH.Sized.Internal.BitVector.minBound#" , "type" : "minBound# :: KnownNat n => BitVector n" , "comment" : "Generates incorrect VDHL for n=0" - , "templateE" : "std_logic_vector'(~LIT[0]-1 downto 0 => '0');" + , "templateE" : "std_logic_vector'(~LIT[0]-1 downto 0 => '0')" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.BitVector.maxBound#" , "type" : "maxBound# :: KnownNat n => BitVector n" , "comment" : "Generates incorrect VDHL for n=0" - , "templateE" : "std_logic_vector'(~LIT[0]-1 downto 0 => '1');" + , "templateE" : "std_logic_vector'(~LIT[0]-1 downto 0 => '1')" } } , { "BlackBox" : diff --git a/src/CLaSH/Backend/VHDL.hs b/src/CLaSH/Backend/VHDL.hs --- a/src/CLaSH/Backend/VHDL.hs +++ b/src/CLaSH/Backend/VHDL.hs @@ -318,12 +318,12 @@ "end" <> semi where ports l = sequence - $ [ (,fromIntegral $ T.length i) A.<$> (fill l (text i) <+> colon <+> "in" <+> vhdlType ty) + $ [ (,fromIntegral $ T.length i) A.<$> (encodingNote ty <$> fill l (text i) <+> colon <+> "in" <+> vhdlType ty) | (i,ty) <- inputs c ] ++ - [ (,fromIntegral $ T.length i) A.<$> (fill l (text i) <+> colon <+> "in" <+> vhdlType ty) + [ (,fromIntegral $ T.length i) A.<$> (encodingNote ty <$> fill l (text i) <+> colon <+> "in" <+> vhdlType ty) | (i,ty) <- hiddenPorts c ] ++ - [ (,fromIntegral $ T.length (fst $ output c)) A.<$> (fill l (text (fst $ output c)) <+> colon <+> "out" <+> vhdlType (snd $ output c)) - ] + [ (,fromIntegral $ T.length i) A.<$> (encodingNote ty <$> fill l (text i) <+> colon <+> "out" <+> vhdlType ty) + | (i,ty) <- outputs c ] architecture :: Component -> VHDLM Doc architecture c = @@ -343,8 +343,8 @@ vhdlType' :: HWType -> VHDLM Doc vhdlType' Bool = "boolean" -vhdlType' (Clock _) = "std_logic" -vhdlType' (Reset _) = "std_logic" +vhdlType' (Clock _ _) = "std_logic" +vhdlType' (Reset _ _) = "std_logic" vhdlType' Integer = "integer" vhdlType' (BitVector n) = case n of 0 -> "std_logic_vector (0 downto 1)" @@ -372,8 +372,8 @@ vhdlTypeMark' hwty where vhdlTypeMark' Bool = "boolean" - vhdlTypeMark' (Clock _) = "std_logic" - vhdlTypeMark' (Reset _) = "std_logic" + vhdlTypeMark' (Clock _ _) = "std_logic" + vhdlTypeMark' (Reset _ _) = "std_logic" vhdlTypeMark' Integer = "integer" vhdlTypeMark' (BitVector _) = "std_logic_vector" vhdlTypeMark' (Index _) = "unsigned" @@ -388,6 +388,8 @@ tyName :: HWType -> VHDLM Doc tyName Integer = "integer" tyName Bool = "boolean" +tyName (Clock _ _) = "std_logic" +tyName (Reset _ _) = "std_logic" tyName (Vector n elTy) = "array_of_" <> int n <> "_" <> tyName elTy tyName (BitVector n) = "std_logic_vector_" <> int n tyName t@(Index _) = "unsigned_" <> int (typeSize t) @@ -413,8 +415,8 @@ vhdlTypeErrValue (SP _ _) = "(others => 'X')" vhdlTypeErrValue (Sum _ _) = "(others => 'X')" vhdlTypeErrValue (Product _ elTys) = tupled $ mapM vhdlTypeErrValue elTys -vhdlTypeErrValue (Reset _) = "'X'" -vhdlTypeErrValue (Clock _) = "'X'" +vhdlTypeErrValue (Reset _ _) = "'X'" +vhdlTypeErrValue (Clock _ _) = "'X'" vhdlTypeErrValue Void = "(0 downto 1 => 'X')" decls :: [Declaration] -> VHDLM Doc @@ -479,6 +481,7 @@ end = start - argSize + 1 expr_ _ (Identifier id_ (Just (Indexed (ty@(Product _ _),_,fI)))) = text id_ <> dot <> tyName ty <> "_sel" <> int fI +expr_ _ (Identifier id_ (Just (Indexed ((Vector _ _),_,fI)))) = text id_ <> parens (int fI) expr_ _ (Identifier id_ (Just (DC (ty@(SP _ _),_)))) = text id_ <> parens (int start <+> "downto" <+> int end) where start = typeSize ty - 1 @@ -650,3 +653,8 @@ punctuate' :: Monad m => m Doc -> m [Doc] -> m Doc punctuate' s d = vcat (punctuate s d) <> s + +encodingNote :: HWType -> VHDLM Doc +encodingNote (Clock _ _) = "-- clock" +encodingNote (Reset _ _) = "-- asynchronous reset: active low" +encodingNote _ = empty